/*******************************************************************************
* File Name: cydevicegnu.inc
* OBSOLETE: Do not use this file. Use the _trm version instead.
* PSoC Creator  4.4
*
* Description:
* This file provides all of the address values for the entire PSoC device.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright (c) 2007-2020 Cypress Semiconductor.  All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, 
* disclaimers, and limitations in the end user license agreement accompanying 
* the software package with which this file was provided.
********************************************************************************/

.set CYDEV_FLASH_BASE, 0x00000000
.set CYDEV_FLASH_SIZE, 0x00040000
.set CYDEV_FLASH_DATA_MBASE, 0x00000000
.set CYDEV_FLASH_DATA_MSIZE, 0x00040000
.set CYDEV_SRAM_BASE, 0x1fff8000
.set CYDEV_SRAM_SIZE, 0x00010000
.set CYDEV_SRAM_CODE64K_MBASE, 0x1fff8000
.set CYDEV_SRAM_CODE64K_MSIZE, 0x00004000
.set CYDEV_SRAM_CODE32K_MBASE, 0x1fffc000
.set CYDEV_SRAM_CODE32K_MSIZE, 0x00002000
.set CYDEV_SRAM_CODE16K_MBASE, 0x1fffe000
.set CYDEV_SRAM_CODE16K_MSIZE, 0x00001000
.set CYDEV_SRAM_CODE_MBASE, 0x1fff8000
.set CYDEV_SRAM_CODE_MSIZE, 0x00008000
.set CYDEV_SRAM_DATA_MBASE, 0x20000000
.set CYDEV_SRAM_DATA_MSIZE, 0x00008000
.set CYDEV_SRAM_DATA16K_MBASE, 0x20001000
.set CYDEV_SRAM_DATA16K_MSIZE, 0x00001000
.set CYDEV_SRAM_DATA32K_MBASE, 0x20002000
.set CYDEV_SRAM_DATA32K_MSIZE, 0x00002000
.set CYDEV_SRAM_DATA64K_MBASE, 0x20004000
.set CYDEV_SRAM_DATA64K_MSIZE, 0x00004000
.set CYDEV_DMA_BASE, 0x20008000
.set CYDEV_DMA_SIZE, 0x00008000
.set CYDEV_DMA_SRAM64K_MBASE, 0x20008000
.set CYDEV_DMA_SRAM64K_MSIZE, 0x00004000
.set CYDEV_DMA_SRAM32K_MBASE, 0x2000c000
.set CYDEV_DMA_SRAM32K_MSIZE, 0x00002000
.set CYDEV_DMA_SRAM16K_MBASE, 0x2000e000
.set CYDEV_DMA_SRAM16K_MSIZE, 0x00001000
.set CYDEV_DMA_SRAM_MBASE, 0x2000f000
.set CYDEV_DMA_SRAM_MSIZE, 0x00001000
.set CYDEV_CLKDIST_BASE, 0x40004000
.set CYDEV_CLKDIST_SIZE, 0x00000110
.set CYDEV_CLKDIST_CR, 0x40004000
.set CYDEV_CLKDIST_LD, 0x40004001
.set CYDEV_CLKDIST_WRK0, 0x40004002
.set CYDEV_CLKDIST_WRK1, 0x40004003
.set CYDEV_CLKDIST_MSTR0, 0x40004004
.set CYDEV_CLKDIST_MSTR1, 0x40004005
.set CYDEV_CLKDIST_BCFG0, 0x40004006
.set CYDEV_CLKDIST_BCFG1, 0x40004007
.set CYDEV_CLKDIST_BCFG2, 0x40004008
.set CYDEV_CLKDIST_UCFG, 0x40004009
.set CYDEV_CLKDIST_DLY0, 0x4000400a
.set CYDEV_CLKDIST_DLY1, 0x4000400b
.set CYDEV_CLKDIST_DMASK, 0x40004010
.set CYDEV_CLKDIST_AMASK, 0x40004014
.set CYDEV_CLKDIST_DCFG0_BASE, 0x40004080
.set CYDEV_CLKDIST_DCFG0_SIZE, 0x00000003
.set CYDEV_CLKDIST_DCFG0_CFG0, 0x40004080
.set CYDEV_CLKDIST_DCFG0_CFG1, 0x40004081
.set CYDEV_CLKDIST_DCFG0_CFG2, 0x40004082
.set CYDEV_CLKDIST_DCFG1_BASE, 0x40004084
.set CYDEV_CLKDIST_DCFG1_SIZE, 0x00000003
.set CYDEV_CLKDIST_DCFG1_CFG0, 0x40004084
.set CYDEV_CLKDIST_DCFG1_CFG1, 0x40004085
.set CYDEV_CLKDIST_DCFG1_CFG2, 0x40004086
.set CYDEV_CLKDIST_DCFG2_BASE, 0x40004088
.set CYDEV_CLKDIST_DCFG2_SIZE, 0x00000003
.set CYDEV_CLKDIST_DCFG2_CFG0, 0x40004088
.set CYDEV_CLKDIST_DCFG2_CFG1, 0x40004089
.set CYDEV_CLKDIST_DCFG2_CFG2, 0x4000408a
.set CYDEV_CLKDIST_DCFG3_BASE, 0x4000408c
.set CYDEV_CLKDIST_DCFG3_SIZE, 0x00000003
.set CYDEV_CLKDIST_DCFG3_CFG0, 0x4000408c
.set CYDEV_CLKDIST_DCFG3_CFG1, 0x4000408d
.set CYDEV_CLKDIST_DCFG3_CFG2, 0x4000408e
.set CYDEV_CLKDIST_DCFG4_BASE, 0x40004090
.set CYDEV_CLKDIST_DCFG4_SIZE, 0x00000003
.set CYDEV_CLKDIST_DCFG4_CFG0, 0x40004090
.set CYDEV_CLKDIST_DCFG4_CFG1, 0x40004091
.set CYDEV_CLKDIST_DCFG4_CFG2, 0x40004092
.set CYDEV_CLKDIST_DCFG5_BASE, 0x40004094
.set CYDEV_CLKDIST_DCFG5_SIZE, 0x00000003
.set CYDEV_CLKDIST_DCFG5_CFG0, 0x40004094
.set CYDEV_CLKDIST_DCFG5_CFG1, 0x40004095
.set CYDEV_CLKDIST_DCFG5_CFG2, 0x40004096
.set CYDEV_CLKDIST_DCFG6_BASE, 0x40004098
.set CYDEV_CLKDIST_DCFG6_SIZE, 0x00000003
.set CYDEV_CLKDIST_DCFG6_CFG0, 0x40004098
.set CYDEV_CLKDIST_DCFG6_CFG1, 0x40004099
.set CYDEV_CLKDIST_DCFG6_CFG2, 0x4000409a
.set CYDEV_CLKDIST_DCFG7_BASE, 0x4000409c
.set CYDEV_CLKDIST_DCFG7_SIZE, 0x00000003
.set CYDEV_CLKDIST_DCFG7_CFG0, 0x4000409c
.set CYDEV_CLKDIST_DCFG7_CFG1, 0x4000409d
.set CYDEV_CLKDIST_DCFG7_CFG2, 0x4000409e
.set CYDEV_CLKDIST_ACFG0_BASE, 0x40004100
.set CYDEV_CLKDIST_ACFG0_SIZE, 0x00000004
.set CYDEV_CLKDIST_ACFG0_CFG0, 0x40004100
.set CYDEV_CLKDIST_ACFG0_CFG1, 0x40004101
.set CYDEV_CLKDIST_ACFG0_CFG2, 0x40004102
.set CYDEV_CLKDIST_ACFG0_CFG3, 0x40004103
.set CYDEV_CLKDIST_ACFG1_BASE, 0x40004104
.set CYDEV_CLKDIST_ACFG1_SIZE, 0x00000004
.set CYDEV_CLKDIST_ACFG1_CFG0, 0x40004104
.set CYDEV_CLKDIST_ACFG1_CFG1, 0x40004105
.set CYDEV_CLKDIST_ACFG1_CFG2, 0x40004106
.set CYDEV_CLKDIST_ACFG1_CFG3, 0x40004107
.set CYDEV_CLKDIST_ACFG2_BASE, 0x40004108
.set CYDEV_CLKDIST_ACFG2_SIZE, 0x00000004
.set CYDEV_CLKDIST_ACFG2_CFG0, 0x40004108
.set CYDEV_CLKDIST_ACFG2_CFG1, 0x40004109
.set CYDEV_CLKDIST_ACFG2_CFG2, 0x4000410a
.set CYDEV_CLKDIST_ACFG2_CFG3, 0x4000410b
.set CYDEV_CLKDIST_ACFG3_BASE, 0x4000410c
.set CYDEV_CLKDIST_ACFG3_SIZE, 0x00000004
.set CYDEV_CLKDIST_ACFG3_CFG0, 0x4000410c
.set CYDEV_CLKDIST_ACFG3_CFG1, 0x4000410d
.set CYDEV_CLKDIST_ACFG3_CFG2, 0x4000410e
.set CYDEV_CLKDIST_ACFG3_CFG3, 0x4000410f
.set CYDEV_FASTCLK_BASE, 0x40004200
.set CYDEV_FASTCLK_SIZE, 0x00000026
.set CYDEV_FASTCLK_IMO_BASE, 0x40004200
.set CYDEV_FASTCLK_IMO_SIZE, 0x00000001
.set CYDEV_FASTCLK_IMO_CR, 0x40004200
.set CYDEV_FASTCLK_XMHZ_BASE, 0x40004210
.set CYDEV_FASTCLK_XMHZ_SIZE, 0x00000004
.set CYDEV_FASTCLK_XMHZ_CSR, 0x40004210
.set CYDEV_FASTCLK_XMHZ_CFG0, 0x40004212
.set CYDEV_FASTCLK_XMHZ_CFG1, 0x40004213
.set CYDEV_FASTCLK_PLL_BASE, 0x40004220
.set CYDEV_FASTCLK_PLL_SIZE, 0x00000006
.set CYDEV_FASTCLK_PLL_CFG0, 0x40004220
.set CYDEV_FASTCLK_PLL_CFG1, 0x40004221
.set CYDEV_FASTCLK_PLL_P, 0x40004222
.set CYDEV_FASTCLK_PLL_Q, 0x40004223
.set CYDEV_FASTCLK_PLL_SR, 0x40004225
.set CYDEV_SLOWCLK_BASE, 0x40004300
.set CYDEV_SLOWCLK_SIZE, 0x0000000b
.set CYDEV_SLOWCLK_ILO_BASE, 0x40004300
.set CYDEV_SLOWCLK_ILO_SIZE, 0x00000002
.set CYDEV_SLOWCLK_ILO_CR0, 0x40004300
.set CYDEV_SLOWCLK_ILO_CR1, 0x40004301
.set CYDEV_SLOWCLK_X32_BASE, 0x40004308
.set CYDEV_SLOWCLK_X32_SIZE, 0x00000003
.set CYDEV_SLOWCLK_X32_CR, 0x40004308
.set CYDEV_SLOWCLK_X32_CFG, 0x40004309
.set CYDEV_SLOWCLK_X32_TST, 0x4000430a
.set CYDEV_BOOST_BASE, 0x40004320
.set CYDEV_BOOST_SIZE, 0x00000007
.set CYDEV_BOOST_CR0, 0x40004320
.set CYDEV_BOOST_CR1, 0x40004321
.set CYDEV_BOOST_CR2, 0x40004322
.set CYDEV_BOOST_CR3, 0x40004323
.set CYDEV_BOOST_SR, 0x40004324
.set CYDEV_BOOST_CR4, 0x40004325
.set CYDEV_BOOST_SR2, 0x40004326
.set CYDEV_PWRSYS_BASE, 0x40004330
.set CYDEV_PWRSYS_SIZE, 0x00000002
.set CYDEV_PWRSYS_CR0, 0x40004330
.set CYDEV_PWRSYS_CR1, 0x40004331
.set CYDEV_PM_BASE, 0x40004380
.set CYDEV_PM_SIZE, 0x00000057
.set CYDEV_PM_TW_CFG0, 0x40004380
.set CYDEV_PM_TW_CFG1, 0x40004381
.set CYDEV_PM_TW_CFG2, 0x40004382
.set CYDEV_PM_WDT_CFG, 0x40004383
.set CYDEV_PM_WDT_CR, 0x40004384
.set CYDEV_PM_INT_SR, 0x40004390
.set CYDEV_PM_MODE_CFG0, 0x40004391
.set CYDEV_PM_MODE_CFG1, 0x40004392
.set CYDEV_PM_MODE_CSR, 0x40004393
.set CYDEV_PM_USB_CR0, 0x40004394
.set CYDEV_PM_WAKEUP_CFG0, 0x40004398
.set CYDEV_PM_WAKEUP_CFG1, 0x40004399
.set CYDEV_PM_WAKEUP_CFG2, 0x4000439a
.set CYDEV_PM_ACT_BASE, 0x400043a0
.set CYDEV_PM_ACT_SIZE, 0x0000000e
.set CYDEV_PM_ACT_CFG0, 0x400043a0
.set CYDEV_PM_ACT_CFG1, 0x400043a1
.set CYDEV_PM_ACT_CFG2, 0x400043a2
.set CYDEV_PM_ACT_CFG3, 0x400043a3
.set CYDEV_PM_ACT_CFG4, 0x400043a4
.set CYDEV_PM_ACT_CFG5, 0x400043a5
.set CYDEV_PM_ACT_CFG6, 0x400043a6
.set CYDEV_PM_ACT_CFG7, 0x400043a7
.set CYDEV_PM_ACT_CFG8, 0x400043a8
.set CYDEV_PM_ACT_CFG9, 0x400043a9
.set CYDEV_PM_ACT_CFG10, 0x400043aa
.set CYDEV_PM_ACT_CFG11, 0x400043ab
.set CYDEV_PM_ACT_CFG12, 0x400043ac
.set CYDEV_PM_ACT_CFG13, 0x400043ad
.set CYDEV_PM_STBY_BASE, 0x400043b0
.set CYDEV_PM_STBY_SIZE, 0x0000000e
.set CYDEV_PM_STBY_CFG0, 0x400043b0
.set CYDEV_PM_STBY_CFG1, 0x400043b1
.set CYDEV_PM_STBY_CFG2, 0x400043b2
.set CYDEV_PM_STBY_CFG3, 0x400043b3
.set CYDEV_PM_STBY_CFG4, 0x400043b4
.set CYDEV_PM_STBY_CFG5, 0x400043b5
.set CYDEV_PM_STBY_CFG6, 0x400043b6
.set CYDEV_PM_STBY_CFG7, 0x400043b7
.set CYDEV_PM_STBY_CFG8, 0x400043b8
.set CYDEV_PM_STBY_CFG9, 0x400043b9
.set CYDEV_PM_STBY_CFG10, 0x400043ba
.set CYDEV_PM_STBY_CFG11, 0x400043bb
.set CYDEV_PM_STBY_CFG12, 0x400043bc
.set CYDEV_PM_STBY_CFG13, 0x400043bd
.set CYDEV_PM_AVAIL_BASE, 0x400043c0
.set CYDEV_PM_AVAIL_SIZE, 0x00000017
.set CYDEV_PM_AVAIL_CR0, 0x400043c0
.set CYDEV_PM_AVAIL_CR1, 0x400043c1
.set CYDEV_PM_AVAIL_CR2, 0x400043c2
.set CYDEV_PM_AVAIL_CR3, 0x400043c3
.set CYDEV_PM_AVAIL_CR4, 0x400043c4
.set CYDEV_PM_AVAIL_CR5, 0x400043c5
.set CYDEV_PM_AVAIL_CR6, 0x400043c6
.set CYDEV_PM_AVAIL_SR0, 0x400043d0
.set CYDEV_PM_AVAIL_SR1, 0x400043d1
.set CYDEV_PM_AVAIL_SR2, 0x400043d2
.set CYDEV_PM_AVAIL_SR3, 0x400043d3
.set CYDEV_PM_AVAIL_SR4, 0x400043d4
.set CYDEV_PM_AVAIL_SR5, 0x400043d5
.set CYDEV_PM_AVAIL_SR6, 0x400043d6
.set CYDEV_PICU_BASE, 0x40004500
.set CYDEV_PICU_SIZE, 0x000000b0
.set CYDEV_PICU_INTTYPE_BASE, 0x40004500
.set CYDEV_PICU_INTTYPE_SIZE, 0x00000080
.set CYDEV_PICU_INTTYPE_PICU0_BASE, 0x40004500
.set CYDEV_PICU_INTTYPE_PICU0_SIZE, 0x00000008
.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE0, 0x40004500
.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE1, 0x40004501
.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE2, 0x40004502
.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE3, 0x40004503
.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE4, 0x40004504
.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE5, 0x40004505
.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE6, 0x40004506
.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE7, 0x40004507
.set CYDEV_PICU_INTTYPE_PICU1_BASE, 0x40004508
.set CYDEV_PICU_INTTYPE_PICU1_SIZE, 0x00000008
.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE0, 0x40004508
.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE1, 0x40004509
.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE2, 0x4000450a
.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE3, 0x4000450b
.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE4, 0x4000450c
.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE5, 0x4000450d
.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE6, 0x4000450e
.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE7, 0x4000450f
.set CYDEV_PICU_INTTYPE_PICU2_BASE, 0x40004510
.set CYDEV_PICU_INTTYPE_PICU2_SIZE, 0x00000008
.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE0, 0x40004510
.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE1, 0x40004511
.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE2, 0x40004512
.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE3, 0x40004513
.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE4, 0x40004514
.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE5, 0x40004515
.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE6, 0x40004516
.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE7, 0x40004517
.set CYDEV_PICU_INTTYPE_PICU3_BASE, 0x40004518
.set CYDEV_PICU_INTTYPE_PICU3_SIZE, 0x00000008
.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE0, 0x40004518
.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE1, 0x40004519
.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE2, 0x4000451a
.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE3, 0x4000451b
.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE4, 0x4000451c
.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE5, 0x4000451d
.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE6, 0x4000451e
.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE7, 0x4000451f
.set CYDEV_PICU_INTTYPE_PICU4_BASE, 0x40004520
.set CYDEV_PICU_INTTYPE_PICU4_SIZE, 0x00000008
.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE0, 0x40004520
.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE1, 0x40004521
.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE2, 0x40004522
.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE3, 0x40004523
.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE4, 0x40004524
.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE5, 0x40004525
.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE6, 0x40004526
.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE7, 0x40004527
.set CYDEV_PICU_INTTYPE_PICU5_BASE, 0x40004528
.set CYDEV_PICU_INTTYPE_PICU5_SIZE, 0x00000008
.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE0, 0x40004528
.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE1, 0x40004529
.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE2, 0x4000452a
.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE3, 0x4000452b
.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE4, 0x4000452c
.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE5, 0x4000452d
.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE6, 0x4000452e
.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE7, 0x4000452f
.set CYDEV_PICU_INTTYPE_PICU6_BASE, 0x40004530
.set CYDEV_PICU_INTTYPE_PICU6_SIZE, 0x00000008
.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE0, 0x40004530
.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE1, 0x40004531
.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE2, 0x40004532
.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE3, 0x40004533
.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE4, 0x40004534
.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE5, 0x40004535
.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE6, 0x40004536
.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE7, 0x40004537
.set CYDEV_PICU_INTTYPE_PICU12_BASE, 0x40004560
.set CYDEV_PICU_INTTYPE_PICU12_SIZE, 0x00000008
.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE0, 0x40004560
.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE1, 0x40004561
.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE2, 0x40004562
.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE3, 0x40004563
.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE4, 0x40004564
.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE5, 0x40004565
.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE6, 0x40004566
.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE7, 0x40004567
.set CYDEV_PICU_INTTYPE_PICU15_BASE, 0x40004578
.set CYDEV_PICU_INTTYPE_PICU15_SIZE, 0x00000008
.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE0, 0x40004578
.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE1, 0x40004579
.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE2, 0x4000457a
.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE3, 0x4000457b
.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE4, 0x4000457c
.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE5, 0x4000457d
.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE6, 0x4000457e
.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE7, 0x4000457f
.set CYDEV_PICU_STAT_BASE, 0x40004580
.set CYDEV_PICU_STAT_SIZE, 0x00000010
.set CYDEV_PICU_STAT_PICU0_BASE, 0x40004580
.set CYDEV_PICU_STAT_PICU0_SIZE, 0x00000001
.set CYDEV_PICU_STAT_PICU0_INTSTAT, 0x40004580
.set CYDEV_PICU_STAT_PICU1_BASE, 0x40004581
.set CYDEV_PICU_STAT_PICU1_SIZE, 0x00000001
.set CYDEV_PICU_STAT_PICU1_INTSTAT, 0x40004581
.set CYDEV_PICU_STAT_PICU2_BASE, 0x40004582
.set CYDEV_PICU_STAT_PICU2_SIZE, 0x00000001
.set CYDEV_PICU_STAT_PICU2_INTSTAT, 0x40004582
.set CYDEV_PICU_STAT_PICU3_BASE, 0x40004583
.set CYDEV_PICU_STAT_PICU3_SIZE, 0x00000001
.set CYDEV_PICU_STAT_PICU3_INTSTAT, 0x40004583
.set CYDEV_PICU_STAT_PICU4_BASE, 0x40004584
.set CYDEV_PICU_STAT_PICU4_SIZE, 0x00000001
.set CYDEV_PICU_STAT_PICU4_INTSTAT, 0x40004584
.set CYDEV_PICU_STAT_PICU5_BASE, 0x40004585
.set CYDEV_PICU_STAT_PICU5_SIZE, 0x00000001
.set CYDEV_PICU_STAT_PICU5_INTSTAT, 0x40004585
.set CYDEV_PICU_STAT_PICU6_BASE, 0x40004586
.set CYDEV_PICU_STAT_PICU6_SIZE, 0x00000001
.set CYDEV_PICU_STAT_PICU6_INTSTAT, 0x40004586
.set CYDEV_PICU_STAT_PICU12_BASE, 0x4000458c
.set CYDEV_PICU_STAT_PICU12_SIZE, 0x00000001
.set CYDEV_PICU_STAT_PICU12_INTSTAT, 0x4000458c
.set CYDEV_PICU_STAT_PICU15_BASE, 0x4000458f
.set CYDEV_PICU_STAT_PICU15_SIZE, 0x00000001
.set CYDEV_PICU_STAT_PICU15_INTSTAT, 0x4000458f
.set CYDEV_PICU_SNAP_BASE, 0x40004590
.set CYDEV_PICU_SNAP_SIZE, 0x00000010
.set CYDEV_PICU_SNAP_PICU0_BASE, 0x40004590
.set CYDEV_PICU_SNAP_PICU0_SIZE, 0x00000001
.set CYDEV_PICU_SNAP_PICU0_SNAP, 0x40004590
.set CYDEV_PICU_SNAP_PICU1_BASE, 0x40004591
.set CYDEV_PICU_SNAP_PICU1_SIZE, 0x00000001
.set CYDEV_PICU_SNAP_PICU1_SNAP, 0x40004591
.set CYDEV_PICU_SNAP_PICU2_BASE, 0x40004592
.set CYDEV_PICU_SNAP_PICU2_SIZE, 0x00000001
.set CYDEV_PICU_SNAP_PICU2_SNAP, 0x40004592
.set CYDEV_PICU_SNAP_PICU3_BASE, 0x40004593
.set CYDEV_PICU_SNAP_PICU3_SIZE, 0x00000001
.set CYDEV_PICU_SNAP_PICU3_SNAP, 0x40004593
.set CYDEV_PICU_SNAP_PICU4_BASE, 0x40004594
.set CYDEV_PICU_SNAP_PICU4_SIZE, 0x00000001
.set CYDEV_PICU_SNAP_PICU4_SNAP, 0x40004594
.set CYDEV_PICU_SNAP_PICU5_BASE, 0x40004595
.set CYDEV_PICU_SNAP_PICU5_SIZE, 0x00000001
.set CYDEV_PICU_SNAP_PICU5_SNAP, 0x40004595
.set CYDEV_PICU_SNAP_PICU6_BASE, 0x40004596
.set CYDEV_PICU_SNAP_PICU6_SIZE, 0x00000001
.set CYDEV_PICU_SNAP_PICU6_SNAP, 0x40004596
.set CYDEV_PICU_SNAP_PICU12_BASE, 0x4000459c
.set CYDEV_PICU_SNAP_PICU12_SIZE, 0x00000001
.set CYDEV_PICU_SNAP_PICU12_SNAP, 0x4000459c
.set CYDEV_PICU_SNAP_PICU_15_BASE, 0x4000459f
.set CYDEV_PICU_SNAP_PICU_15_SIZE, 0x00000001
.set CYDEV_PICU_SNAP_PICU_15_SNAP_15, 0x4000459f
.set CYDEV_PICU_DISABLE_COR_BASE, 0x400045a0
.set CYDEV_PICU_DISABLE_COR_SIZE, 0x00000010
.set CYDEV_PICU_DISABLE_COR_PICU0_BASE, 0x400045a0
.set CYDEV_PICU_DISABLE_COR_PICU0_SIZE, 0x00000001
.set CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR, 0x400045a0
.set CYDEV_PICU_DISABLE_COR_PICU1_BASE, 0x400045a1
.set CYDEV_PICU_DISABLE_COR_PICU1_SIZE, 0x00000001
.set CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR, 0x400045a1
.set CYDEV_PICU_DISABLE_COR_PICU2_BASE, 0x400045a2
.set CYDEV_PICU_DISABLE_COR_PICU2_SIZE, 0x00000001
.set CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR, 0x400045a2
.set CYDEV_PICU_DISABLE_COR_PICU3_BASE, 0x400045a3
.set CYDEV_PICU_DISABLE_COR_PICU3_SIZE, 0x00000001
.set CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR, 0x400045a3
.set CYDEV_PICU_DISABLE_COR_PICU4_BASE, 0x400045a4
.set CYDEV_PICU_DISABLE_COR_PICU4_SIZE, 0x00000001
.set CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR, 0x400045a4
.set CYDEV_PICU_DISABLE_COR_PICU5_BASE, 0x400045a5
.set CYDEV_PICU_DISABLE_COR_PICU5_SIZE, 0x00000001
.set CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR, 0x400045a5
.set CYDEV_PICU_DISABLE_COR_PICU6_BASE, 0x400045a6
.set CYDEV_PICU_DISABLE_COR_PICU6_SIZE, 0x00000001
.set CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR, 0x400045a6
.set CYDEV_PICU_DISABLE_COR_PICU12_BASE, 0x400045ac
.set CYDEV_PICU_DISABLE_COR_PICU12_SIZE, 0x00000001
.set CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR, 0x400045ac
.set CYDEV_PICU_DISABLE_COR_PICU15_BASE, 0x400045af
.set CYDEV_PICU_DISABLE_COR_PICU15_SIZE, 0x00000001
.set CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR, 0x400045af
.set CYDEV_MFGCFG_BASE, 0x40004600
.set CYDEV_MFGCFG_SIZE, 0x000000ed
.set CYDEV_MFGCFG_ANAIF_BASE, 0x40004600
.set CYDEV_MFGCFG_ANAIF_SIZE, 0x00000038
.set CYDEV_MFGCFG_ANAIF_DAC0_BASE, 0x40004608
.set CYDEV_MFGCFG_ANAIF_DAC0_SIZE, 0x00000001
.set CYDEV_MFGCFG_ANAIF_DAC0_TR, 0x40004608
.set CYDEV_MFGCFG_ANAIF_DAC1_BASE, 0x40004609
.set CYDEV_MFGCFG_ANAIF_DAC1_SIZE, 0x00000001
.set CYDEV_MFGCFG_ANAIF_DAC1_TR, 0x40004609
.set CYDEV_MFGCFG_ANAIF_DAC2_BASE, 0x4000460a
.set CYDEV_MFGCFG_ANAIF_DAC2_SIZE, 0x00000001
.set CYDEV_MFGCFG_ANAIF_DAC2_TR, 0x4000460a
.set CYDEV_MFGCFG_ANAIF_DAC3_BASE, 0x4000460b
.set CYDEV_MFGCFG_ANAIF_DAC3_SIZE, 0x00000001
.set CYDEV_MFGCFG_ANAIF_DAC3_TR, 0x4000460b
.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE, 0x40004610
.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE, 0x00000001
.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0, 0x40004610
.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE, 0x40004611
.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE, 0x00000001
.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0, 0x40004611
.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE, 0x40004612
.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE, 0x00000001
.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0, 0x40004612
.set CYDEV_MFGCFG_ANAIF_SAR0_BASE, 0x40004614
.set CYDEV_MFGCFG_ANAIF_SAR0_SIZE, 0x00000001
.set CYDEV_MFGCFG_ANAIF_SAR0_TR0, 0x40004614
.set CYDEV_MFGCFG_ANAIF_SAR1_BASE, 0x40004616
.set CYDEV_MFGCFG_ANAIF_SAR1_SIZE, 0x00000001
.set CYDEV_MFGCFG_ANAIF_SAR1_TR0, 0x40004616
.set CYDEV_MFGCFG_ANAIF_OPAMP0_BASE, 0x40004620
.set CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE, 0x00000002
.set CYDEV_MFGCFG_ANAIF_OPAMP0_TR0, 0x40004620
.set CYDEV_MFGCFG_ANAIF_OPAMP0_TR1, 0x40004621
.set CYDEV_MFGCFG_ANAIF_OPAMP1_BASE, 0x40004622
.set CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE, 0x00000002
.set CYDEV_MFGCFG_ANAIF_OPAMP1_TR0, 0x40004622
.set CYDEV_MFGCFG_ANAIF_OPAMP1_TR1, 0x40004623
.set CYDEV_MFGCFG_ANAIF_OPAMP2_BASE, 0x40004624
.set CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE, 0x00000002
.set CYDEV_MFGCFG_ANAIF_OPAMP2_TR0, 0x40004624
.set CYDEV_MFGCFG_ANAIF_OPAMP2_TR1, 0x40004625
.set CYDEV_MFGCFG_ANAIF_OPAMP3_BASE, 0x40004626
.set CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE, 0x00000002
.set CYDEV_MFGCFG_ANAIF_OPAMP3_TR0, 0x40004626
.set CYDEV_MFGCFG_ANAIF_OPAMP3_TR1, 0x40004627
.set CYDEV_MFGCFG_ANAIF_CMP0_BASE, 0x40004630
.set CYDEV_MFGCFG_ANAIF_CMP0_SIZE, 0x00000002
.set CYDEV_MFGCFG_ANAIF_CMP0_TR0, 0x40004630
.set CYDEV_MFGCFG_ANAIF_CMP0_TR1, 0x40004631
.set CYDEV_MFGCFG_ANAIF_CMP1_BASE, 0x40004632
.set CYDEV_MFGCFG_ANAIF_CMP1_SIZE, 0x00000002
.set CYDEV_MFGCFG_ANAIF_CMP1_TR0, 0x40004632
.set CYDEV_MFGCFG_ANAIF_CMP1_TR1, 0x40004633
.set CYDEV_MFGCFG_ANAIF_CMP2_BASE, 0x40004634
.set CYDEV_MFGCFG_ANAIF_CMP2_SIZE, 0x00000002
.set CYDEV_MFGCFG_ANAIF_CMP2_TR0, 0x40004634
.set CYDEV_MFGCFG_ANAIF_CMP2_TR1, 0x40004635
.set CYDEV_MFGCFG_ANAIF_CMP3_BASE, 0x40004636
.set CYDEV_MFGCFG_ANAIF_CMP3_SIZE, 0x00000002
.set CYDEV_MFGCFG_ANAIF_CMP3_TR0, 0x40004636
.set CYDEV_MFGCFG_ANAIF_CMP3_TR1, 0x40004637
.set CYDEV_MFGCFG_PWRSYS_BASE, 0x40004680
.set CYDEV_MFGCFG_PWRSYS_SIZE, 0x0000000b
.set CYDEV_MFGCFG_PWRSYS_HIB_TR0, 0x40004680
.set CYDEV_MFGCFG_PWRSYS_HIB_TR1, 0x40004681
.set CYDEV_MFGCFG_PWRSYS_I2C_TR, 0x40004682
.set CYDEV_MFGCFG_PWRSYS_SLP_TR, 0x40004683
.set CYDEV_MFGCFG_PWRSYS_BUZZ_TR, 0x40004684
.set CYDEV_MFGCFG_PWRSYS_WAKE_TR0, 0x40004685
.set CYDEV_MFGCFG_PWRSYS_WAKE_TR1, 0x40004686
.set CYDEV_MFGCFG_PWRSYS_BREF_TR, 0x40004687
.set CYDEV_MFGCFG_PWRSYS_BG_TR, 0x40004688
.set CYDEV_MFGCFG_PWRSYS_WAKE_TR2, 0x40004689
.set CYDEV_MFGCFG_PWRSYS_WAKE_TR3, 0x4000468a
.set CYDEV_MFGCFG_ILO_BASE, 0x40004690
.set CYDEV_MFGCFG_ILO_SIZE, 0x00000002
.set CYDEV_MFGCFG_ILO_TR0, 0x40004690
.set CYDEV_MFGCFG_ILO_TR1, 0x40004691
.set CYDEV_MFGCFG_X32_BASE, 0x40004698
.set CYDEV_MFGCFG_X32_SIZE, 0x00000001
.set CYDEV_MFGCFG_X32_TR, 0x40004698
.set CYDEV_MFGCFG_IMO_BASE, 0x400046a0
.set CYDEV_MFGCFG_IMO_SIZE, 0x00000005
.set CYDEV_MFGCFG_IMO_TR0, 0x400046a0
.set CYDEV_MFGCFG_IMO_TR1, 0x400046a1
.set CYDEV_MFGCFG_IMO_GAIN, 0x400046a2
.set CYDEV_MFGCFG_IMO_C36M, 0x400046a3
.set CYDEV_MFGCFG_IMO_TR2, 0x400046a4
.set CYDEV_MFGCFG_XMHZ_BASE, 0x400046a8
.set CYDEV_MFGCFG_XMHZ_SIZE, 0x00000001
.set CYDEV_MFGCFG_XMHZ_TR, 0x400046a8
.set CYDEV_MFGCFG_DLY, 0x400046c0
.set CYDEV_MFGCFG_MLOGIC_BASE, 0x400046e0
.set CYDEV_MFGCFG_MLOGIC_SIZE, 0x0000000d
.set CYDEV_MFGCFG_MLOGIC_DMPSTR, 0x400046e2
.set CYDEV_MFGCFG_MLOGIC_SEG_BASE, 0x400046e4
.set CYDEV_MFGCFG_MLOGIC_SEG_SIZE, 0x00000002
.set CYDEV_MFGCFG_MLOGIC_SEG_CR, 0x400046e4
.set CYDEV_MFGCFG_MLOGIC_SEG_CFG0, 0x400046e5
.set CYDEV_MFGCFG_MLOGIC_DEBUG, 0x400046e8
.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE, 0x400046ea
.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE, 0x00000001
.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR, 0x400046ea
.set CYDEV_MFGCFG_MLOGIC_REV_ID, 0x400046ec
.set CYDEV_RESET_BASE, 0x400046f0
.set CYDEV_RESET_SIZE, 0x0000000f
.set CYDEV_RESET_IPOR_CR0, 0x400046f0
.set CYDEV_RESET_IPOR_CR1, 0x400046f1
.set CYDEV_RESET_IPOR_CR2, 0x400046f2
.set CYDEV_RESET_IPOR_CR3, 0x400046f3
.set CYDEV_RESET_CR0, 0x400046f4
.set CYDEV_RESET_CR1, 0x400046f5
.set CYDEV_RESET_CR2, 0x400046f6
.set CYDEV_RESET_CR3, 0x400046f7
.set CYDEV_RESET_CR4, 0x400046f8
.set CYDEV_RESET_CR5, 0x400046f9
.set CYDEV_RESET_SR0, 0x400046fa
.set CYDEV_RESET_SR1, 0x400046fb
.set CYDEV_RESET_SR2, 0x400046fc
.set CYDEV_RESET_SR3, 0x400046fd
.set CYDEV_RESET_TR, 0x400046fe
.set CYDEV_SPC_BASE, 0x40004700
.set CYDEV_SPC_SIZE, 0x00000100
.set CYDEV_SPC_FM_EE_CR, 0x40004700
.set CYDEV_SPC_FM_EE_WAKE_CNT, 0x40004701
.set CYDEV_SPC_EE_SCR, 0x40004702
.set CYDEV_SPC_EE_ERR, 0x40004703
.set CYDEV_SPC_CPU_DATA, 0x40004720
.set CYDEV_SPC_DMA_DATA, 0x40004721
.set CYDEV_SPC_SR, 0x40004722
.set CYDEV_SPC_CR, 0x40004723
.set CYDEV_SPC_DMM_MAP_BASE, 0x40004780
.set CYDEV_SPC_DMM_MAP_SIZE, 0x00000080
.set CYDEV_SPC_DMM_MAP_SRAM_MBASE, 0x40004780
.set CYDEV_SPC_DMM_MAP_SRAM_MSIZE, 0x00000080
.set CYDEV_CACHE_BASE, 0x40004800
.set CYDEV_CACHE_SIZE, 0x0000009c
.set CYDEV_CACHE_CC_CTL, 0x40004800
.set CYDEV_CACHE_ECC_CORR, 0x40004880
.set CYDEV_CACHE_ECC_ERR, 0x40004888
.set CYDEV_CACHE_FLASH_ERR, 0x40004890
.set CYDEV_CACHE_HITMISS, 0x40004898
.set CYDEV_I2C_BASE, 0x40004900
.set CYDEV_I2C_SIZE, 0x000000e1
.set CYDEV_I2C_XCFG, 0x400049c8
.set CYDEV_I2C_ADR, 0x400049ca
.set CYDEV_I2C_CFG, 0x400049d6
.set CYDEV_I2C_CSR, 0x400049d7
.set CYDEV_I2C_D, 0x400049d8
.set CYDEV_I2C_MCSR, 0x400049d9
.set CYDEV_I2C_CLK_DIV1, 0x400049db
.set CYDEV_I2C_CLK_DIV2, 0x400049dc
.set CYDEV_I2C_TMOUT_CSR, 0x400049dd
.set CYDEV_I2C_TMOUT_SR, 0x400049de
.set CYDEV_I2C_TMOUT_CFG0, 0x400049df
.set CYDEV_I2C_TMOUT_CFG1, 0x400049e0
.set CYDEV_DEC_BASE, 0x40004e00
.set CYDEV_DEC_SIZE, 0x00000015
.set CYDEV_DEC_CR, 0x40004e00
.set CYDEV_DEC_SR, 0x40004e01
.set CYDEV_DEC_SHIFT1, 0x40004e02
.set CYDEV_DEC_SHIFT2, 0x40004e03
.set CYDEV_DEC_DR2, 0x40004e04
.set CYDEV_DEC_DR2H, 0x40004e05
.set CYDEV_DEC_DR1, 0x40004e06
.set CYDEV_DEC_OCOR, 0x40004e08
.set CYDEV_DEC_OCORM, 0x40004e09
.set CYDEV_DEC_OCORH, 0x40004e0a
.set CYDEV_DEC_GCOR, 0x40004e0c
.set CYDEV_DEC_GCORH, 0x40004e0d
.set CYDEV_DEC_GVAL, 0x40004e0e
.set CYDEV_DEC_OUTSAMP, 0x40004e10
.set CYDEV_DEC_OUTSAMPM, 0x40004e11
.set CYDEV_DEC_OUTSAMPH, 0x40004e12
.set CYDEV_DEC_OUTSAMPS, 0x40004e13
.set CYDEV_DEC_COHER, 0x40004e14
.set CYDEV_TMR0_BASE, 0x40004f00
.set CYDEV_TMR0_SIZE, 0x0000000c
.set CYDEV_TMR0_CFG0, 0x40004f00
.set CYDEV_TMR0_CFG1, 0x40004f01
.set CYDEV_TMR0_CFG2, 0x40004f02
.set CYDEV_TMR0_SR0, 0x40004f03
.set CYDEV_TMR0_PER0, 0x40004f04
.set CYDEV_TMR0_PER1, 0x40004f05
.set CYDEV_TMR0_CNT_CMP0, 0x40004f06
.set CYDEV_TMR0_CNT_CMP1, 0x40004f07
.set CYDEV_TMR0_CAP0, 0x40004f08
.set CYDEV_TMR0_CAP1, 0x40004f09
.set CYDEV_TMR0_RT0, 0x40004f0a
.set CYDEV_TMR0_RT1, 0x40004f0b
.set CYDEV_TMR1_BASE, 0x40004f0c
.set CYDEV_TMR1_SIZE, 0x0000000c
.set CYDEV_TMR1_CFG0, 0x40004f0c
.set CYDEV_TMR1_CFG1, 0x40004f0d
.set CYDEV_TMR1_CFG2, 0x40004f0e
.set CYDEV_TMR1_SR0, 0x40004f0f
.set CYDEV_TMR1_PER0, 0x40004f10
.set CYDEV_TMR1_PER1, 0x40004f11
.set CYDEV_TMR1_CNT_CMP0, 0x40004f12
.set CYDEV_TMR1_CNT_CMP1, 0x40004f13
.set CYDEV_TMR1_CAP0, 0x40004f14
.set CYDEV_TMR1_CAP1, 0x40004f15
.set CYDEV_TMR1_RT0, 0x40004f16
.set CYDEV_TMR1_RT1, 0x40004f17
.set CYDEV_TMR2_BASE, 0x40004f18
.set CYDEV_TMR2_SIZE, 0x0000000c
.set CYDEV_TMR2_CFG0, 0x40004f18
.set CYDEV_TMR2_CFG1, 0x40004f19
.set CYDEV_TMR2_CFG2, 0x40004f1a
.set CYDEV_TMR2_SR0, 0x40004f1b
.set CYDEV_TMR2_PER0, 0x40004f1c
.set CYDEV_TMR2_PER1, 0x40004f1d
.set CYDEV_TMR2_CNT_CMP0, 0x40004f1e
.set CYDEV_TMR2_CNT_CMP1, 0x40004f1f
.set CYDEV_TMR2_CAP0, 0x40004f20
.set CYDEV_TMR2_CAP1, 0x40004f21
.set CYDEV_TMR2_RT0, 0x40004f22
.set CYDEV_TMR2_RT1, 0x40004f23
.set CYDEV_TMR3_BASE, 0x40004f24
.set CYDEV_TMR3_SIZE, 0x0000000c
.set CYDEV_TMR3_CFG0, 0x40004f24
.set CYDEV_TMR3_CFG1, 0x40004f25
.set CYDEV_TMR3_CFG2, 0x40004f26
.set CYDEV_TMR3_SR0, 0x40004f27
.set CYDEV_TMR3_PER0, 0x40004f28
.set CYDEV_TMR3_PER1, 0x40004f29
.set CYDEV_TMR3_CNT_CMP0, 0x40004f2a
.set CYDEV_TMR3_CNT_CMP1, 0x40004f2b
.set CYDEV_TMR3_CAP0, 0x40004f2c
.set CYDEV_TMR3_CAP1, 0x40004f2d
.set CYDEV_TMR3_RT0, 0x40004f2e
.set CYDEV_TMR3_RT1, 0x40004f2f
.set CYDEV_IO_BASE, 0x40005000
.set CYDEV_IO_SIZE, 0x00000200
.set CYDEV_IO_PC_BASE, 0x40005000
.set CYDEV_IO_PC_SIZE, 0x00000080
.set CYDEV_IO_PC_PRT0_BASE, 0x40005000
.set CYDEV_IO_PC_PRT0_SIZE, 0x00000008
.set CYDEV_IO_PC_PRT0_PC0, 0x40005000
.set CYDEV_IO_PC_PRT0_PC1, 0x40005001
.set CYDEV_IO_PC_PRT0_PC2, 0x40005002
.set CYDEV_IO_PC_PRT0_PC3, 0x40005003
.set CYDEV_IO_PC_PRT0_PC4, 0x40005004
.set CYDEV_IO_PC_PRT0_PC5, 0x40005005
.set CYDEV_IO_PC_PRT0_PC6, 0x40005006
.set CYDEV_IO_PC_PRT0_PC7, 0x40005007
.set CYDEV_IO_PC_PRT1_BASE, 0x40005008
.set CYDEV_IO_PC_PRT1_SIZE, 0x00000008
.set CYDEV_IO_PC_PRT1_PC0, 0x40005008
.set CYDEV_IO_PC_PRT1_PC1, 0x40005009
.set CYDEV_IO_PC_PRT1_PC2, 0x4000500a
.set CYDEV_IO_PC_PRT1_PC3, 0x4000500b
.set CYDEV_IO_PC_PRT1_PC4, 0x4000500c
.set CYDEV_IO_PC_PRT1_PC5, 0x4000500d
.set CYDEV_IO_PC_PRT1_PC6, 0x4000500e
.set CYDEV_IO_PC_PRT1_PC7, 0x4000500f
.set CYDEV_IO_PC_PRT2_BASE, 0x40005010
.set CYDEV_IO_PC_PRT2_SIZE, 0x00000008
.set CYDEV_IO_PC_PRT2_PC0, 0x40005010
.set CYDEV_IO_PC_PRT2_PC1, 0x40005011
.set CYDEV_IO_PC_PRT2_PC2, 0x40005012
.set CYDEV_IO_PC_PRT2_PC3, 0x40005013
.set CYDEV_IO_PC_PRT2_PC4, 0x40005014
.set CYDEV_IO_PC_PRT2_PC5, 0x40005015
.set CYDEV_IO_PC_PRT2_PC6, 0x40005016
.set CYDEV_IO_PC_PRT2_PC7, 0x40005017
.set CYDEV_IO_PC_PRT3_BASE, 0x40005018
.set CYDEV_IO_PC_PRT3_SIZE, 0x00000008
.set CYDEV_IO_PC_PRT3_PC0, 0x40005018
.set CYDEV_IO_PC_PRT3_PC1, 0x40005019
.set CYDEV_IO_PC_PRT3_PC2, 0x4000501a
.set CYDEV_IO_PC_PRT3_PC3, 0x4000501b
.set CYDEV_IO_PC_PRT3_PC4, 0x4000501c
.set CYDEV_IO_PC_PRT3_PC5, 0x4000501d
.set CYDEV_IO_PC_PRT3_PC6, 0x4000501e
.set CYDEV_IO_PC_PRT3_PC7, 0x4000501f
.set CYDEV_IO_PC_PRT4_BASE, 0x40005020
.set CYDEV_IO_PC_PRT4_SIZE, 0x00000008
.set CYDEV_IO_PC_PRT4_PC0, 0x40005020
.set CYDEV_IO_PC_PRT4_PC1, 0x40005021
.set CYDEV_IO_PC_PRT4_PC2, 0x40005022
.set CYDEV_IO_PC_PRT4_PC3, 0x40005023
.set CYDEV_IO_PC_PRT4_PC4, 0x40005024
.set CYDEV_IO_PC_PRT4_PC5, 0x40005025
.set CYDEV_IO_PC_PRT4_PC6, 0x40005026
.set CYDEV_IO_PC_PRT4_PC7, 0x40005027
.set CYDEV_IO_PC_PRT5_BASE, 0x40005028
.set CYDEV_IO_PC_PRT5_SIZE, 0x00000008
.set CYDEV_IO_PC_PRT5_PC0, 0x40005028
.set CYDEV_IO_PC_PRT5_PC1, 0x40005029
.set CYDEV_IO_PC_PRT5_PC2, 0x4000502a
.set CYDEV_IO_PC_PRT5_PC3, 0x4000502b
.set CYDEV_IO_PC_PRT5_PC4, 0x4000502c
.set CYDEV_IO_PC_PRT5_PC5, 0x4000502d
.set CYDEV_IO_PC_PRT5_PC6, 0x4000502e
.set CYDEV_IO_PC_PRT5_PC7, 0x4000502f
.set CYDEV_IO_PC_PRT6_BASE, 0x40005030
.set CYDEV_IO_PC_PRT6_SIZE, 0x00000008
.set CYDEV_IO_PC_PRT6_PC0, 0x40005030
.set CYDEV_IO_PC_PRT6_PC1, 0x40005031
.set CYDEV_IO_PC_PRT6_PC2, 0x40005032
.set CYDEV_IO_PC_PRT6_PC3, 0x40005033
.set CYDEV_IO_PC_PRT6_PC4, 0x40005034
.set CYDEV_IO_PC_PRT6_PC5, 0x40005035
.set CYDEV_IO_PC_PRT6_PC6, 0x40005036
.set CYDEV_IO_PC_PRT6_PC7, 0x40005037
.set CYDEV_IO_PC_PRT12_BASE, 0x40005060
.set CYDEV_IO_PC_PRT12_SIZE, 0x00000008
.set CYDEV_IO_PC_PRT12_PC0, 0x40005060
.set CYDEV_IO_PC_PRT12_PC1, 0x40005061
.set CYDEV_IO_PC_PRT12_PC2, 0x40005062
.set CYDEV_IO_PC_PRT12_PC3, 0x40005063
.set CYDEV_IO_PC_PRT12_PC4, 0x40005064
.set CYDEV_IO_PC_PRT12_PC5, 0x40005065
.set CYDEV_IO_PC_PRT12_PC6, 0x40005066
.set CYDEV_IO_PC_PRT12_PC7, 0x40005067
.set CYDEV_IO_PC_PRT15_BASE, 0x40005078
.set CYDEV_IO_PC_PRT15_SIZE, 0x00000006
.set CYDEV_IO_PC_PRT15_PC0, 0x40005078
.set CYDEV_IO_PC_PRT15_PC1, 0x40005079
.set CYDEV_IO_PC_PRT15_PC2, 0x4000507a
.set CYDEV_IO_PC_PRT15_PC3, 0x4000507b
.set CYDEV_IO_PC_PRT15_PC4, 0x4000507c
.set CYDEV_IO_PC_PRT15_PC5, 0x4000507d
.set CYDEV_IO_PC_PRT15_7_6_BASE, 0x4000507e
.set CYDEV_IO_PC_PRT15_7_6_SIZE, 0x00000002
.set CYDEV_IO_PC_PRT15_7_6_PC0, 0x4000507e
.set CYDEV_IO_PC_PRT15_7_6_PC1, 0x4000507f
.set CYDEV_IO_DR_BASE, 0x40005080
.set CYDEV_IO_DR_SIZE, 0x00000010
.set CYDEV_IO_DR_PRT0_BASE, 0x40005080
.set CYDEV_IO_DR_PRT0_SIZE, 0x00000001
.set CYDEV_IO_DR_PRT0_DR_ALIAS, 0x40005080
.set CYDEV_IO_DR_PRT1_BASE, 0x40005081
.set CYDEV_IO_DR_PRT1_SIZE, 0x00000001
.set CYDEV_IO_DR_PRT1_DR_ALIAS, 0x40005081
.set CYDEV_IO_DR_PRT2_BASE, 0x40005082
.set CYDEV_IO_DR_PRT2_SIZE, 0x00000001
.set CYDEV_IO_DR_PRT2_DR_ALIAS, 0x40005082
.set CYDEV_IO_DR_PRT3_BASE, 0x40005083
.set CYDEV_IO_DR_PRT3_SIZE, 0x00000001
.set CYDEV_IO_DR_PRT3_DR_ALIAS, 0x40005083
.set CYDEV_IO_DR_PRT4_BASE, 0x40005084
.set CYDEV_IO_DR_PRT4_SIZE, 0x00000001
.set CYDEV_IO_DR_PRT4_DR_ALIAS, 0x40005084
.set CYDEV_IO_DR_PRT5_BASE, 0x40005085
.set CYDEV_IO_DR_PRT5_SIZE, 0x00000001
.set CYDEV_IO_DR_PRT5_DR_ALIAS, 0x40005085
.set CYDEV_IO_DR_PRT6_BASE, 0x40005086
.set CYDEV_IO_DR_PRT6_SIZE, 0x00000001
.set CYDEV_IO_DR_PRT6_DR_ALIAS, 0x40005086
.set CYDEV_IO_DR_PRT12_BASE, 0x4000508c
.set CYDEV_IO_DR_PRT12_SIZE, 0x00000001
.set CYDEV_IO_DR_PRT12_DR_ALIAS, 0x4000508c
.set CYDEV_IO_DR_PRT15_BASE, 0x4000508f
.set CYDEV_IO_DR_PRT15_SIZE, 0x00000001
.set CYDEV_IO_DR_PRT15_DR_15_ALIAS, 0x4000508f
.set CYDEV_IO_PS_BASE, 0x40005090
.set CYDEV_IO_PS_SIZE, 0x00000010
.set CYDEV_IO_PS_PRT0_BASE, 0x40005090
.set CYDEV_IO_PS_PRT0_SIZE, 0x00000001
.set CYDEV_IO_PS_PRT0_PS_ALIAS, 0x40005090
.set CYDEV_IO_PS_PRT1_BASE, 0x40005091
.set CYDEV_IO_PS_PRT1_SIZE, 0x00000001
.set CYDEV_IO_PS_PRT1_PS_ALIAS, 0x40005091
.set CYDEV_IO_PS_PRT2_BASE, 0x40005092
.set CYDEV_IO_PS_PRT2_SIZE, 0x00000001
.set CYDEV_IO_PS_PRT2_PS_ALIAS, 0x40005092
.set CYDEV_IO_PS_PRT3_BASE, 0x40005093
.set CYDEV_IO_PS_PRT3_SIZE, 0x00000001
.set CYDEV_IO_PS_PRT3_PS_ALIAS, 0x40005093
.set CYDEV_IO_PS_PRT4_BASE, 0x40005094
.set CYDEV_IO_PS_PRT4_SIZE, 0x00000001
.set CYDEV_IO_PS_PRT4_PS_ALIAS, 0x40005094
.set CYDEV_IO_PS_PRT5_BASE, 0x40005095
.set CYDEV_IO_PS_PRT5_SIZE, 0x00000001
.set CYDEV_IO_PS_PRT5_PS_ALIAS, 0x40005095
.set CYDEV_IO_PS_PRT6_BASE, 0x40005096
.set CYDEV_IO_PS_PRT6_SIZE, 0x00000001
.set CYDEV_IO_PS_PRT6_PS_ALIAS, 0x40005096
.set CYDEV_IO_PS_PRT12_BASE, 0x4000509c
.set CYDEV_IO_PS_PRT12_SIZE, 0x00000001
.set CYDEV_IO_PS_PRT12_PS_ALIAS, 0x4000509c
.set CYDEV_IO_PS_PRT15_BASE, 0x4000509f
.set CYDEV_IO_PS_PRT15_SIZE, 0x00000001
.set CYDEV_IO_PS_PRT15_PS15_ALIAS, 0x4000509f
.set CYDEV_IO_PRT_BASE, 0x40005100
.set CYDEV_IO_PRT_SIZE, 0x00000100
.set CYDEV_IO_PRT_PRT0_BASE, 0x40005100
.set CYDEV_IO_PRT_PRT0_SIZE, 0x00000010
.set CYDEV_IO_PRT_PRT0_DR, 0x40005100
.set CYDEV_IO_PRT_PRT0_PS, 0x40005101
.set CYDEV_IO_PRT_PRT0_DM0, 0x40005102
.set CYDEV_IO_PRT_PRT0_DM1, 0x40005103
.set CYDEV_IO_PRT_PRT0_DM2, 0x40005104
.set CYDEV_IO_PRT_PRT0_SLW, 0x40005105
.set CYDEV_IO_PRT_PRT0_BYP, 0x40005106
.set CYDEV_IO_PRT_PRT0_BIE, 0x40005107
.set CYDEV_IO_PRT_PRT0_INP_DIS, 0x40005108
.set CYDEV_IO_PRT_PRT0_CTL, 0x40005109
.set CYDEV_IO_PRT_PRT0_PRT, 0x4000510a
.set CYDEV_IO_PRT_PRT0_BIT_MASK, 0x4000510b
.set CYDEV_IO_PRT_PRT0_AMUX, 0x4000510c
.set CYDEV_IO_PRT_PRT0_AG, 0x4000510d
.set CYDEV_IO_PRT_PRT0_LCD_COM_SEG, 0x4000510e
.set CYDEV_IO_PRT_PRT0_LCD_EN, 0x4000510f
.set CYDEV_IO_PRT_PRT1_BASE, 0x40005110
.set CYDEV_IO_PRT_PRT1_SIZE, 0x00000010
.set CYDEV_IO_PRT_PRT1_DR, 0x40005110
.set CYDEV_IO_PRT_PRT1_PS, 0x40005111
.set CYDEV_IO_PRT_PRT1_DM0, 0x40005112
.set CYDEV_IO_PRT_PRT1_DM1, 0x40005113
.set CYDEV_IO_PRT_PRT1_DM2, 0x40005114
.set CYDEV_IO_PRT_PRT1_SLW, 0x40005115
.set CYDEV_IO_PRT_PRT1_BYP, 0x40005116
.set CYDEV_IO_PRT_PRT1_BIE, 0x40005117
.set CYDEV_IO_PRT_PRT1_INP_DIS, 0x40005118
.set CYDEV_IO_PRT_PRT1_CTL, 0x40005119
.set CYDEV_IO_PRT_PRT1_PRT, 0x4000511a
.set CYDEV_IO_PRT_PRT1_BIT_MASK, 0x4000511b
.set CYDEV_IO_PRT_PRT1_AMUX, 0x4000511c
.set CYDEV_IO_PRT_PRT1_AG, 0x4000511d
.set CYDEV_IO_PRT_PRT1_LCD_COM_SEG, 0x4000511e
.set CYDEV_IO_PRT_PRT1_LCD_EN, 0x4000511f
.set CYDEV_IO_PRT_PRT2_BASE, 0x40005120
.set CYDEV_IO_PRT_PRT2_SIZE, 0x00000010
.set CYDEV_IO_PRT_PRT2_DR, 0x40005120
.set CYDEV_IO_PRT_PRT2_PS, 0x40005121
.set CYDEV_IO_PRT_PRT2_DM0, 0x40005122
.set CYDEV_IO_PRT_PRT2_DM1, 0x40005123
.set CYDEV_IO_PRT_PRT2_DM2, 0x40005124
.set CYDEV_IO_PRT_PRT2_SLW, 0x40005125
.set CYDEV_IO_PRT_PRT2_BYP, 0x40005126
.set CYDEV_IO_PRT_PRT2_BIE, 0x40005127
.set CYDEV_IO_PRT_PRT2_INP_DIS, 0x40005128
.set CYDEV_IO_PRT_PRT2_CTL, 0x40005129
.set CYDEV_IO_PRT_PRT2_PRT, 0x4000512a
.set CYDEV_IO_PRT_PRT2_BIT_MASK, 0x4000512b
.set CYDEV_IO_PRT_PRT2_AMUX, 0x4000512c
.set CYDEV_IO_PRT_PRT2_AG, 0x4000512d
.set CYDEV_IO_PRT_PRT2_LCD_COM_SEG, 0x4000512e
.set CYDEV_IO_PRT_PRT2_LCD_EN, 0x4000512f
.set CYDEV_IO_PRT_PRT3_BASE, 0x40005130
.set CYDEV_IO_PRT_PRT3_SIZE, 0x00000010
.set CYDEV_IO_PRT_PRT3_DR, 0x40005130
.set CYDEV_IO_PRT_PRT3_PS, 0x40005131
.set CYDEV_IO_PRT_PRT3_DM0, 0x40005132
.set CYDEV_IO_PRT_PRT3_DM1, 0x40005133
.set CYDEV_IO_PRT_PRT3_DM2, 0x40005134
.set CYDEV_IO_PRT_PRT3_SLW, 0x40005135
.set CYDEV_IO_PRT_PRT3_BYP, 0x40005136
.set CYDEV_IO_PRT_PRT3_BIE, 0x40005137
.set CYDEV_IO_PRT_PRT3_INP_DIS, 0x40005138
.set CYDEV_IO_PRT_PRT3_CTL, 0x40005139
.set CYDEV_IO_PRT_PRT3_PRT, 0x4000513a
.set CYDEV_IO_PRT_PRT3_BIT_MASK, 0x4000513b
.set CYDEV_IO_PRT_PRT3_AMUX, 0x4000513c
.set CYDEV_IO_PRT_PRT3_AG, 0x4000513d
.set CYDEV_IO_PRT_PRT3_LCD_COM_SEG, 0x4000513e
.set CYDEV_IO_PRT_PRT3_LCD_EN, 0x4000513f
.set CYDEV_IO_PRT_PRT4_BASE, 0x40005140
.set CYDEV_IO_PRT_PRT4_SIZE, 0x00000010
.set CYDEV_IO_PRT_PRT4_DR, 0x40005140
.set CYDEV_IO_PRT_PRT4_PS, 0x40005141
.set CYDEV_IO_PRT_PRT4_DM0, 0x40005142
.set CYDEV_IO_PRT_PRT4_DM1, 0x40005143
.set CYDEV_IO_PRT_PRT4_DM2, 0x40005144
.set CYDEV_IO_PRT_PRT4_SLW, 0x40005145
.set CYDEV_IO_PRT_PRT4_BYP, 0x40005146
.set CYDEV_IO_PRT_PRT4_BIE, 0x40005147
.set CYDEV_IO_PRT_PRT4_INP_DIS, 0x40005148
.set CYDEV_IO_PRT_PRT4_CTL, 0x40005149
.set CYDEV_IO_PRT_PRT4_PRT, 0x4000514a
.set CYDEV_IO_PRT_PRT4_BIT_MASK, 0x4000514b
.set CYDEV_IO_PRT_PRT4_AMUX, 0x4000514c
.set CYDEV_IO_PRT_PRT4_AG, 0x4000514d
.set CYDEV_IO_PRT_PRT4_LCD_COM_SEG, 0x4000514e
.set CYDEV_IO_PRT_PRT4_LCD_EN, 0x4000514f
.set CYDEV_IO_PRT_PRT5_BASE, 0x40005150
.set CYDEV_IO_PRT_PRT5_SIZE, 0x00000010
.set CYDEV_IO_PRT_PRT5_DR, 0x40005150
.set CYDEV_IO_PRT_PRT5_PS, 0x40005151
.set CYDEV_IO_PRT_PRT5_DM0, 0x40005152
.set CYDEV_IO_PRT_PRT5_DM1, 0x40005153
.set CYDEV_IO_PRT_PRT5_DM2, 0x40005154
.set CYDEV_IO_PRT_PRT5_SLW, 0x40005155
.set CYDEV_IO_PRT_PRT5_BYP, 0x40005156
.set CYDEV_IO_PRT_PRT5_BIE, 0x40005157
.set CYDEV_IO_PRT_PRT5_INP_DIS, 0x40005158
.set CYDEV_IO_PRT_PRT5_CTL, 0x40005159
.set CYDEV_IO_PRT_PRT5_PRT, 0x4000515a
.set CYDEV_IO_PRT_PRT5_BIT_MASK, 0x4000515b
.set CYDEV_IO_PRT_PRT5_AMUX, 0x4000515c
.set CYDEV_IO_PRT_PRT5_AG, 0x4000515d
.set CYDEV_IO_PRT_PRT5_LCD_COM_SEG, 0x4000515e
.set CYDEV_IO_PRT_PRT5_LCD_EN, 0x4000515f
.set CYDEV_IO_PRT_PRT6_BASE, 0x40005160
.set CYDEV_IO_PRT_PRT6_SIZE, 0x00000010
.set CYDEV_IO_PRT_PRT6_DR, 0x40005160
.set CYDEV_IO_PRT_PRT6_PS, 0x40005161
.set CYDEV_IO_PRT_PRT6_DM0, 0x40005162
.set CYDEV_IO_PRT_PRT6_DM1, 0x40005163
.set CYDEV_IO_PRT_PRT6_DM2, 0x40005164
.set CYDEV_IO_PRT_PRT6_SLW, 0x40005165
.set CYDEV_IO_PRT_PRT6_BYP, 0x40005166
.set CYDEV_IO_PRT_PRT6_BIE, 0x40005167
.set CYDEV_IO_PRT_PRT6_INP_DIS, 0x40005168
.set CYDEV_IO_PRT_PRT6_CTL, 0x40005169
.set CYDEV_IO_PRT_PRT6_PRT, 0x4000516a
.set CYDEV_IO_PRT_PRT6_BIT_MASK, 0x4000516b
.set CYDEV_IO_PRT_PRT6_AMUX, 0x4000516c
.set CYDEV_IO_PRT_PRT6_AG, 0x4000516d
.set CYDEV_IO_PRT_PRT6_LCD_COM_SEG, 0x4000516e
.set CYDEV_IO_PRT_PRT6_LCD_EN, 0x4000516f
.set CYDEV_IO_PRT_PRT12_BASE, 0x400051c0
.set CYDEV_IO_PRT_PRT12_SIZE, 0x00000010
.set CYDEV_IO_PRT_PRT12_DR, 0x400051c0
.set CYDEV_IO_PRT_PRT12_PS, 0x400051c1
.set CYDEV_IO_PRT_PRT12_DM0, 0x400051c2
.set CYDEV_IO_PRT_PRT12_DM1, 0x400051c3
.set CYDEV_IO_PRT_PRT12_DM2, 0x400051c4
.set CYDEV_IO_PRT_PRT12_SLW, 0x400051c5
.set CYDEV_IO_PRT_PRT12_BYP, 0x400051c6
.set CYDEV_IO_PRT_PRT12_BIE, 0x400051c7
.set CYDEV_IO_PRT_PRT12_INP_DIS, 0x400051c8
.set CYDEV_IO_PRT_PRT12_SIO_HYST_EN, 0x400051c9
.set CYDEV_IO_PRT_PRT12_PRT, 0x400051ca
.set CYDEV_IO_PRT_PRT12_BIT_MASK, 0x400051cb
.set CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ, 0x400051cc
.set CYDEV_IO_PRT_PRT12_AG, 0x400051cd
.set CYDEV_IO_PRT_PRT12_SIO_CFG, 0x400051ce
.set CYDEV_IO_PRT_PRT12_SIO_DIFF, 0x400051cf
.set CYDEV_IO_PRT_PRT15_BASE, 0x400051f0
.set CYDEV_IO_PRT_PRT15_SIZE, 0x00000010
.set CYDEV_IO_PRT_PRT15_DR, 0x400051f0
.set CYDEV_IO_PRT_PRT15_PS, 0x400051f1
.set CYDEV_IO_PRT_PRT15_DM0, 0x400051f2
.set CYDEV_IO_PRT_PRT15_DM1, 0x400051f3
.set CYDEV_IO_PRT_PRT15_DM2, 0x400051f4
.set CYDEV_IO_PRT_PRT15_SLW, 0x400051f5
.set CYDEV_IO_PRT_PRT15_BYP, 0x400051f6
.set CYDEV_IO_PRT_PRT15_BIE, 0x400051f7
.set CYDEV_IO_PRT_PRT15_INP_DIS, 0x400051f8
.set CYDEV_IO_PRT_PRT15_CTL, 0x400051f9
.set CYDEV_IO_PRT_PRT15_PRT, 0x400051fa
.set CYDEV_IO_PRT_PRT15_BIT_MASK, 0x400051fb
.set CYDEV_IO_PRT_PRT15_AMUX, 0x400051fc
.set CYDEV_IO_PRT_PRT15_AG, 0x400051fd
.set CYDEV_IO_PRT_PRT15_LCD_COM_SEG, 0x400051fe
.set CYDEV_IO_PRT_PRT15_LCD_EN, 0x400051ff
.set CYDEV_PRTDSI_BASE, 0x40005200
.set CYDEV_PRTDSI_SIZE, 0x0000007f
.set CYDEV_PRTDSI_PRT0_BASE, 0x40005200
.set CYDEV_PRTDSI_PRT0_SIZE, 0x00000007
.set CYDEV_PRTDSI_PRT0_OUT_SEL0, 0x40005200
.set CYDEV_PRTDSI_PRT0_OUT_SEL1, 0x40005201
.set CYDEV_PRTDSI_PRT0_OE_SEL0, 0x40005202
.set CYDEV_PRTDSI_PRT0_OE_SEL1, 0x40005203
.set CYDEV_PRTDSI_PRT0_DBL_SYNC_IN, 0x40005204
.set CYDEV_PRTDSI_PRT0_SYNC_OUT, 0x40005205
.set CYDEV_PRTDSI_PRT0_CAPS_SEL, 0x40005206
.set CYDEV_PRTDSI_PRT1_BASE, 0x40005208
.set CYDEV_PRTDSI_PRT1_SIZE, 0x00000007
.set CYDEV_PRTDSI_PRT1_OUT_SEL0, 0x40005208
.set CYDEV_PRTDSI_PRT1_OUT_SEL1, 0x40005209
.set CYDEV_PRTDSI_PRT1_OE_SEL0, 0x4000520a
.set CYDEV_PRTDSI_PRT1_OE_SEL1, 0x4000520b
.set CYDEV_PRTDSI_PRT1_DBL_SYNC_IN, 0x4000520c
.set CYDEV_PRTDSI_PRT1_SYNC_OUT, 0x4000520d
.set CYDEV_PRTDSI_PRT1_CAPS_SEL, 0x4000520e
.set CYDEV_PRTDSI_PRT2_BASE, 0x40005210
.set CYDEV_PRTDSI_PRT2_SIZE, 0x00000007
.set CYDEV_PRTDSI_PRT2_OUT_SEL0, 0x40005210
.set CYDEV_PRTDSI_PRT2_OUT_SEL1, 0x40005211
.set CYDEV_PRTDSI_PRT2_OE_SEL0, 0x40005212
.set CYDEV_PRTDSI_PRT2_OE_SEL1, 0x40005213
.set CYDEV_PRTDSI_PRT2_DBL_SYNC_IN, 0x40005214
.set CYDEV_PRTDSI_PRT2_SYNC_OUT, 0x40005215
.set CYDEV_PRTDSI_PRT2_CAPS_SEL, 0x40005216
.set CYDEV_PRTDSI_PRT3_BASE, 0x40005218
.set CYDEV_PRTDSI_PRT3_SIZE, 0x00000007
.set CYDEV_PRTDSI_PRT3_OUT_SEL0, 0x40005218
.set CYDEV_PRTDSI_PRT3_OUT_SEL1, 0x40005219
.set CYDEV_PRTDSI_PRT3_OE_SEL0, 0x4000521a
.set CYDEV_PRTDSI_PRT3_OE_SEL1, 0x4000521b
.set CYDEV_PRTDSI_PRT3_DBL_SYNC_IN, 0x4000521c
.set CYDEV_PRTDSI_PRT3_SYNC_OUT, 0x4000521d
.set CYDEV_PRTDSI_PRT3_CAPS_SEL, 0x4000521e
.set CYDEV_PRTDSI_PRT4_BASE, 0x40005220
.set CYDEV_PRTDSI_PRT4_SIZE, 0x00000007
.set CYDEV_PRTDSI_PRT4_OUT_SEL0, 0x40005220
.set CYDEV_PRTDSI_PRT4_OUT_SEL1, 0x40005221
.set CYDEV_PRTDSI_PRT4_OE_SEL0, 0x40005222
.set CYDEV_PRTDSI_PRT4_OE_SEL1, 0x40005223
.set CYDEV_PRTDSI_PRT4_DBL_SYNC_IN, 0x40005224
.set CYDEV_PRTDSI_PRT4_SYNC_OUT, 0x40005225
.set CYDEV_PRTDSI_PRT4_CAPS_SEL, 0x40005226
.set CYDEV_PRTDSI_PRT5_BASE, 0x40005228
.set CYDEV_PRTDSI_PRT5_SIZE, 0x00000007
.set CYDEV_PRTDSI_PRT5_OUT_SEL0, 0x40005228
.set CYDEV_PRTDSI_PRT5_OUT_SEL1, 0x40005229
.set CYDEV_PRTDSI_PRT5_OE_SEL0, 0x4000522a
.set CYDEV_PRTDSI_PRT5_OE_SEL1, 0x4000522b
.set CYDEV_PRTDSI_PRT5_DBL_SYNC_IN, 0x4000522c
.set CYDEV_PRTDSI_PRT5_SYNC_OUT, 0x4000522d
.set CYDEV_PRTDSI_PRT5_CAPS_SEL, 0x4000522e
.set CYDEV_PRTDSI_PRT6_BASE, 0x40005230
.set CYDEV_PRTDSI_PRT6_SIZE, 0x00000007
.set CYDEV_PRTDSI_PRT6_OUT_SEL0, 0x40005230
.set CYDEV_PRTDSI_PRT6_OUT_SEL1, 0x40005231
.set CYDEV_PRTDSI_PRT6_OE_SEL0, 0x40005232
.set CYDEV_PRTDSI_PRT6_OE_SEL1, 0x40005233
.set CYDEV_PRTDSI_PRT6_DBL_SYNC_IN, 0x40005234
.set CYDEV_PRTDSI_PRT6_SYNC_OUT, 0x40005235
.set CYDEV_PRTDSI_PRT6_CAPS_SEL, 0x40005236
.set CYDEV_PRTDSI_PRT12_BASE, 0x40005260
.set CYDEV_PRTDSI_PRT12_SIZE, 0x00000006
.set CYDEV_PRTDSI_PRT12_OUT_SEL0, 0x40005260
.set CYDEV_PRTDSI_PRT12_OUT_SEL1, 0x40005261
.set CYDEV_PRTDSI_PRT12_OE_SEL0, 0x40005262
.set CYDEV_PRTDSI_PRT12_OE_SEL1, 0x40005263
.set CYDEV_PRTDSI_PRT12_DBL_SYNC_IN, 0x40005264
.set CYDEV_PRTDSI_PRT12_SYNC_OUT, 0x40005265
.set CYDEV_PRTDSI_PRT15_BASE, 0x40005278
.set CYDEV_PRTDSI_PRT15_SIZE, 0x00000007
.set CYDEV_PRTDSI_PRT15_OUT_SEL0, 0x40005278
.set CYDEV_PRTDSI_PRT15_OUT_SEL1, 0x40005279
.set CYDEV_PRTDSI_PRT15_OE_SEL0, 0x4000527a
.set CYDEV_PRTDSI_PRT15_OE_SEL1, 0x4000527b
.set CYDEV_PRTDSI_PRT15_DBL_SYNC_IN, 0x4000527c
.set CYDEV_PRTDSI_PRT15_SYNC_OUT, 0x4000527d
.set CYDEV_PRTDSI_PRT15_CAPS_SEL, 0x4000527e
.set CYDEV_EMIF_BASE, 0x40005400
.set CYDEV_EMIF_SIZE, 0x00000007
.set CYDEV_EMIF_NO_UDB, 0x40005400
.set CYDEV_EMIF_RP_WAIT_STATES, 0x40005401
.set CYDEV_EMIF_MEM_DWN, 0x40005402
.set CYDEV_EMIF_MEMCLK_DIV, 0x40005403
.set CYDEV_EMIF_CLOCK_EN, 0x40005404
.set CYDEV_EMIF_EM_TYPE, 0x40005405
.set CYDEV_EMIF_WP_WAIT_STATES, 0x40005406
.set CYDEV_ANAIF_BASE, 0x40005800
.set CYDEV_ANAIF_SIZE, 0x000003a9
.set CYDEV_ANAIF_CFG_BASE, 0x40005800
.set CYDEV_ANAIF_CFG_SIZE, 0x0000010f
.set CYDEV_ANAIF_CFG_SC0_BASE, 0x40005800
.set CYDEV_ANAIF_CFG_SC0_SIZE, 0x00000003
.set CYDEV_ANAIF_CFG_SC0_CR0, 0x40005800
.set CYDEV_ANAIF_CFG_SC0_CR1, 0x40005801
.set CYDEV_ANAIF_CFG_SC0_CR2, 0x40005802
.set CYDEV_ANAIF_CFG_SC1_BASE, 0x40005804
.set CYDEV_ANAIF_CFG_SC1_SIZE, 0x00000003
.set CYDEV_ANAIF_CFG_SC1_CR0, 0x40005804
.set CYDEV_ANAIF_CFG_SC1_CR1, 0x40005805
.set CYDEV_ANAIF_CFG_SC1_CR2, 0x40005806
.set CYDEV_ANAIF_CFG_SC2_BASE, 0x40005808
.set CYDEV_ANAIF_CFG_SC2_SIZE, 0x00000003
.set CYDEV_ANAIF_CFG_SC2_CR0, 0x40005808
.set CYDEV_ANAIF_CFG_SC2_CR1, 0x40005809
.set CYDEV_ANAIF_CFG_SC2_CR2, 0x4000580a
.set CYDEV_ANAIF_CFG_SC3_BASE, 0x4000580c
.set CYDEV_ANAIF_CFG_SC3_SIZE, 0x00000003
.set CYDEV_ANAIF_CFG_SC3_CR0, 0x4000580c
.set CYDEV_ANAIF_CFG_SC3_CR1, 0x4000580d
.set CYDEV_ANAIF_CFG_SC3_CR2, 0x4000580e
.set CYDEV_ANAIF_CFG_DAC0_BASE, 0x40005820
.set CYDEV_ANAIF_CFG_DAC0_SIZE, 0x00000003
.set CYDEV_ANAIF_CFG_DAC0_CR0, 0x40005820
.set CYDEV_ANAIF_CFG_DAC0_CR1, 0x40005821
.set CYDEV_ANAIF_CFG_DAC0_TST, 0x40005822
.set CYDEV_ANAIF_CFG_DAC1_BASE, 0x40005824
.set CYDEV_ANAIF_CFG_DAC1_SIZE, 0x00000003
.set CYDEV_ANAIF_CFG_DAC1_CR0, 0x40005824
.set CYDEV_ANAIF_CFG_DAC1_CR1, 0x40005825
.set CYDEV_ANAIF_CFG_DAC1_TST, 0x40005826
.set CYDEV_ANAIF_CFG_DAC2_BASE, 0x40005828
.set CYDEV_ANAIF_CFG_DAC2_SIZE, 0x00000003
.set CYDEV_ANAIF_CFG_DAC2_CR0, 0x40005828
.set CYDEV_ANAIF_CFG_DAC2_CR1, 0x40005829
.set CYDEV_ANAIF_CFG_DAC2_TST, 0x4000582a
.set CYDEV_ANAIF_CFG_DAC3_BASE, 0x4000582c
.set CYDEV_ANAIF_CFG_DAC3_SIZE, 0x00000003
.set CYDEV_ANAIF_CFG_DAC3_CR0, 0x4000582c
.set CYDEV_ANAIF_CFG_DAC3_CR1, 0x4000582d
.set CYDEV_ANAIF_CFG_DAC3_TST, 0x4000582e
.set CYDEV_ANAIF_CFG_CMP0_BASE, 0x40005840
.set CYDEV_ANAIF_CFG_CMP0_SIZE, 0x00000001
.set CYDEV_ANAIF_CFG_CMP0_CR, 0x40005840
.set CYDEV_ANAIF_CFG_CMP1_BASE, 0x40005841
.set CYDEV_ANAIF_CFG_CMP1_SIZE, 0x00000001
.set CYDEV_ANAIF_CFG_CMP1_CR, 0x40005841
.set CYDEV_ANAIF_CFG_CMP2_BASE, 0x40005842
.set CYDEV_ANAIF_CFG_CMP2_SIZE, 0x00000001
.set CYDEV_ANAIF_CFG_CMP2_CR, 0x40005842
.set CYDEV_ANAIF_CFG_CMP3_BASE, 0x40005843
.set CYDEV_ANAIF_CFG_CMP3_SIZE, 0x00000001
.set CYDEV_ANAIF_CFG_CMP3_CR, 0x40005843
.set CYDEV_ANAIF_CFG_LUT0_BASE, 0x40005848
.set CYDEV_ANAIF_CFG_LUT0_SIZE, 0x00000002
.set CYDEV_ANAIF_CFG_LUT0_CR, 0x40005848
.set CYDEV_ANAIF_CFG_LUT0_MX, 0x40005849
.set CYDEV_ANAIF_CFG_LUT1_BASE, 0x4000584a
.set CYDEV_ANAIF_CFG_LUT1_SIZE, 0x00000002
.set CYDEV_ANAIF_CFG_LUT1_CR, 0x4000584a
.set CYDEV_ANAIF_CFG_LUT1_MX, 0x4000584b
.set CYDEV_ANAIF_CFG_LUT2_BASE, 0x4000584c
.set CYDEV_ANAIF_CFG_LUT2_SIZE, 0x00000002
.set CYDEV_ANAIF_CFG_LUT2_CR, 0x4000584c
.set CYDEV_ANAIF_CFG_LUT2_MX, 0x4000584d
.set CYDEV_ANAIF_CFG_LUT3_BASE, 0x4000584e
.set CYDEV_ANAIF_CFG_LUT3_SIZE, 0x00000002
.set CYDEV_ANAIF_CFG_LUT3_CR, 0x4000584e
.set CYDEV_ANAIF_CFG_LUT3_MX, 0x4000584f
.set CYDEV_ANAIF_CFG_OPAMP0_BASE, 0x40005858
.set CYDEV_ANAIF_CFG_OPAMP0_SIZE, 0x00000002
.set CYDEV_ANAIF_CFG_OPAMP0_CR, 0x40005858
.set CYDEV_ANAIF_CFG_OPAMP0_RSVD, 0x40005859
.set CYDEV_ANAIF_CFG_OPAMP1_BASE, 0x4000585a
.set CYDEV_ANAIF_CFG_OPAMP1_SIZE, 0x00000002
.set CYDEV_ANAIF_CFG_OPAMP1_CR, 0x4000585a
.set CYDEV_ANAIF_CFG_OPAMP1_RSVD, 0x4000585b
.set CYDEV_ANAIF_CFG_OPAMP2_BASE, 0x4000585c
.set CYDEV_ANAIF_CFG_OPAMP2_SIZE, 0x00000002
.set CYDEV_ANAIF_CFG_OPAMP2_CR, 0x4000585c
.set CYDEV_ANAIF_CFG_OPAMP2_RSVD, 0x4000585d
.set CYDEV_ANAIF_CFG_OPAMP3_BASE, 0x4000585e
.set CYDEV_ANAIF_CFG_OPAMP3_SIZE, 0x00000002
.set CYDEV_ANAIF_CFG_OPAMP3_CR, 0x4000585e
.set CYDEV_ANAIF_CFG_OPAMP3_RSVD, 0x4000585f
.set CYDEV_ANAIF_CFG_LCDDAC_BASE, 0x40005868
.set CYDEV_ANAIF_CFG_LCDDAC_SIZE, 0x00000002
.set CYDEV_ANAIF_CFG_LCDDAC_CR0, 0x40005868
.set CYDEV_ANAIF_CFG_LCDDAC_CR1, 0x40005869
.set CYDEV_ANAIF_CFG_LCDDRV_BASE, 0x4000586a
.set CYDEV_ANAIF_CFG_LCDDRV_SIZE, 0x00000001
.set CYDEV_ANAIF_CFG_LCDDRV_CR, 0x4000586a
.set CYDEV_ANAIF_CFG_LCDTMR_BASE, 0x4000586b
.set CYDEV_ANAIF_CFG_LCDTMR_SIZE, 0x00000001
.set CYDEV_ANAIF_CFG_LCDTMR_CFG, 0x4000586b
.set CYDEV_ANAIF_CFG_BG_BASE, 0x4000586c
.set CYDEV_ANAIF_CFG_BG_SIZE, 0x00000004
.set CYDEV_ANAIF_CFG_BG_CR0, 0x4000586c
.set CYDEV_ANAIF_CFG_BG_RSVD, 0x4000586d
.set CYDEV_ANAIF_CFG_BG_DFT0, 0x4000586e
.set CYDEV_ANAIF_CFG_BG_DFT1, 0x4000586f
.set CYDEV_ANAIF_CFG_CAPSL_BASE, 0x40005870
.set CYDEV_ANAIF_CFG_CAPSL_SIZE, 0x00000002
.set CYDEV_ANAIF_CFG_CAPSL_CFG0, 0x40005870
.set CYDEV_ANAIF_CFG_CAPSL_CFG1, 0x40005871
.set CYDEV_ANAIF_CFG_CAPSR_BASE, 0x40005872
.set CYDEV_ANAIF_CFG_CAPSR_SIZE, 0x00000002
.set CYDEV_ANAIF_CFG_CAPSR_CFG0, 0x40005872
.set CYDEV_ANAIF_CFG_CAPSR_CFG1, 0x40005873
.set CYDEV_ANAIF_CFG_PUMP_BASE, 0x40005876
.set CYDEV_ANAIF_CFG_PUMP_SIZE, 0x00000002
.set CYDEV_ANAIF_CFG_PUMP_CR0, 0x40005876
.set CYDEV_ANAIF_CFG_PUMP_CR1, 0x40005877
.set CYDEV_ANAIF_CFG_LPF0_BASE, 0x40005878
.set CYDEV_ANAIF_CFG_LPF0_SIZE, 0x00000002
.set CYDEV_ANAIF_CFG_LPF0_CR0, 0x40005878
.set CYDEV_ANAIF_CFG_LPF0_RSVD, 0x40005879
.set CYDEV_ANAIF_CFG_LPF1_BASE, 0x4000587a
.set CYDEV_ANAIF_CFG_LPF1_SIZE, 0x00000002
.set CYDEV_ANAIF_CFG_LPF1_CR0, 0x4000587a
.set CYDEV_ANAIF_CFG_LPF1_RSVD, 0x4000587b
.set CYDEV_ANAIF_CFG_MISC_BASE, 0x4000587c
.set CYDEV_ANAIF_CFG_MISC_SIZE, 0x00000001
.set CYDEV_ANAIF_CFG_MISC_CR0, 0x4000587c
.set CYDEV_ANAIF_CFG_DSM0_BASE, 0x40005880
.set CYDEV_ANAIF_CFG_DSM0_SIZE, 0x00000020
.set CYDEV_ANAIF_CFG_DSM0_CR0, 0x40005880
.set CYDEV_ANAIF_CFG_DSM0_CR1, 0x40005881
.set CYDEV_ANAIF_CFG_DSM0_CR2, 0x40005882
.set CYDEV_ANAIF_CFG_DSM0_CR3, 0x40005883
.set CYDEV_ANAIF_CFG_DSM0_CR4, 0x40005884
.set CYDEV_ANAIF_CFG_DSM0_CR5, 0x40005885
.set CYDEV_ANAIF_CFG_DSM0_CR6, 0x40005886
.set CYDEV_ANAIF_CFG_DSM0_CR7, 0x40005887
.set CYDEV_ANAIF_CFG_DSM0_CR8, 0x40005888
.set CYDEV_ANAIF_CFG_DSM0_CR9, 0x40005889
.set CYDEV_ANAIF_CFG_DSM0_CR10, 0x4000588a
.set CYDEV_ANAIF_CFG_DSM0_CR11, 0x4000588b
.set CYDEV_ANAIF_CFG_DSM0_CR12, 0x4000588c
.set CYDEV_ANAIF_CFG_DSM0_CR13, 0x4000588d
.set CYDEV_ANAIF_CFG_DSM0_CR14, 0x4000588e
.set CYDEV_ANAIF_CFG_DSM0_CR15, 0x4000588f
.set CYDEV_ANAIF_CFG_DSM0_CR16, 0x40005890
.set CYDEV_ANAIF_CFG_DSM0_CR17, 0x40005891
.set CYDEV_ANAIF_CFG_DSM0_REF0, 0x40005892
.set CYDEV_ANAIF_CFG_DSM0_REF1, 0x40005893
.set CYDEV_ANAIF_CFG_DSM0_REF2, 0x40005894
.set CYDEV_ANAIF_CFG_DSM0_REF3, 0x40005895
.set CYDEV_ANAIF_CFG_DSM0_DEM0, 0x40005896
.set CYDEV_ANAIF_CFG_DSM0_DEM1, 0x40005897
.set CYDEV_ANAIF_CFG_DSM0_TST0, 0x40005898
.set CYDEV_ANAIF_CFG_DSM0_TST1, 0x40005899
.set CYDEV_ANAIF_CFG_DSM0_BUF0, 0x4000589a
.set CYDEV_ANAIF_CFG_DSM0_BUF1, 0x4000589b
.set CYDEV_ANAIF_CFG_DSM0_BUF2, 0x4000589c
.set CYDEV_ANAIF_CFG_DSM0_BUF3, 0x4000589d
.set CYDEV_ANAIF_CFG_DSM0_MISC, 0x4000589e
.set CYDEV_ANAIF_CFG_DSM0_RSVD1, 0x4000589f
.set CYDEV_ANAIF_CFG_SAR0_BASE, 0x40005900
.set CYDEV_ANAIF_CFG_SAR0_SIZE, 0x00000007
.set CYDEV_ANAIF_CFG_SAR0_CSR0, 0x40005900
.set CYDEV_ANAIF_CFG_SAR0_CSR1, 0x40005901
.set CYDEV_ANAIF_CFG_SAR0_CSR2, 0x40005902
.set CYDEV_ANAIF_CFG_SAR0_CSR3, 0x40005903
.set CYDEV_ANAIF_CFG_SAR0_CSR4, 0x40005904
.set CYDEV_ANAIF_CFG_SAR0_CSR5, 0x40005905
.set CYDEV_ANAIF_CFG_SAR0_CSR6, 0x40005906
.set CYDEV_ANAIF_CFG_SAR1_BASE, 0x40005908
.set CYDEV_ANAIF_CFG_SAR1_SIZE, 0x00000007
.set CYDEV_ANAIF_CFG_SAR1_CSR0, 0x40005908
.set CYDEV_ANAIF_CFG_SAR1_CSR1, 0x40005909
.set CYDEV_ANAIF_CFG_SAR1_CSR2, 0x4000590a
.set CYDEV_ANAIF_CFG_SAR1_CSR3, 0x4000590b
.set CYDEV_ANAIF_CFG_SAR1_CSR4, 0x4000590c
.set CYDEV_ANAIF_CFG_SAR1_CSR5, 0x4000590d
.set CYDEV_ANAIF_CFG_SAR1_CSR6, 0x4000590e
.set CYDEV_ANAIF_RT_BASE, 0x40005a00
.set CYDEV_ANAIF_RT_SIZE, 0x00000162
.set CYDEV_ANAIF_RT_SC0_BASE, 0x40005a00
.set CYDEV_ANAIF_RT_SC0_SIZE, 0x0000000d
.set CYDEV_ANAIF_RT_SC0_SW0, 0x40005a00
.set CYDEV_ANAIF_RT_SC0_SW2, 0x40005a02
.set CYDEV_ANAIF_RT_SC0_SW3, 0x40005a03
.set CYDEV_ANAIF_RT_SC0_SW4, 0x40005a04
.set CYDEV_ANAIF_RT_SC0_SW6, 0x40005a06
.set CYDEV_ANAIF_RT_SC0_SW7, 0x40005a07
.set CYDEV_ANAIF_RT_SC0_SW8, 0x40005a08
.set CYDEV_ANAIF_RT_SC0_SW10, 0x40005a0a
.set CYDEV_ANAIF_RT_SC0_CLK, 0x40005a0b
.set CYDEV_ANAIF_RT_SC0_BST, 0x40005a0c
.set CYDEV_ANAIF_RT_SC1_BASE, 0x40005a10
.set CYDEV_ANAIF_RT_SC1_SIZE, 0x0000000d
.set CYDEV_ANAIF_RT_SC1_SW0, 0x40005a10
.set CYDEV_ANAIF_RT_SC1_SW2, 0x40005a12
.set CYDEV_ANAIF_RT_SC1_SW3, 0x40005a13
.set CYDEV_ANAIF_RT_SC1_SW4, 0x40005a14
.set CYDEV_ANAIF_RT_SC1_SW6, 0x40005a16
.set CYDEV_ANAIF_RT_SC1_SW7, 0x40005a17
.set CYDEV_ANAIF_RT_SC1_SW8, 0x40005a18
.set CYDEV_ANAIF_RT_SC1_SW10, 0x40005a1a
.set CYDEV_ANAIF_RT_SC1_CLK, 0x40005a1b
.set CYDEV_ANAIF_RT_SC1_BST, 0x40005a1c
.set CYDEV_ANAIF_RT_SC2_BASE, 0x40005a20
.set CYDEV_ANAIF_RT_SC2_SIZE, 0x0000000d
.set CYDEV_ANAIF_RT_SC2_SW0, 0x40005a20
.set CYDEV_ANAIF_RT_SC2_SW2, 0x40005a22
.set CYDEV_ANAIF_RT_SC2_SW3, 0x40005a23
.set CYDEV_ANAIF_RT_SC2_SW4, 0x40005a24
.set CYDEV_ANAIF_RT_SC2_SW6, 0x40005a26
.set CYDEV_ANAIF_RT_SC2_SW7, 0x40005a27
.set CYDEV_ANAIF_RT_SC2_SW8, 0x40005a28
.set CYDEV_ANAIF_RT_SC2_SW10, 0x40005a2a
.set CYDEV_ANAIF_RT_SC2_CLK, 0x40005a2b
.set CYDEV_ANAIF_RT_SC2_BST, 0x40005a2c
.set CYDEV_ANAIF_RT_SC3_BASE, 0x40005a30
.set CYDEV_ANAIF_RT_SC3_SIZE, 0x0000000d
.set CYDEV_ANAIF_RT_SC3_SW0, 0x40005a30
.set CYDEV_ANAIF_RT_SC3_SW2, 0x40005a32
.set CYDEV_ANAIF_RT_SC3_SW3, 0x40005a33
.set CYDEV_ANAIF_RT_SC3_SW4, 0x40005a34
.set CYDEV_ANAIF_RT_SC3_SW6, 0x40005a36
.set CYDEV_ANAIF_RT_SC3_SW7, 0x40005a37
.set CYDEV_ANAIF_RT_SC3_SW8, 0x40005a38
.set CYDEV_ANAIF_RT_SC3_SW10, 0x40005a3a
.set CYDEV_ANAIF_RT_SC3_CLK, 0x40005a3b
.set CYDEV_ANAIF_RT_SC3_BST, 0x40005a3c
.set CYDEV_ANAIF_RT_DAC0_BASE, 0x40005a80
.set CYDEV_ANAIF_RT_DAC0_SIZE, 0x00000008
.set CYDEV_ANAIF_RT_DAC0_SW0, 0x40005a80
.set CYDEV_ANAIF_RT_DAC0_SW2, 0x40005a82
.set CYDEV_ANAIF_RT_DAC0_SW3, 0x40005a83
.set CYDEV_ANAIF_RT_DAC0_SW4, 0x40005a84
.set CYDEV_ANAIF_RT_DAC0_STROBE, 0x40005a87
.set CYDEV_ANAIF_RT_DAC1_BASE, 0x40005a88
.set CYDEV_ANAIF_RT_DAC1_SIZE, 0x00000008
.set CYDEV_ANAIF_RT_DAC1_SW0, 0x40005a88
.set CYDEV_ANAIF_RT_DAC1_SW2, 0x40005a8a
.set CYDEV_ANAIF_RT_DAC1_SW3, 0x40005a8b
.set CYDEV_ANAIF_RT_DAC1_SW4, 0x40005a8c
.set CYDEV_ANAIF_RT_DAC1_STROBE, 0x40005a8f
.set CYDEV_ANAIF_RT_DAC2_BASE, 0x40005a90
.set CYDEV_ANAIF_RT_DAC2_SIZE, 0x00000008
.set CYDEV_ANAIF_RT_DAC2_SW0, 0x40005a90
.set CYDEV_ANAIF_RT_DAC2_SW2, 0x40005a92
.set CYDEV_ANAIF_RT_DAC2_SW3, 0x40005a93
.set CYDEV_ANAIF_RT_DAC2_SW4, 0x40005a94
.set CYDEV_ANAIF_RT_DAC2_STROBE, 0x40005a97
.set CYDEV_ANAIF_RT_DAC3_BASE, 0x40005a98
.set CYDEV_ANAIF_RT_DAC3_SIZE, 0x00000008
.set CYDEV_ANAIF_RT_DAC3_SW0, 0x40005a98
.set CYDEV_ANAIF_RT_DAC3_SW2, 0x40005a9a
.set CYDEV_ANAIF_RT_DAC3_SW3, 0x40005a9b
.set CYDEV_ANAIF_RT_DAC3_SW4, 0x40005a9c
.set CYDEV_ANAIF_RT_DAC3_STROBE, 0x40005a9f
.set CYDEV_ANAIF_RT_CMP0_BASE, 0x40005ac0
.set CYDEV_ANAIF_RT_CMP0_SIZE, 0x00000008
.set CYDEV_ANAIF_RT_CMP0_SW0, 0x40005ac0
.set CYDEV_ANAIF_RT_CMP0_SW2, 0x40005ac2
.set CYDEV_ANAIF_RT_CMP0_SW3, 0x40005ac3
.set CYDEV_ANAIF_RT_CMP0_SW4, 0x40005ac4
.set CYDEV_ANAIF_RT_CMP0_SW6, 0x40005ac6
.set CYDEV_ANAIF_RT_CMP0_CLK, 0x40005ac7
.set CYDEV_ANAIF_RT_CMP1_BASE, 0x40005ac8
.set CYDEV_ANAIF_RT_CMP1_SIZE, 0x00000008
.set CYDEV_ANAIF_RT_CMP1_SW0, 0x40005ac8
.set CYDEV_ANAIF_RT_CMP1_SW2, 0x40005aca
.set CYDEV_ANAIF_RT_CMP1_SW3, 0x40005acb
.set CYDEV_ANAIF_RT_CMP1_SW4, 0x40005acc
.set CYDEV_ANAIF_RT_CMP1_SW6, 0x40005ace
.set CYDEV_ANAIF_RT_CMP1_CLK, 0x40005acf
.set CYDEV_ANAIF_RT_CMP2_BASE, 0x40005ad0
.set CYDEV_ANAIF_RT_CMP2_SIZE, 0x00000008
.set CYDEV_ANAIF_RT_CMP2_SW0, 0x40005ad0
.set CYDEV_ANAIF_RT_CMP2_SW2, 0x40005ad2
.set CYDEV_ANAIF_RT_CMP2_SW3, 0x40005ad3
.set CYDEV_ANAIF_RT_CMP2_SW4, 0x40005ad4
.set CYDEV_ANAIF_RT_CMP2_SW6, 0x40005ad6
.set CYDEV_ANAIF_RT_CMP2_CLK, 0x40005ad7
.set CYDEV_ANAIF_RT_CMP3_BASE, 0x40005ad8
.set CYDEV_ANAIF_RT_CMP3_SIZE, 0x00000008
.set CYDEV_ANAIF_RT_CMP3_SW0, 0x40005ad8
.set CYDEV_ANAIF_RT_CMP3_SW2, 0x40005ada
.set CYDEV_ANAIF_RT_CMP3_SW3, 0x40005adb
.set CYDEV_ANAIF_RT_CMP3_SW4, 0x40005adc
.set CYDEV_ANAIF_RT_CMP3_SW6, 0x40005ade
.set CYDEV_ANAIF_RT_CMP3_CLK, 0x40005adf
.set CYDEV_ANAIF_RT_DSM0_BASE, 0x40005b00
.set CYDEV_ANAIF_RT_DSM0_SIZE, 0x00000008
.set CYDEV_ANAIF_RT_DSM0_SW0, 0x40005b00
.set CYDEV_ANAIF_RT_DSM0_SW2, 0x40005b02
.set CYDEV_ANAIF_RT_DSM0_SW3, 0x40005b03
.set CYDEV_ANAIF_RT_DSM0_SW4, 0x40005b04
.set CYDEV_ANAIF_RT_DSM0_SW6, 0x40005b06
.set CYDEV_ANAIF_RT_DSM0_CLK, 0x40005b07
.set CYDEV_ANAIF_RT_SAR0_BASE, 0x40005b20
.set CYDEV_ANAIF_RT_SAR0_SIZE, 0x00000008
.set CYDEV_ANAIF_RT_SAR0_SW0, 0x40005b20
.set CYDEV_ANAIF_RT_SAR0_SW2, 0x40005b22
.set CYDEV_ANAIF_RT_SAR0_SW3, 0x40005b23
.set CYDEV_ANAIF_RT_SAR0_SW4, 0x40005b24
.set CYDEV_ANAIF_RT_SAR0_SW6, 0x40005b26
.set CYDEV_ANAIF_RT_SAR0_CLK, 0x40005b27
.set CYDEV_ANAIF_RT_SAR1_BASE, 0x40005b28
.set CYDEV_ANAIF_RT_SAR1_SIZE, 0x00000008
.set CYDEV_ANAIF_RT_SAR1_SW0, 0x40005b28
.set CYDEV_ANAIF_RT_SAR1_SW2, 0x40005b2a
.set CYDEV_ANAIF_RT_SAR1_SW3, 0x40005b2b
.set CYDEV_ANAIF_RT_SAR1_SW4, 0x40005b2c
.set CYDEV_ANAIF_RT_SAR1_SW6, 0x40005b2e
.set CYDEV_ANAIF_RT_SAR1_CLK, 0x40005b2f
.set CYDEV_ANAIF_RT_OPAMP0_BASE, 0x40005b40
.set CYDEV_ANAIF_RT_OPAMP0_SIZE, 0x00000002
.set CYDEV_ANAIF_RT_OPAMP0_MX, 0x40005b40
.set CYDEV_ANAIF_RT_OPAMP0_SW, 0x40005b41
.set CYDEV_ANAIF_RT_OPAMP1_BASE, 0x40005b42
.set CYDEV_ANAIF_RT_OPAMP1_SIZE, 0x00000002
.set CYDEV_ANAIF_RT_OPAMP1_MX, 0x40005b42
.set CYDEV_ANAIF_RT_OPAMP1_SW, 0x40005b43
.set CYDEV_ANAIF_RT_OPAMP2_BASE, 0x40005b44
.set CYDEV_ANAIF_RT_OPAMP2_SIZE, 0x00000002
.set CYDEV_ANAIF_RT_OPAMP2_MX, 0x40005b44
.set CYDEV_ANAIF_RT_OPAMP2_SW, 0x40005b45
.set CYDEV_ANAIF_RT_OPAMP3_BASE, 0x40005b46
.set CYDEV_ANAIF_RT_OPAMP3_SIZE, 0x00000002
.set CYDEV_ANAIF_RT_OPAMP3_MX, 0x40005b46
.set CYDEV_ANAIF_RT_OPAMP3_SW, 0x40005b47
.set CYDEV_ANAIF_RT_LCDDAC_BASE, 0x40005b50
.set CYDEV_ANAIF_RT_LCDDAC_SIZE, 0x00000005
.set CYDEV_ANAIF_RT_LCDDAC_SW0, 0x40005b50
.set CYDEV_ANAIF_RT_LCDDAC_SW1, 0x40005b51
.set CYDEV_ANAIF_RT_LCDDAC_SW2, 0x40005b52
.set CYDEV_ANAIF_RT_LCDDAC_SW3, 0x40005b53
.set CYDEV_ANAIF_RT_LCDDAC_SW4, 0x40005b54
.set CYDEV_ANAIF_RT_SC_BASE, 0x40005b56
.set CYDEV_ANAIF_RT_SC_SIZE, 0x00000001
.set CYDEV_ANAIF_RT_SC_MISC, 0x40005b56
.set CYDEV_ANAIF_RT_BUS_BASE, 0x40005b58
.set CYDEV_ANAIF_RT_BUS_SIZE, 0x00000004
.set CYDEV_ANAIF_RT_BUS_SW0, 0x40005b58
.set CYDEV_ANAIF_RT_BUS_SW2, 0x40005b5a
.set CYDEV_ANAIF_RT_BUS_SW3, 0x40005b5b
.set CYDEV_ANAIF_RT_DFT_BASE, 0x40005b5c
.set CYDEV_ANAIF_RT_DFT_SIZE, 0x00000006
.set CYDEV_ANAIF_RT_DFT_CR0, 0x40005b5c
.set CYDEV_ANAIF_RT_DFT_CR1, 0x40005b5d
.set CYDEV_ANAIF_RT_DFT_CR2, 0x40005b5e
.set CYDEV_ANAIF_RT_DFT_CR3, 0x40005b5f
.set CYDEV_ANAIF_RT_DFT_CR4, 0x40005b60
.set CYDEV_ANAIF_RT_DFT_CR5, 0x40005b61
.set CYDEV_ANAIF_WRK_BASE, 0x40005b80
.set CYDEV_ANAIF_WRK_SIZE, 0x00000029
.set CYDEV_ANAIF_WRK_DAC0_BASE, 0x40005b80
.set CYDEV_ANAIF_WRK_DAC0_SIZE, 0x00000001
.set CYDEV_ANAIF_WRK_DAC0_D, 0x40005b80
.set CYDEV_ANAIF_WRK_DAC1_BASE, 0x40005b81
.set CYDEV_ANAIF_WRK_DAC1_SIZE, 0x00000001
.set CYDEV_ANAIF_WRK_DAC1_D, 0x40005b81
.set CYDEV_ANAIF_WRK_DAC2_BASE, 0x40005b82
.set CYDEV_ANAIF_WRK_DAC2_SIZE, 0x00000001
.set CYDEV_ANAIF_WRK_DAC2_D, 0x40005b82
.set CYDEV_ANAIF_WRK_DAC3_BASE, 0x40005b83
.set CYDEV_ANAIF_WRK_DAC3_SIZE, 0x00000001
.set CYDEV_ANAIF_WRK_DAC3_D, 0x40005b83
.set CYDEV_ANAIF_WRK_DSM0_BASE, 0x40005b88
.set CYDEV_ANAIF_WRK_DSM0_SIZE, 0x00000002
.set CYDEV_ANAIF_WRK_DSM0_OUT0, 0x40005b88
.set CYDEV_ANAIF_WRK_DSM0_OUT1, 0x40005b89
.set CYDEV_ANAIF_WRK_LUT_BASE, 0x40005b90
.set CYDEV_ANAIF_WRK_LUT_SIZE, 0x00000005
.set CYDEV_ANAIF_WRK_LUT_SR, 0x40005b90
.set CYDEV_ANAIF_WRK_LUT_WRK1, 0x40005b91
.set CYDEV_ANAIF_WRK_LUT_MSK, 0x40005b92
.set CYDEV_ANAIF_WRK_LUT_CLK, 0x40005b93
.set CYDEV_ANAIF_WRK_LUT_CPTR, 0x40005b94
.set CYDEV_ANAIF_WRK_CMP_BASE, 0x40005b96
.set CYDEV_ANAIF_WRK_CMP_SIZE, 0x00000002
.set CYDEV_ANAIF_WRK_CMP_WRK, 0x40005b96
.set CYDEV_ANAIF_WRK_CMP_TST, 0x40005b97
.set CYDEV_ANAIF_WRK_SC_BASE, 0x40005b98
.set CYDEV_ANAIF_WRK_SC_SIZE, 0x00000005
.set CYDEV_ANAIF_WRK_SC_SR, 0x40005b98
.set CYDEV_ANAIF_WRK_SC_WRK1, 0x40005b99
.set CYDEV_ANAIF_WRK_SC_MSK, 0x40005b9a
.set CYDEV_ANAIF_WRK_SC_CMPINV, 0x40005b9b
.set CYDEV_ANAIF_WRK_SC_CPTR, 0x40005b9c
.set CYDEV_ANAIF_WRK_SAR0_BASE, 0x40005ba0
.set CYDEV_ANAIF_WRK_SAR0_SIZE, 0x00000002
.set CYDEV_ANAIF_WRK_SAR0_WRK0, 0x40005ba0
.set CYDEV_ANAIF_WRK_SAR0_WRK1, 0x40005ba1
.set CYDEV_ANAIF_WRK_SAR1_BASE, 0x40005ba2
.set CYDEV_ANAIF_WRK_SAR1_SIZE, 0x00000002
.set CYDEV_ANAIF_WRK_SAR1_WRK0, 0x40005ba2
.set CYDEV_ANAIF_WRK_SAR1_WRK1, 0x40005ba3
.set CYDEV_ANAIF_WRK_SARS_BASE, 0x40005ba8
.set CYDEV_ANAIF_WRK_SARS_SIZE, 0x00000001
.set CYDEV_ANAIF_WRK_SARS_SOF, 0x40005ba8
.set CYDEV_USB_BASE, 0x40006000
.set CYDEV_USB_SIZE, 0x00000300
.set CYDEV_USB_EP0_DR0, 0x40006000
.set CYDEV_USB_EP0_DR1, 0x40006001
.set CYDEV_USB_EP0_DR2, 0x40006002
.set CYDEV_USB_EP0_DR3, 0x40006003
.set CYDEV_USB_EP0_DR4, 0x40006004
.set CYDEV_USB_EP0_DR5, 0x40006005
.set CYDEV_USB_EP0_DR6, 0x40006006
.set CYDEV_USB_EP0_DR7, 0x40006007
.set CYDEV_USB_CR0, 0x40006008
.set CYDEV_USB_CR1, 0x40006009
.set CYDEV_USB_SIE_EP_INT_EN, 0x4000600a
.set CYDEV_USB_SIE_EP_INT_SR, 0x4000600b
.set CYDEV_USB_SIE_EP1_BASE, 0x4000600c
.set CYDEV_USB_SIE_EP1_SIZE, 0x00000003
.set CYDEV_USB_SIE_EP1_CNT0, 0x4000600c
.set CYDEV_USB_SIE_EP1_CNT1, 0x4000600d
.set CYDEV_USB_SIE_EP1_CR0, 0x4000600e
.set CYDEV_USB_USBIO_CR0, 0x40006010
.set CYDEV_USB_USBIO_CR1, 0x40006012
.set CYDEV_USB_DYN_RECONFIG, 0x40006014
.set CYDEV_USB_SOF0, 0x40006018
.set CYDEV_USB_SOF1, 0x40006019
.set CYDEV_USB_SIE_EP2_BASE, 0x4000601c
.set CYDEV_USB_SIE_EP2_SIZE, 0x00000003
.set CYDEV_USB_SIE_EP2_CNT0, 0x4000601c
.set CYDEV_USB_SIE_EP2_CNT1, 0x4000601d
.set CYDEV_USB_SIE_EP2_CR0, 0x4000601e
.set CYDEV_USB_EP0_CR, 0x40006028
.set CYDEV_USB_EP0_CNT, 0x40006029
.set CYDEV_USB_SIE_EP3_BASE, 0x4000602c
.set CYDEV_USB_SIE_EP3_SIZE, 0x00000003
.set CYDEV_USB_SIE_EP3_CNT0, 0x4000602c
.set CYDEV_USB_SIE_EP3_CNT1, 0x4000602d
.set CYDEV_USB_SIE_EP3_CR0, 0x4000602e
.set CYDEV_USB_SIE_EP4_BASE, 0x4000603c
.set CYDEV_USB_SIE_EP4_SIZE, 0x00000003
.set CYDEV_USB_SIE_EP4_CNT0, 0x4000603c
.set CYDEV_USB_SIE_EP4_CNT1, 0x4000603d
.set CYDEV_USB_SIE_EP4_CR0, 0x4000603e
.set CYDEV_USB_SIE_EP5_BASE, 0x4000604c
.set CYDEV_USB_SIE_EP5_SIZE, 0x00000003
.set CYDEV_USB_SIE_EP5_CNT0, 0x4000604c
.set CYDEV_USB_SIE_EP5_CNT1, 0x4000604d
.set CYDEV_USB_SIE_EP5_CR0, 0x4000604e
.set CYDEV_USB_SIE_EP6_BASE, 0x4000605c
.set CYDEV_USB_SIE_EP6_SIZE, 0x00000003
.set CYDEV_USB_SIE_EP6_CNT0, 0x4000605c
.set CYDEV_USB_SIE_EP6_CNT1, 0x4000605d
.set CYDEV_USB_SIE_EP6_CR0, 0x4000605e
.set CYDEV_USB_SIE_EP7_BASE, 0x4000606c
.set CYDEV_USB_SIE_EP7_SIZE, 0x00000003
.set CYDEV_USB_SIE_EP7_CNT0, 0x4000606c
.set CYDEV_USB_SIE_EP7_CNT1, 0x4000606d
.set CYDEV_USB_SIE_EP7_CR0, 0x4000606e
.set CYDEV_USB_SIE_EP8_BASE, 0x4000607c
.set CYDEV_USB_SIE_EP8_SIZE, 0x00000003
.set CYDEV_USB_SIE_EP8_CNT0, 0x4000607c
.set CYDEV_USB_SIE_EP8_CNT1, 0x4000607d
.set CYDEV_USB_SIE_EP8_CR0, 0x4000607e
.set CYDEV_USB_ARB_EP1_BASE, 0x40006080
.set CYDEV_USB_ARB_EP1_SIZE, 0x00000003
.set CYDEV_USB_ARB_EP1_CFG, 0x40006080
.set CYDEV_USB_ARB_EP1_INT_EN, 0x40006081
.set CYDEV_USB_ARB_EP1_SR, 0x40006082
.set CYDEV_USB_ARB_RW1_BASE, 0x40006084
.set CYDEV_USB_ARB_RW1_SIZE, 0x00000005
.set CYDEV_USB_ARB_RW1_WA, 0x40006084
.set CYDEV_USB_ARB_RW1_WA_MSB, 0x40006085
.set CYDEV_USB_ARB_RW1_RA, 0x40006086
.set CYDEV_USB_ARB_RW1_RA_MSB, 0x40006087
.set CYDEV_USB_ARB_RW1_DR, 0x40006088
.set CYDEV_USB_BUF_SIZE, 0x4000608c
.set CYDEV_USB_EP_ACTIVE, 0x4000608e
.set CYDEV_USB_EP_TYPE, 0x4000608f
.set CYDEV_USB_ARB_EP2_BASE, 0x40006090
.set CYDEV_USB_ARB_EP2_SIZE, 0x00000003
.set CYDEV_USB_ARB_EP2_CFG, 0x40006090
.set CYDEV_USB_ARB_EP2_INT_EN, 0x40006091
.set CYDEV_USB_ARB_EP2_SR, 0x40006092
.set CYDEV_USB_ARB_RW2_BASE, 0x40006094
.set CYDEV_USB_ARB_RW2_SIZE, 0x00000005
.set CYDEV_USB_ARB_RW2_WA, 0x40006094
.set CYDEV_USB_ARB_RW2_WA_MSB, 0x40006095
.set CYDEV_USB_ARB_RW2_RA, 0x40006096
.set CYDEV_USB_ARB_RW2_RA_MSB, 0x40006097
.set CYDEV_USB_ARB_RW2_DR, 0x40006098
.set CYDEV_USB_ARB_CFG, 0x4000609c
.set CYDEV_USB_USB_CLK_EN, 0x4000609d
.set CYDEV_USB_ARB_INT_EN, 0x4000609e
.set CYDEV_USB_ARB_INT_SR, 0x4000609f
.set CYDEV_USB_ARB_EP3_BASE, 0x400060a0
.set CYDEV_USB_ARB_EP3_SIZE, 0x00000003
.set CYDEV_USB_ARB_EP3_CFG, 0x400060a0
.set CYDEV_USB_ARB_EP3_INT_EN, 0x400060a1
.set CYDEV_USB_ARB_EP3_SR, 0x400060a2
.set CYDEV_USB_ARB_RW3_BASE, 0x400060a4
.set CYDEV_USB_ARB_RW3_SIZE, 0x00000005
.set CYDEV_USB_ARB_RW3_WA, 0x400060a4
.set CYDEV_USB_ARB_RW3_WA_MSB, 0x400060a5
.set CYDEV_USB_ARB_RW3_RA, 0x400060a6
.set CYDEV_USB_ARB_RW3_RA_MSB, 0x400060a7
.set CYDEV_USB_ARB_RW3_DR, 0x400060a8
.set CYDEV_USB_CWA, 0x400060ac
.set CYDEV_USB_CWA_MSB, 0x400060ad
.set CYDEV_USB_ARB_EP4_BASE, 0x400060b0
.set CYDEV_USB_ARB_EP4_SIZE, 0x00000003
.set CYDEV_USB_ARB_EP4_CFG, 0x400060b0
.set CYDEV_USB_ARB_EP4_INT_EN, 0x400060b1
.set CYDEV_USB_ARB_EP4_SR, 0x400060b2
.set CYDEV_USB_ARB_RW4_BASE, 0x400060b4
.set CYDEV_USB_ARB_RW4_SIZE, 0x00000005
.set CYDEV_USB_ARB_RW4_WA, 0x400060b4
.set CYDEV_USB_ARB_RW4_WA_MSB, 0x400060b5
.set CYDEV_USB_ARB_RW4_RA, 0x400060b6
.set CYDEV_USB_ARB_RW4_RA_MSB, 0x400060b7
.set CYDEV_USB_ARB_RW4_DR, 0x400060b8
.set CYDEV_USB_DMA_THRES, 0x400060bc
.set CYDEV_USB_DMA_THRES_MSB, 0x400060bd
.set CYDEV_USB_ARB_EP5_BASE, 0x400060c0
.set CYDEV_USB_ARB_EP5_SIZE, 0x00000003
.set CYDEV_USB_ARB_EP5_CFG, 0x400060c0
.set CYDEV_USB_ARB_EP5_INT_EN, 0x400060c1
.set CYDEV_USB_ARB_EP5_SR, 0x400060c2
.set CYDEV_USB_ARB_RW5_BASE, 0x400060c4
.set CYDEV_USB_ARB_RW5_SIZE, 0x00000005
.set CYDEV_USB_ARB_RW5_WA, 0x400060c4
.set CYDEV_USB_ARB_RW5_WA_MSB, 0x400060c5
.set CYDEV_USB_ARB_RW5_RA, 0x400060c6
.set CYDEV_USB_ARB_RW5_RA_MSB, 0x400060c7
.set CYDEV_USB_ARB_RW5_DR, 0x400060c8
.set CYDEV_USB_BUS_RST_CNT, 0x400060cc
.set CYDEV_USB_ARB_EP6_BASE, 0x400060d0
.set CYDEV_USB_ARB_EP6_SIZE, 0x00000003
.set CYDEV_USB_ARB_EP6_CFG, 0x400060d0
.set CYDEV_USB_ARB_EP6_INT_EN, 0x400060d1
.set CYDEV_USB_ARB_EP6_SR, 0x400060d2
.set CYDEV_USB_ARB_RW6_BASE, 0x400060d4
.set CYDEV_USB_ARB_RW6_SIZE, 0x00000005
.set CYDEV_USB_ARB_RW6_WA, 0x400060d4
.set CYDEV_USB_ARB_RW6_WA_MSB, 0x400060d5
.set CYDEV_USB_ARB_RW6_RA, 0x400060d6
.set CYDEV_USB_ARB_RW6_RA_MSB, 0x400060d7
.set CYDEV_USB_ARB_RW6_DR, 0x400060d8
.set CYDEV_USB_ARB_EP7_BASE, 0x400060e0
.set CYDEV_USB_ARB_EP7_SIZE, 0x00000003
.set CYDEV_USB_ARB_EP7_CFG, 0x400060e0
.set CYDEV_USB_ARB_EP7_INT_EN, 0x400060e1
.set CYDEV_USB_ARB_EP7_SR, 0x400060e2
.set CYDEV_USB_ARB_RW7_BASE, 0x400060e4
.set CYDEV_USB_ARB_RW7_SIZE, 0x00000005
.set CYDEV_USB_ARB_RW7_WA, 0x400060e4
.set CYDEV_USB_ARB_RW7_WA_MSB, 0x400060e5
.set CYDEV_USB_ARB_RW7_RA, 0x400060e6
.set CYDEV_USB_ARB_RW7_RA_MSB, 0x400060e7
.set CYDEV_USB_ARB_RW7_DR, 0x400060e8
.set CYDEV_USB_ARB_EP8_BASE, 0x400060f0
.set CYDEV_USB_ARB_EP8_SIZE, 0x00000003
.set CYDEV_USB_ARB_EP8_CFG, 0x400060f0
.set CYDEV_USB_ARB_EP8_INT_EN, 0x400060f1
.set CYDEV_USB_ARB_EP8_SR, 0x400060f2
.set CYDEV_USB_ARB_RW8_BASE, 0x400060f4
.set CYDEV_USB_ARB_RW8_SIZE, 0x00000005
.set CYDEV_USB_ARB_RW8_WA, 0x400060f4
.set CYDEV_USB_ARB_RW8_WA_MSB, 0x400060f5
.set CYDEV_USB_ARB_RW8_RA, 0x400060f6
.set CYDEV_USB_ARB_RW8_RA_MSB, 0x400060f7
.set CYDEV_USB_ARB_RW8_DR, 0x400060f8
.set CYDEV_USB_MEM_BASE, 0x40006100
.set CYDEV_USB_MEM_SIZE, 0x00000200
.set CYDEV_USB_MEM_DATA_MBASE, 0x40006100
.set CYDEV_USB_MEM_DATA_MSIZE, 0x00000200
.set CYDEV_UWRK_BASE, 0x40006400
.set CYDEV_UWRK_SIZE, 0x00000b60
.set CYDEV_UWRK_UWRK8_BASE, 0x40006400
.set CYDEV_UWRK_UWRK8_SIZE, 0x000003b0
.set CYDEV_UWRK_UWRK8_B0_BASE, 0x40006400
.set CYDEV_UWRK_UWRK8_B0_SIZE, 0x000000b0
.set CYDEV_UWRK_UWRK8_B0_UDB00_A0, 0x40006400
.set CYDEV_UWRK_UWRK8_B0_UDB01_A0, 0x40006401
.set CYDEV_UWRK_UWRK8_B0_UDB02_A0, 0x40006402
.set CYDEV_UWRK_UWRK8_B0_UDB03_A0, 0x40006403
.set CYDEV_UWRK_UWRK8_B0_UDB04_A0, 0x40006404
.set CYDEV_UWRK_UWRK8_B0_UDB05_A0, 0x40006405
.set CYDEV_UWRK_UWRK8_B0_UDB06_A0, 0x40006406
.set CYDEV_UWRK_UWRK8_B0_UDB07_A0, 0x40006407
.set CYDEV_UWRK_UWRK8_B0_UDB08_A0, 0x40006408
.set CYDEV_UWRK_UWRK8_B0_UDB09_A0, 0x40006409
.set CYDEV_UWRK_UWRK8_B0_UDB10_A0, 0x4000640a
.set CYDEV_UWRK_UWRK8_B0_UDB11_A0, 0x4000640b
.set CYDEV_UWRK_UWRK8_B0_UDB12_A0, 0x4000640c
.set CYDEV_UWRK_UWRK8_B0_UDB13_A0, 0x4000640d
.set CYDEV_UWRK_UWRK8_B0_UDB14_A0, 0x4000640e
.set CYDEV_UWRK_UWRK8_B0_UDB15_A0, 0x4000640f
.set CYDEV_UWRK_UWRK8_B0_UDB00_A1, 0x40006410
.set CYDEV_UWRK_UWRK8_B0_UDB01_A1, 0x40006411
.set CYDEV_UWRK_UWRK8_B0_UDB02_A1, 0x40006412
.set CYDEV_UWRK_UWRK8_B0_UDB03_A1, 0x40006413
.set CYDEV_UWRK_UWRK8_B0_UDB04_A1, 0x40006414
.set CYDEV_UWRK_UWRK8_B0_UDB05_A1, 0x40006415
.set CYDEV_UWRK_UWRK8_B0_UDB06_A1, 0x40006416
.set CYDEV_UWRK_UWRK8_B0_UDB07_A1, 0x40006417
.set CYDEV_UWRK_UWRK8_B0_UDB08_A1, 0x40006418
.set CYDEV_UWRK_UWRK8_B0_UDB09_A1, 0x40006419
.set CYDEV_UWRK_UWRK8_B0_UDB10_A1, 0x4000641a
.set CYDEV_UWRK_UWRK8_B0_UDB11_A1, 0x4000641b
.set CYDEV_UWRK_UWRK8_B0_UDB12_A1, 0x4000641c
.set CYDEV_UWRK_UWRK8_B0_UDB13_A1, 0x4000641d
.set CYDEV_UWRK_UWRK8_B0_UDB14_A1, 0x4000641e
.set CYDEV_UWRK_UWRK8_B0_UDB15_A1, 0x4000641f
.set CYDEV_UWRK_UWRK8_B0_UDB00_D0, 0x40006420
.set CYDEV_UWRK_UWRK8_B0_UDB01_D0, 0x40006421
.set CYDEV_UWRK_UWRK8_B0_UDB02_D0, 0x40006422
.set CYDEV_UWRK_UWRK8_B0_UDB03_D0, 0x40006423
.set CYDEV_UWRK_UWRK8_B0_UDB04_D0, 0x40006424
.set CYDEV_UWRK_UWRK8_B0_UDB05_D0, 0x40006425
.set CYDEV_UWRK_UWRK8_B0_UDB06_D0, 0x40006426
.set CYDEV_UWRK_UWRK8_B0_UDB07_D0, 0x40006427
.set CYDEV_UWRK_UWRK8_B0_UDB08_D0, 0x40006428
.set CYDEV_UWRK_UWRK8_B0_UDB09_D0, 0x40006429
.set CYDEV_UWRK_UWRK8_B0_UDB10_D0, 0x4000642a
.set CYDEV_UWRK_UWRK8_B0_UDB11_D0, 0x4000642b
.set CYDEV_UWRK_UWRK8_B0_UDB12_D0, 0x4000642c
.set CYDEV_UWRK_UWRK8_B0_UDB13_D0, 0x4000642d
.set CYDEV_UWRK_UWRK8_B0_UDB14_D0, 0x4000642e
.set CYDEV_UWRK_UWRK8_B0_UDB15_D0, 0x4000642f
.set CYDEV_UWRK_UWRK8_B0_UDB00_D1, 0x40006430
.set CYDEV_UWRK_UWRK8_B0_UDB01_D1, 0x40006431
.set CYDEV_UWRK_UWRK8_B0_UDB02_D1, 0x40006432
.set CYDEV_UWRK_UWRK8_B0_UDB03_D1, 0x40006433
.set CYDEV_UWRK_UWRK8_B0_UDB04_D1, 0x40006434
.set CYDEV_UWRK_UWRK8_B0_UDB05_D1, 0x40006435
.set CYDEV_UWRK_UWRK8_B0_UDB06_D1, 0x40006436
.set CYDEV_UWRK_UWRK8_B0_UDB07_D1, 0x40006437
.set CYDEV_UWRK_UWRK8_B0_UDB08_D1, 0x40006438
.set CYDEV_UWRK_UWRK8_B0_UDB09_D1, 0x40006439
.set CYDEV_UWRK_UWRK8_B0_UDB10_D1, 0x4000643a
.set CYDEV_UWRK_UWRK8_B0_UDB11_D1, 0x4000643b
.set CYDEV_UWRK_UWRK8_B0_UDB12_D1, 0x4000643c
.set CYDEV_UWRK_UWRK8_B0_UDB13_D1, 0x4000643d
.set CYDEV_UWRK_UWRK8_B0_UDB14_D1, 0x4000643e
.set CYDEV_UWRK_UWRK8_B0_UDB15_D1, 0x4000643f
.set CYDEV_UWRK_UWRK8_B0_UDB00_F0, 0x40006440
.set CYDEV_UWRK_UWRK8_B0_UDB01_F0, 0x40006441
.set CYDEV_UWRK_UWRK8_B0_UDB02_F0, 0x40006442
.set CYDEV_UWRK_UWRK8_B0_UDB03_F0, 0x40006443
.set CYDEV_UWRK_UWRK8_B0_UDB04_F0, 0x40006444
.set CYDEV_UWRK_UWRK8_B0_UDB05_F0, 0x40006445
.set CYDEV_UWRK_UWRK8_B0_UDB06_F0, 0x40006446
.set CYDEV_UWRK_UWRK8_B0_UDB07_F0, 0x40006447
.set CYDEV_UWRK_UWRK8_B0_UDB08_F0, 0x40006448
.set CYDEV_UWRK_UWRK8_B0_UDB09_F0, 0x40006449
.set CYDEV_UWRK_UWRK8_B0_UDB10_F0, 0x4000644a
.set CYDEV_UWRK_UWRK8_B0_UDB11_F0, 0x4000644b
.set CYDEV_UWRK_UWRK8_B0_UDB12_F0, 0x4000644c
.set CYDEV_UWRK_UWRK8_B0_UDB13_F0, 0x4000644d
.set CYDEV_UWRK_UWRK8_B0_UDB14_F0, 0x4000644e
.set CYDEV_UWRK_UWRK8_B0_UDB15_F0, 0x4000644f
.set CYDEV_UWRK_UWRK8_B0_UDB00_F1, 0x40006450
.set CYDEV_UWRK_UWRK8_B0_UDB01_F1, 0x40006451
.set CYDEV_UWRK_UWRK8_B0_UDB02_F1, 0x40006452
.set CYDEV_UWRK_UWRK8_B0_UDB03_F1, 0x40006453
.set CYDEV_UWRK_UWRK8_B0_UDB04_F1, 0x40006454
.set CYDEV_UWRK_UWRK8_B0_UDB05_F1, 0x40006455
.set CYDEV_UWRK_UWRK8_B0_UDB06_F1, 0x40006456
.set CYDEV_UWRK_UWRK8_B0_UDB07_F1, 0x40006457
.set CYDEV_UWRK_UWRK8_B0_UDB08_F1, 0x40006458
.set CYDEV_UWRK_UWRK8_B0_UDB09_F1, 0x40006459
.set CYDEV_UWRK_UWRK8_B0_UDB10_F1, 0x4000645a
.set CYDEV_UWRK_UWRK8_B0_UDB11_F1, 0x4000645b
.set CYDEV_UWRK_UWRK8_B0_UDB12_F1, 0x4000645c
.set CYDEV_UWRK_UWRK8_B0_UDB13_F1, 0x4000645d
.set CYDEV_UWRK_UWRK8_B0_UDB14_F1, 0x4000645e
.set CYDEV_UWRK_UWRK8_B0_UDB15_F1, 0x4000645f
.set CYDEV_UWRK_UWRK8_B0_UDB00_ST, 0x40006460
.set CYDEV_UWRK_UWRK8_B0_UDB01_ST, 0x40006461
.set CYDEV_UWRK_UWRK8_B0_UDB02_ST, 0x40006462
.set CYDEV_UWRK_UWRK8_B0_UDB03_ST, 0x40006463
.set CYDEV_UWRK_UWRK8_B0_UDB04_ST, 0x40006464
.set CYDEV_UWRK_UWRK8_B0_UDB05_ST, 0x40006465
.set CYDEV_UWRK_UWRK8_B0_UDB06_ST, 0x40006466
.set CYDEV_UWRK_UWRK8_B0_UDB07_ST, 0x40006467
.set CYDEV_UWRK_UWRK8_B0_UDB08_ST, 0x40006468
.set CYDEV_UWRK_UWRK8_B0_UDB09_ST, 0x40006469
.set CYDEV_UWRK_UWRK8_B0_UDB10_ST, 0x4000646a
.set CYDEV_UWRK_UWRK8_B0_UDB11_ST, 0x4000646b
.set CYDEV_UWRK_UWRK8_B0_UDB12_ST, 0x4000646c
.set CYDEV_UWRK_UWRK8_B0_UDB13_ST, 0x4000646d
.set CYDEV_UWRK_UWRK8_B0_UDB14_ST, 0x4000646e
.set CYDEV_UWRK_UWRK8_B0_UDB15_ST, 0x4000646f
.set CYDEV_UWRK_UWRK8_B0_UDB00_CTL, 0x40006470
.set CYDEV_UWRK_UWRK8_B0_UDB01_CTL, 0x40006471
.set CYDEV_UWRK_UWRK8_B0_UDB02_CTL, 0x40006472
.set CYDEV_UWRK_UWRK8_B0_UDB03_CTL, 0x40006473
.set CYDEV_UWRK_UWRK8_B0_UDB04_CTL, 0x40006474
.set CYDEV_UWRK_UWRK8_B0_UDB05_CTL, 0x40006475
.set CYDEV_UWRK_UWRK8_B0_UDB06_CTL, 0x40006476
.set CYDEV_UWRK_UWRK8_B0_UDB07_CTL, 0x40006477
.set CYDEV_UWRK_UWRK8_B0_UDB08_CTL, 0x40006478
.set CYDEV_UWRK_UWRK8_B0_UDB09_CTL, 0x40006479
.set CYDEV_UWRK_UWRK8_B0_UDB10_CTL, 0x4000647a
.set CYDEV_UWRK_UWRK8_B0_UDB11_CTL, 0x4000647b
.set CYDEV_UWRK_UWRK8_B0_UDB12_CTL, 0x4000647c
.set CYDEV_UWRK_UWRK8_B0_UDB13_CTL, 0x4000647d
.set CYDEV_UWRK_UWRK8_B0_UDB14_CTL, 0x4000647e
.set CYDEV_UWRK_UWRK8_B0_UDB15_CTL, 0x4000647f
.set CYDEV_UWRK_UWRK8_B0_UDB00_MSK, 0x40006480
.set CYDEV_UWRK_UWRK8_B0_UDB01_MSK, 0x40006481
.set CYDEV_UWRK_UWRK8_B0_UDB02_MSK, 0x40006482
.set CYDEV_UWRK_UWRK8_B0_UDB03_MSK, 0x40006483
.set CYDEV_UWRK_UWRK8_B0_UDB04_MSK, 0x40006484
.set CYDEV_UWRK_UWRK8_B0_UDB05_MSK, 0x40006485
.set CYDEV_UWRK_UWRK8_B0_UDB06_MSK, 0x40006486
.set CYDEV_UWRK_UWRK8_B0_UDB07_MSK, 0x40006487
.set CYDEV_UWRK_UWRK8_B0_UDB08_MSK, 0x40006488
.set CYDEV_UWRK_UWRK8_B0_UDB09_MSK, 0x40006489
.set CYDEV_UWRK_UWRK8_B0_UDB10_MSK, 0x4000648a
.set CYDEV_UWRK_UWRK8_B0_UDB11_MSK, 0x4000648b
.set CYDEV_UWRK_UWRK8_B0_UDB12_MSK, 0x4000648c
.set CYDEV_UWRK_UWRK8_B0_UDB13_MSK, 0x4000648d
.set CYDEV_UWRK_UWRK8_B0_UDB14_MSK, 0x4000648e
.set CYDEV_UWRK_UWRK8_B0_UDB15_MSK, 0x4000648f
.set CYDEV_UWRK_UWRK8_B0_UDB00_ACTL, 0x40006490
.set CYDEV_UWRK_UWRK8_B0_UDB01_ACTL, 0x40006491
.set CYDEV_UWRK_UWRK8_B0_UDB02_ACTL, 0x40006492
.set CYDEV_UWRK_UWRK8_B0_UDB03_ACTL, 0x40006493
.set CYDEV_UWRK_UWRK8_B0_UDB04_ACTL, 0x40006494
.set CYDEV_UWRK_UWRK8_B0_UDB05_ACTL, 0x40006495
.set CYDEV_UWRK_UWRK8_B0_UDB06_ACTL, 0x40006496
.set CYDEV_UWRK_UWRK8_B0_UDB07_ACTL, 0x40006497
.set CYDEV_UWRK_UWRK8_B0_UDB08_ACTL, 0x40006498
.set CYDEV_UWRK_UWRK8_B0_UDB09_ACTL, 0x40006499
.set CYDEV_UWRK_UWRK8_B0_UDB10_ACTL, 0x4000649a
.set CYDEV_UWRK_UWRK8_B0_UDB11_ACTL, 0x4000649b
.set CYDEV_UWRK_UWRK8_B0_UDB12_ACTL, 0x4000649c
.set CYDEV_UWRK_UWRK8_B0_UDB13_ACTL, 0x4000649d
.set CYDEV_UWRK_UWRK8_B0_UDB14_ACTL, 0x4000649e
.set CYDEV_UWRK_UWRK8_B0_UDB15_ACTL, 0x4000649f
.set CYDEV_UWRK_UWRK8_B0_UDB00_MC, 0x400064a0
.set CYDEV_UWRK_UWRK8_B0_UDB01_MC, 0x400064a1
.set CYDEV_UWRK_UWRK8_B0_UDB02_MC, 0x400064a2
.set CYDEV_UWRK_UWRK8_B0_UDB03_MC, 0x400064a3
.set CYDEV_UWRK_UWRK8_B0_UDB04_MC, 0x400064a4
.set CYDEV_UWRK_UWRK8_B0_UDB05_MC, 0x400064a5
.set CYDEV_UWRK_UWRK8_B0_UDB06_MC, 0x400064a6
.set CYDEV_UWRK_UWRK8_B0_UDB07_MC, 0x400064a7
.set CYDEV_UWRK_UWRK8_B0_UDB08_MC, 0x400064a8
.set CYDEV_UWRK_UWRK8_B0_UDB09_MC, 0x400064a9
.set CYDEV_UWRK_UWRK8_B0_UDB10_MC, 0x400064aa
.set CYDEV_UWRK_UWRK8_B0_UDB11_MC, 0x400064ab
.set CYDEV_UWRK_UWRK8_B0_UDB12_MC, 0x400064ac
.set CYDEV_UWRK_UWRK8_B0_UDB13_MC, 0x400064ad
.set CYDEV_UWRK_UWRK8_B0_UDB14_MC, 0x400064ae
.set CYDEV_UWRK_UWRK8_B0_UDB15_MC, 0x400064af
.set CYDEV_UWRK_UWRK8_B1_BASE, 0x40006500
.set CYDEV_UWRK_UWRK8_B1_SIZE, 0x000000b0
.set CYDEV_UWRK_UWRK8_B1_UDB04_A0, 0x40006504
.set CYDEV_UWRK_UWRK8_B1_UDB05_A0, 0x40006505
.set CYDEV_UWRK_UWRK8_B1_UDB06_A0, 0x40006506
.set CYDEV_UWRK_UWRK8_B1_UDB07_A0, 0x40006507
.set CYDEV_UWRK_UWRK8_B1_UDB08_A0, 0x40006508
.set CYDEV_UWRK_UWRK8_B1_UDB09_A0, 0x40006509
.set CYDEV_UWRK_UWRK8_B1_UDB10_A0, 0x4000650a
.set CYDEV_UWRK_UWRK8_B1_UDB11_A0, 0x4000650b
.set CYDEV_UWRK_UWRK8_B1_UDB04_A1, 0x40006514
.set CYDEV_UWRK_UWRK8_B1_UDB05_A1, 0x40006515
.set CYDEV_UWRK_UWRK8_B1_UDB06_A1, 0x40006516
.set CYDEV_UWRK_UWRK8_B1_UDB07_A1, 0x40006517
.set CYDEV_UWRK_UWRK8_B1_UDB08_A1, 0x40006518
.set CYDEV_UWRK_UWRK8_B1_UDB09_A1, 0x40006519
.set CYDEV_UWRK_UWRK8_B1_UDB10_A1, 0x4000651a
.set CYDEV_UWRK_UWRK8_B1_UDB11_A1, 0x4000651b
.set CYDEV_UWRK_UWRK8_B1_UDB04_D0, 0x40006524
.set CYDEV_UWRK_UWRK8_B1_UDB05_D0, 0x40006525
.set CYDEV_UWRK_UWRK8_B1_UDB06_D0, 0x40006526
.set CYDEV_UWRK_UWRK8_B1_UDB07_D0, 0x40006527
.set CYDEV_UWRK_UWRK8_B1_UDB08_D0, 0x40006528
.set CYDEV_UWRK_UWRK8_B1_UDB09_D0, 0x40006529
.set CYDEV_UWRK_UWRK8_B1_UDB10_D0, 0x4000652a
.set CYDEV_UWRK_UWRK8_B1_UDB11_D0, 0x4000652b
.set CYDEV_UWRK_UWRK8_B1_UDB04_D1, 0x40006534
.set CYDEV_UWRK_UWRK8_B1_UDB05_D1, 0x40006535
.set CYDEV_UWRK_UWRK8_B1_UDB06_D1, 0x40006536
.set CYDEV_UWRK_UWRK8_B1_UDB07_D1, 0x40006537
.set CYDEV_UWRK_UWRK8_B1_UDB08_D1, 0x40006538
.set CYDEV_UWRK_UWRK8_B1_UDB09_D1, 0x40006539
.set CYDEV_UWRK_UWRK8_B1_UDB10_D1, 0x4000653a
.set CYDEV_UWRK_UWRK8_B1_UDB11_D1, 0x4000653b
.set CYDEV_UWRK_UWRK8_B1_UDB04_F0, 0x40006544
.set CYDEV_UWRK_UWRK8_B1_UDB05_F0, 0x40006545
.set CYDEV_UWRK_UWRK8_B1_UDB06_F0, 0x40006546
.set CYDEV_UWRK_UWRK8_B1_UDB07_F0, 0x40006547
.set CYDEV_UWRK_UWRK8_B1_UDB08_F0, 0x40006548
.set CYDEV_UWRK_UWRK8_B1_UDB09_F0, 0x40006549
.set CYDEV_UWRK_UWRK8_B1_UDB10_F0, 0x4000654a
.set CYDEV_UWRK_UWRK8_B1_UDB11_F0, 0x4000654b
.set CYDEV_UWRK_UWRK8_B1_UDB04_F1, 0x40006554
.set CYDEV_UWRK_UWRK8_B1_UDB05_F1, 0x40006555
.set CYDEV_UWRK_UWRK8_B1_UDB06_F1, 0x40006556
.set CYDEV_UWRK_UWRK8_B1_UDB07_F1, 0x40006557
.set CYDEV_UWRK_UWRK8_B1_UDB08_F1, 0x40006558
.set CYDEV_UWRK_UWRK8_B1_UDB09_F1, 0x40006559
.set CYDEV_UWRK_UWRK8_B1_UDB10_F1, 0x4000655a
.set CYDEV_UWRK_UWRK8_B1_UDB11_F1, 0x4000655b
.set CYDEV_UWRK_UWRK8_B1_UDB04_ST, 0x40006564
.set CYDEV_UWRK_UWRK8_B1_UDB05_ST, 0x40006565
.set CYDEV_UWRK_UWRK8_B1_UDB06_ST, 0x40006566
.set CYDEV_UWRK_UWRK8_B1_UDB07_ST, 0x40006567
.set CYDEV_UWRK_UWRK8_B1_UDB08_ST, 0x40006568
.set CYDEV_UWRK_UWRK8_B1_UDB09_ST, 0x40006569
.set CYDEV_UWRK_UWRK8_B1_UDB10_ST, 0x4000656a
.set CYDEV_UWRK_UWRK8_B1_UDB11_ST, 0x4000656b
.set CYDEV_UWRK_UWRK8_B1_UDB04_CTL, 0x40006574
.set CYDEV_UWRK_UWRK8_B1_UDB05_CTL, 0x40006575
.set CYDEV_UWRK_UWRK8_B1_UDB06_CTL, 0x40006576
.set CYDEV_UWRK_UWRK8_B1_UDB07_CTL, 0x40006577
.set CYDEV_UWRK_UWRK8_B1_UDB08_CTL, 0x40006578
.set CYDEV_UWRK_UWRK8_B1_UDB09_CTL, 0x40006579
.set CYDEV_UWRK_UWRK8_B1_UDB10_CTL, 0x4000657a
.set CYDEV_UWRK_UWRK8_B1_UDB11_CTL, 0x4000657b
.set CYDEV_UWRK_UWRK8_B1_UDB04_MSK, 0x40006584
.set CYDEV_UWRK_UWRK8_B1_UDB05_MSK, 0x40006585
.set CYDEV_UWRK_UWRK8_B1_UDB06_MSK, 0x40006586
.set CYDEV_UWRK_UWRK8_B1_UDB07_MSK, 0x40006587
.set CYDEV_UWRK_UWRK8_B1_UDB08_MSK, 0x40006588
.set CYDEV_UWRK_UWRK8_B1_UDB09_MSK, 0x40006589
.set CYDEV_UWRK_UWRK8_B1_UDB10_MSK, 0x4000658a
.set CYDEV_UWRK_UWRK8_B1_UDB11_MSK, 0x4000658b
.set CYDEV_UWRK_UWRK8_B1_UDB04_ACTL, 0x40006594
.set CYDEV_UWRK_UWRK8_B1_UDB05_ACTL, 0x40006595
.set CYDEV_UWRK_UWRK8_B1_UDB06_ACTL, 0x40006596
.set CYDEV_UWRK_UWRK8_B1_UDB07_ACTL, 0x40006597
.set CYDEV_UWRK_UWRK8_B1_UDB08_ACTL, 0x40006598
.set CYDEV_UWRK_UWRK8_B1_UDB09_ACTL, 0x40006599
.set CYDEV_UWRK_UWRK8_B1_UDB10_ACTL, 0x4000659a
.set CYDEV_UWRK_UWRK8_B1_UDB11_ACTL, 0x4000659b
.set CYDEV_UWRK_UWRK8_B1_UDB04_MC, 0x400065a4
.set CYDEV_UWRK_UWRK8_B1_UDB05_MC, 0x400065a5
.set CYDEV_UWRK_UWRK8_B1_UDB06_MC, 0x400065a6
.set CYDEV_UWRK_UWRK8_B1_UDB07_MC, 0x400065a7
.set CYDEV_UWRK_UWRK8_B1_UDB08_MC, 0x400065a8
.set CYDEV_UWRK_UWRK8_B1_UDB09_MC, 0x400065a9
.set CYDEV_UWRK_UWRK8_B1_UDB10_MC, 0x400065aa
.set CYDEV_UWRK_UWRK8_B1_UDB11_MC, 0x400065ab
.set CYDEV_UWRK_UWRK16_BASE, 0x40006800
.set CYDEV_UWRK_UWRK16_SIZE, 0x00000760
.set CYDEV_UWRK_UWRK16_CAT_BASE, 0x40006800
.set CYDEV_UWRK_UWRK16_CAT_SIZE, 0x00000760
.set CYDEV_UWRK_UWRK16_CAT_B0_BASE, 0x40006800
.set CYDEV_UWRK_UWRK16_CAT_B0_SIZE, 0x00000160
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1, 0x40006800
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1, 0x40006802
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1, 0x40006804
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1, 0x40006806
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1, 0x40006808
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1, 0x4000680a
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1, 0x4000680c
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1, 0x4000680e
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1, 0x40006810
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1, 0x40006812
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1, 0x40006814
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1, 0x40006816
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1, 0x40006818
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1, 0x4000681a
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1, 0x4000681c
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1, 0x4000681e
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1, 0x40006840
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1, 0x40006842
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1, 0x40006844
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1, 0x40006846
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1, 0x40006848
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1, 0x4000684a
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1, 0x4000684c
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1, 0x4000684e
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1, 0x40006850
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1, 0x40006852
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1, 0x40006854
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1, 0x40006856
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1, 0x40006858
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1, 0x4000685a
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1, 0x4000685c
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1, 0x4000685e
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1, 0x40006880
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1, 0x40006882
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1, 0x40006884
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1, 0x40006886
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1, 0x40006888
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1, 0x4000688a
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1, 0x4000688c
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1, 0x4000688e
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1, 0x40006890
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1, 0x40006892
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1, 0x40006894
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1, 0x40006896
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1, 0x40006898
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1, 0x4000689a
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1, 0x4000689c
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1, 0x4000689e
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL, 0x400068c0
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL, 0x400068c2
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL, 0x400068c4
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL, 0x400068c6
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL, 0x400068c8
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL, 0x400068ca
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL, 0x400068cc
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL, 0x400068ce
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL, 0x400068d0
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL, 0x400068d2
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL, 0x400068d4
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL, 0x400068d6
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL, 0x400068d8
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL, 0x400068da
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL, 0x400068dc
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL, 0x400068de
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL, 0x40006900
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL, 0x40006902
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL, 0x40006904
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL, 0x40006906
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL, 0x40006908
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL, 0x4000690a
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL, 0x4000690c
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL, 0x4000690e
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL, 0x40006910
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL, 0x40006912
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL, 0x40006914
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL, 0x40006916
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL, 0x40006918
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL, 0x4000691a
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL, 0x4000691c
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL, 0x4000691e
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00, 0x40006940
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00, 0x40006942
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00, 0x40006944
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00, 0x40006946
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00, 0x40006948
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00, 0x4000694a
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00, 0x4000694c
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00, 0x4000694e
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00, 0x40006950
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00, 0x40006952
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00, 0x40006954
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00, 0x40006956
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00, 0x40006958
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00, 0x4000695a
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00, 0x4000695c
.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00, 0x4000695e
.set CYDEV_UWRK_UWRK16_CAT_B1_BASE, 0x40006a00
.set CYDEV_UWRK_UWRK16_CAT_B1_SIZE, 0x00000160
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1, 0x40006a08
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1, 0x40006a0a
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1, 0x40006a0c
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1, 0x40006a0e
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1, 0x40006a10
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1, 0x40006a12
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1, 0x40006a14
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1, 0x40006a16
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1, 0x40006a48
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1, 0x40006a4a
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1, 0x40006a4c
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1, 0x40006a4e
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1, 0x40006a50
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1, 0x40006a52
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1, 0x40006a54
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1, 0x40006a56
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1, 0x40006a88
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1, 0x40006a8a
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1, 0x40006a8c
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1, 0x40006a8e
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1, 0x40006a90
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1, 0x40006a92
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1, 0x40006a94
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1, 0x40006a96
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL, 0x40006ac8
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL, 0x40006aca
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL, 0x40006acc
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL, 0x40006ace
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL, 0x40006ad0
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL, 0x40006ad2
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL, 0x40006ad4
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL, 0x40006ad6
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL, 0x40006b08
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL, 0x40006b0a
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL, 0x40006b0c
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL, 0x40006b0e
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL, 0x40006b10
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL, 0x40006b12
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL, 0x40006b14
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL, 0x40006b16
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00, 0x40006b48
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00, 0x40006b4a
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00, 0x40006b4c
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00, 0x40006b4e
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00, 0x40006b50
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00, 0x40006b52
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00, 0x40006b54
.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00, 0x40006b56
.set CYDEV_UWRK_UWRK16_DEF_BASE, 0x40006800
.set CYDEV_UWRK_UWRK16_DEF_SIZE, 0x0000075e
.set CYDEV_UWRK_UWRK16_DEF_B0_BASE, 0x40006800
.set CYDEV_UWRK_UWRK16_DEF_B0_SIZE, 0x0000015e
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0, 0x40006800
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0, 0x40006802
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0, 0x40006804
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0, 0x40006806
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0, 0x40006808
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0, 0x4000680a
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0, 0x4000680c
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0, 0x4000680e
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0, 0x40006810
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0, 0x40006812
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0, 0x40006814
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0, 0x40006816
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0, 0x40006818
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0, 0x4000681a
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0, 0x4000681c
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1, 0x40006820
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1, 0x40006822
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1, 0x40006824
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1, 0x40006826
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1, 0x40006828
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1, 0x4000682a
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1, 0x4000682c
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1, 0x4000682e
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1, 0x40006830
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1, 0x40006832
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1, 0x40006834
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1, 0x40006836
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1, 0x40006838
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1, 0x4000683a
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1, 0x4000683c
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0, 0x40006840
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0, 0x40006842
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0, 0x40006844
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0, 0x40006846
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0, 0x40006848
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0, 0x4000684a
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0, 0x4000684c
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0, 0x4000684e
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0, 0x40006850
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0, 0x40006852
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0, 0x40006854
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0, 0x40006856
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0, 0x40006858
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0, 0x4000685a
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0, 0x4000685c
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1, 0x40006860
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1, 0x40006862
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1, 0x40006864
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1, 0x40006866
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1, 0x40006868
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1, 0x4000686a
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1, 0x4000686c
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1, 0x4000686e
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1, 0x40006870
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1, 0x40006872
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1, 0x40006874
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1, 0x40006876
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1, 0x40006878
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1, 0x4000687a
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1, 0x4000687c
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0, 0x40006880
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0, 0x40006882
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0, 0x40006884
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0, 0x40006886
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0, 0x40006888
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0, 0x4000688a
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0, 0x4000688c
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0, 0x4000688e
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0, 0x40006890
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0, 0x40006892
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0, 0x40006894
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0, 0x40006896
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0, 0x40006898
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0, 0x4000689a
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0, 0x4000689c
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1, 0x400068a0
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1, 0x400068a2
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1, 0x400068a4
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1, 0x400068a6
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1, 0x400068a8
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1, 0x400068aa
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1, 0x400068ac
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1, 0x400068ae
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1, 0x400068b0
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1, 0x400068b2
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1, 0x400068b4
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1, 0x400068b6
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1, 0x400068b8
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1, 0x400068ba
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1, 0x400068bc
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST, 0x400068c0
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST, 0x400068c2
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST, 0x400068c4
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST, 0x400068c6
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST, 0x400068c8
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST, 0x400068ca
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST, 0x400068cc
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST, 0x400068ce
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST, 0x400068d0
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST, 0x400068d2
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST, 0x400068d4
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST, 0x400068d6
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST, 0x400068d8
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST, 0x400068da
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST, 0x400068dc
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL, 0x400068e0
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL, 0x400068e2
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL, 0x400068e4
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL, 0x400068e6
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL, 0x400068e8
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL, 0x400068ea
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL, 0x400068ec
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL, 0x400068ee
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL, 0x400068f0
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL, 0x400068f2
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL, 0x400068f4
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL, 0x400068f6
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL, 0x400068f8
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL, 0x400068fa
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL, 0x400068fc
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK, 0x40006900
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK, 0x40006902
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK, 0x40006904
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK, 0x40006906
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK, 0x40006908
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK, 0x4000690a
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK, 0x4000690c
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK, 0x4000690e
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK, 0x40006910
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK, 0x40006912
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK, 0x40006914
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK, 0x40006916
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK, 0x40006918
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK, 0x4000691a
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK, 0x4000691c
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL, 0x40006920
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL, 0x40006922
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL, 0x40006924
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL, 0x40006926
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL, 0x40006928
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL, 0x4000692a
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL, 0x4000692c
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL, 0x4000692e
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL, 0x40006930
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL, 0x40006932
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL, 0x40006934
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL, 0x40006936
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL, 0x40006938
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL, 0x4000693a
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL, 0x4000693c
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC, 0x40006940
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC, 0x40006942
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC, 0x40006944
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC, 0x40006946
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC, 0x40006948
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC, 0x4000694a
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC, 0x4000694c
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC, 0x4000694e
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC, 0x40006950
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC, 0x40006952
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC, 0x40006954
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC, 0x40006956
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC, 0x40006958
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC, 0x4000695a
.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC, 0x4000695c
.set CYDEV_UWRK_UWRK16_DEF_B1_BASE, 0x40006a00
.set CYDEV_UWRK_UWRK16_DEF_B1_SIZE, 0x0000015e
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0, 0x40006a08
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0, 0x40006a0a
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0, 0x40006a0c
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0, 0x40006a0e
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0, 0x40006a10
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0, 0x40006a12
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0, 0x40006a14
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0, 0x40006a16
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1, 0x40006a28
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1, 0x40006a2a
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1, 0x40006a2c
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1, 0x40006a2e
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1, 0x40006a30
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1, 0x40006a32
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1, 0x40006a34
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1, 0x40006a36
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0, 0x40006a48
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0, 0x40006a4a
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0, 0x40006a4c
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0, 0x40006a4e
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0, 0x40006a50
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0, 0x40006a52
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0, 0x40006a54
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0, 0x40006a56
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1, 0x40006a68
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1, 0x40006a6a
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1, 0x40006a6c
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1, 0x40006a6e
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1, 0x40006a70
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1, 0x40006a72
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1, 0x40006a74
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1, 0x40006a76
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0, 0x40006a88
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0, 0x40006a8a
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0, 0x40006a8c
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0, 0x40006a8e
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0, 0x40006a90
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0, 0x40006a92
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0, 0x40006a94
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0, 0x40006a96
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1, 0x40006aa8
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1, 0x40006aaa
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1, 0x40006aac
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1, 0x40006aae
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1, 0x40006ab0
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1, 0x40006ab2
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1, 0x40006ab4
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1, 0x40006ab6
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST, 0x40006ac8
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST, 0x40006aca
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST, 0x40006acc
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST, 0x40006ace
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST, 0x40006ad0
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST, 0x40006ad2
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST, 0x40006ad4
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST, 0x40006ad6
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL, 0x40006ae8
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL, 0x40006aea
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL, 0x40006aec
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL, 0x40006aee
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL, 0x40006af0
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL, 0x40006af2
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL, 0x40006af4
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL, 0x40006af6
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK, 0x40006b08
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK, 0x40006b0a
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK, 0x40006b0c
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK, 0x40006b0e
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK, 0x40006b10
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK, 0x40006b12
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK, 0x40006b14
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK, 0x40006b16
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL, 0x40006b28
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL, 0x40006b2a
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL, 0x40006b2c
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL, 0x40006b2e
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL, 0x40006b30
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL, 0x40006b32
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL, 0x40006b34
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL, 0x40006b36
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC, 0x40006b48
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC, 0x40006b4a
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC, 0x40006b4c
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC, 0x40006b4e
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC, 0x40006b50
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC, 0x40006b52
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC, 0x40006b54
.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC, 0x40006b56
.set CYDEV_PHUB_BASE, 0x40007000
.set CYDEV_PHUB_SIZE, 0x00000c00
.set CYDEV_PHUB_CFG, 0x40007000
.set CYDEV_PHUB_ERR, 0x40007004
.set CYDEV_PHUB_ERR_ADR, 0x40007008
.set CYDEV_PHUB_CH0_BASE, 0x40007010
.set CYDEV_PHUB_CH0_SIZE, 0x0000000c
.set CYDEV_PHUB_CH0_BASIC_CFG, 0x40007010
.set CYDEV_PHUB_CH0_ACTION, 0x40007014
.set CYDEV_PHUB_CH0_BASIC_STATUS, 0x40007018
.set CYDEV_PHUB_CH1_BASE, 0x40007020
.set CYDEV_PHUB_CH1_SIZE, 0x0000000c
.set CYDEV_PHUB_CH1_BASIC_CFG, 0x40007020
.set CYDEV_PHUB_CH1_ACTION, 0x40007024
.set CYDEV_PHUB_CH1_BASIC_STATUS, 0x40007028
.set CYDEV_PHUB_CH2_BASE, 0x40007030
.set CYDEV_PHUB_CH2_SIZE, 0x0000000c
.set CYDEV_PHUB_CH2_BASIC_CFG, 0x40007030
.set CYDEV_PHUB_CH2_ACTION, 0x40007034
.set CYDEV_PHUB_CH2_BASIC_STATUS, 0x40007038
.set CYDEV_PHUB_CH3_BASE, 0x40007040
.set CYDEV_PHUB_CH3_SIZE, 0x0000000c
.set CYDEV_PHUB_CH3_BASIC_CFG, 0x40007040
.set CYDEV_PHUB_CH3_ACTION, 0x40007044
.set CYDEV_PHUB_CH3_BASIC_STATUS, 0x40007048
.set CYDEV_PHUB_CH4_BASE, 0x40007050
.set CYDEV_PHUB_CH4_SIZE, 0x0000000c
.set CYDEV_PHUB_CH4_BASIC_CFG, 0x40007050
.set CYDEV_PHUB_CH4_ACTION, 0x40007054
.set CYDEV_PHUB_CH4_BASIC_STATUS, 0x40007058
.set CYDEV_PHUB_CH5_BASE, 0x40007060
.set CYDEV_PHUB_CH5_SIZE, 0x0000000c
.set CYDEV_PHUB_CH5_BASIC_CFG, 0x40007060
.set CYDEV_PHUB_CH5_ACTION, 0x40007064
.set CYDEV_PHUB_CH5_BASIC_STATUS, 0x40007068
.set CYDEV_PHUB_CH6_BASE, 0x40007070
.set CYDEV_PHUB_CH6_SIZE, 0x0000000c
.set CYDEV_PHUB_CH6_BASIC_CFG, 0x40007070
.set CYDEV_PHUB_CH6_ACTION, 0x40007074
.set CYDEV_PHUB_CH6_BASIC_STATUS, 0x40007078
.set CYDEV_PHUB_CH7_BASE, 0x40007080
.set CYDEV_PHUB_CH7_SIZE, 0x0000000c
.set CYDEV_PHUB_CH7_BASIC_CFG, 0x40007080
.set CYDEV_PHUB_CH7_ACTION, 0x40007084
.set CYDEV_PHUB_CH7_BASIC_STATUS, 0x40007088
.set CYDEV_PHUB_CH8_BASE, 0x40007090
.set CYDEV_PHUB_CH8_SIZE, 0x0000000c
.set CYDEV_PHUB_CH8_BASIC_CFG, 0x40007090
.set CYDEV_PHUB_CH8_ACTION, 0x40007094
.set CYDEV_PHUB_CH8_BASIC_STATUS, 0x40007098
.set CYDEV_PHUB_CH9_BASE, 0x400070a0
.set CYDEV_PHUB_CH9_SIZE, 0x0000000c
.set CYDEV_PHUB_CH9_BASIC_CFG, 0x400070a0
.set CYDEV_PHUB_CH9_ACTION, 0x400070a4
.set CYDEV_PHUB_CH9_BASIC_STATUS, 0x400070a8
.set CYDEV_PHUB_CH10_BASE, 0x400070b0
.set CYDEV_PHUB_CH10_SIZE, 0x0000000c
.set CYDEV_PHUB_CH10_BASIC_CFG, 0x400070b0
.set CYDEV_PHUB_CH10_ACTION, 0x400070b4
.set CYDEV_PHUB_CH10_BASIC_STATUS, 0x400070b8
.set CYDEV_PHUB_CH11_BASE, 0x400070c0
.set CYDEV_PHUB_CH11_SIZE, 0x0000000c
.set CYDEV_PHUB_CH11_BASIC_CFG, 0x400070c0
.set CYDEV_PHUB_CH11_ACTION, 0x400070c4
.set CYDEV_PHUB_CH11_BASIC_STATUS, 0x400070c8
.set CYDEV_PHUB_CH12_BASE, 0x400070d0
.set CYDEV_PHUB_CH12_SIZE, 0x0000000c
.set CYDEV_PHUB_CH12_BASIC_CFG, 0x400070d0
.set CYDEV_PHUB_CH12_ACTION, 0x400070d4
.set CYDEV_PHUB_CH12_BASIC_STATUS, 0x400070d8
.set CYDEV_PHUB_CH13_BASE, 0x400070e0
.set CYDEV_PHUB_CH13_SIZE, 0x0000000c
.set CYDEV_PHUB_CH13_BASIC_CFG, 0x400070e0
.set CYDEV_PHUB_CH13_ACTION, 0x400070e4
.set CYDEV_PHUB_CH13_BASIC_STATUS, 0x400070e8
.set CYDEV_PHUB_CH14_BASE, 0x400070f0
.set CYDEV_PHUB_CH14_SIZE, 0x0000000c
.set CYDEV_PHUB_CH14_BASIC_CFG, 0x400070f0
.set CYDEV_PHUB_CH14_ACTION, 0x400070f4
.set CYDEV_PHUB_CH14_BASIC_STATUS, 0x400070f8
.set CYDEV_PHUB_CH15_BASE, 0x40007100
.set CYDEV_PHUB_CH15_SIZE, 0x0000000c
.set CYDEV_PHUB_CH15_BASIC_CFG, 0x40007100
.set CYDEV_PHUB_CH15_ACTION, 0x40007104
.set CYDEV_PHUB_CH15_BASIC_STATUS, 0x40007108
.set CYDEV_PHUB_CH16_BASE, 0x40007110
.set CYDEV_PHUB_CH16_SIZE, 0x0000000c
.set CYDEV_PHUB_CH16_BASIC_CFG, 0x40007110
.set CYDEV_PHUB_CH16_ACTION, 0x40007114
.set CYDEV_PHUB_CH16_BASIC_STATUS, 0x40007118
.set CYDEV_PHUB_CH17_BASE, 0x40007120
.set CYDEV_PHUB_CH17_SIZE, 0x0000000c
.set CYDEV_PHUB_CH17_BASIC_CFG, 0x40007120
.set CYDEV_PHUB_CH17_ACTION, 0x40007124
.set CYDEV_PHUB_CH17_BASIC_STATUS, 0x40007128
.set CYDEV_PHUB_CH18_BASE, 0x40007130
.set CYDEV_PHUB_CH18_SIZE, 0x0000000c
.set CYDEV_PHUB_CH18_BASIC_CFG, 0x40007130
.set CYDEV_PHUB_CH18_ACTION, 0x40007134
.set CYDEV_PHUB_CH18_BASIC_STATUS, 0x40007138
.set CYDEV_PHUB_CH19_BASE, 0x40007140
.set CYDEV_PHUB_CH19_SIZE, 0x0000000c
.set CYDEV_PHUB_CH19_BASIC_CFG, 0x40007140
.set CYDEV_PHUB_CH19_ACTION, 0x40007144
.set CYDEV_PHUB_CH19_BASIC_STATUS, 0x40007148
.set CYDEV_PHUB_CH20_BASE, 0x40007150
.set CYDEV_PHUB_CH20_SIZE, 0x0000000c
.set CYDEV_PHUB_CH20_BASIC_CFG, 0x40007150
.set CYDEV_PHUB_CH20_ACTION, 0x40007154
.set CYDEV_PHUB_CH20_BASIC_STATUS, 0x40007158
.set CYDEV_PHUB_CH21_BASE, 0x40007160
.set CYDEV_PHUB_CH21_SIZE, 0x0000000c
.set CYDEV_PHUB_CH21_BASIC_CFG, 0x40007160
.set CYDEV_PHUB_CH21_ACTION, 0x40007164
.set CYDEV_PHUB_CH21_BASIC_STATUS, 0x40007168
.set CYDEV_PHUB_CH22_BASE, 0x40007170
.set CYDEV_PHUB_CH22_SIZE, 0x0000000c
.set CYDEV_PHUB_CH22_BASIC_CFG, 0x40007170
.set CYDEV_PHUB_CH22_ACTION, 0x40007174
.set CYDEV_PHUB_CH22_BASIC_STATUS, 0x40007178
.set CYDEV_PHUB_CH23_BASE, 0x40007180
.set CYDEV_PHUB_CH23_SIZE, 0x0000000c
.set CYDEV_PHUB_CH23_BASIC_CFG, 0x40007180
.set CYDEV_PHUB_CH23_ACTION, 0x40007184
.set CYDEV_PHUB_CH23_BASIC_STATUS, 0x40007188
.set CYDEV_PHUB_CFGMEM0_BASE, 0x40007600
.set CYDEV_PHUB_CFGMEM0_SIZE, 0x00000008
.set CYDEV_PHUB_CFGMEM0_CFG0, 0x40007600
.set CYDEV_PHUB_CFGMEM0_CFG1, 0x40007604
.set CYDEV_PHUB_CFGMEM1_BASE, 0x40007608
.set CYDEV_PHUB_CFGMEM1_SIZE, 0x00000008
.set CYDEV_PHUB_CFGMEM1_CFG0, 0x40007608
.set CYDEV_PHUB_CFGMEM1_CFG1, 0x4000760c
.set CYDEV_PHUB_CFGMEM2_BASE, 0x40007610
.set CYDEV_PHUB_CFGMEM2_SIZE, 0x00000008
.set CYDEV_PHUB_CFGMEM2_CFG0, 0x40007610
.set CYDEV_PHUB_CFGMEM2_CFG1, 0x40007614
.set CYDEV_PHUB_CFGMEM3_BASE, 0x40007618
.set CYDEV_PHUB_CFGMEM3_SIZE, 0x00000008
.set CYDEV_PHUB_CFGMEM3_CFG0, 0x40007618
.set CYDEV_PHUB_CFGMEM3_CFG1, 0x4000761c
.set CYDEV_PHUB_CFGMEM4_BASE, 0x40007620
.set CYDEV_PHUB_CFGMEM4_SIZE, 0x00000008
.set CYDEV_PHUB_CFGMEM4_CFG0, 0x40007620
.set CYDEV_PHUB_CFGMEM4_CFG1, 0x40007624
.set CYDEV_PHUB_CFGMEM5_BASE, 0x40007628
.set CYDEV_PHUB_CFGMEM5_SIZE, 0x00000008
.set CYDEV_PHUB_CFGMEM5_CFG0, 0x40007628
.set CYDEV_PHUB_CFGMEM5_CFG1, 0x4000762c
.set CYDEV_PHUB_CFGMEM6_BASE, 0x40007630
.set CYDEV_PHUB_CFGMEM6_SIZE, 0x00000008
.set CYDEV_PHUB_CFGMEM6_CFG0, 0x40007630
.set CYDEV_PHUB_CFGMEM6_CFG1, 0x40007634
.set CYDEV_PHUB_CFGMEM7_BASE, 0x40007638
.set CYDEV_PHUB_CFGMEM7_SIZE, 0x00000008
.set CYDEV_PHUB_CFGMEM7_CFG0, 0x40007638
.set CYDEV_PHUB_CFGMEM7_CFG1, 0x4000763c
.set CYDEV_PHUB_CFGMEM8_BASE, 0x40007640
.set CYDEV_PHUB_CFGMEM8_SIZE, 0x00000008
.set CYDEV_PHUB_CFGMEM8_CFG0, 0x40007640
.set CYDEV_PHUB_CFGMEM8_CFG1, 0x40007644
.set CYDEV_PHUB_CFGMEM9_BASE, 0x40007648
.set CYDEV_PHUB_CFGMEM9_SIZE, 0x00000008
.set CYDEV_PHUB_CFGMEM9_CFG0, 0x40007648
.set CYDEV_PHUB_CFGMEM9_CFG1, 0x4000764c
.set CYDEV_PHUB_CFGMEM10_BASE, 0x40007650
.set CYDEV_PHUB_CFGMEM10_SIZE, 0x00000008
.set CYDEV_PHUB_CFGMEM10_CFG0, 0x40007650
.set CYDEV_PHUB_CFGMEM10_CFG1, 0x40007654
.set CYDEV_PHUB_CFGMEM11_BASE, 0x40007658
.set CYDEV_PHUB_CFGMEM11_SIZE, 0x00000008
.set CYDEV_PHUB_CFGMEM11_CFG0, 0x40007658
.set CYDEV_PHUB_CFGMEM11_CFG1, 0x4000765c
.set CYDEV_PHUB_CFGMEM12_BASE, 0x40007660
.set CYDEV_PHUB_CFGMEM12_SIZE, 0x00000008
.set CYDEV_PHUB_CFGMEM12_CFG0, 0x40007660
.set CYDEV_PHUB_CFGMEM12_CFG1, 0x40007664
.set CYDEV_PHUB_CFGMEM13_BASE, 0x40007668
.set CYDEV_PHUB_CFGMEM13_SIZE, 0x00000008
.set CYDEV_PHUB_CFGMEM13_CFG0, 0x40007668
.set CYDEV_PHUB_CFGMEM13_CFG1, 0x4000766c
.set CYDEV_PHUB_CFGMEM14_BASE, 0x40007670
.set CYDEV_PHUB_CFGMEM14_SIZE, 0x00000008
.set CYDEV_PHUB_CFGMEM14_CFG0, 0x40007670
.set CYDEV_PHUB_CFGMEM14_CFG1, 0x40007674
.set CYDEV_PHUB_CFGMEM15_BASE, 0x40007678
.set CYDEV_PHUB_CFGMEM15_SIZE, 0x00000008
.set CYDEV_PHUB_CFGMEM15_CFG0, 0x40007678
.set CYDEV_PHUB_CFGMEM15_CFG1, 0x4000767c
.set CYDEV_PHUB_CFGMEM16_BASE, 0x40007680
.set CYDEV_PHUB_CFGMEM16_SIZE, 0x00000008
.set CYDEV_PHUB_CFGMEM16_CFG0, 0x40007680
.set CYDEV_PHUB_CFGMEM16_CFG1, 0x40007684
.set CYDEV_PHUB_CFGMEM17_BASE, 0x40007688
.set CYDEV_PHUB_CFGMEM17_SIZE, 0x00000008
.set CYDEV_PHUB_CFGMEM17_CFG0, 0x40007688
.set CYDEV_PHUB_CFGMEM17_CFG1, 0x4000768c
.set CYDEV_PHUB_CFGMEM18_BASE, 0x40007690
.set CYDEV_PHUB_CFGMEM18_SIZE, 0x00000008
.set CYDEV_PHUB_CFGMEM18_CFG0, 0x40007690
.set CYDEV_PHUB_CFGMEM18_CFG1, 0x40007694
.set CYDEV_PHUB_CFGMEM19_BASE, 0x40007698
.set CYDEV_PHUB_CFGMEM19_SIZE, 0x00000008
.set CYDEV_PHUB_CFGMEM19_CFG0, 0x40007698
.set CYDEV_PHUB_CFGMEM19_CFG1, 0x4000769c
.set CYDEV_PHUB_CFGMEM20_BASE, 0x400076a0
.set CYDEV_PHUB_CFGMEM20_SIZE, 0x00000008
.set CYDEV_PHUB_CFGMEM20_CFG0, 0x400076a0
.set CYDEV_PHUB_CFGMEM20_CFG1, 0x400076a4
.set CYDEV_PHUB_CFGMEM21_BASE, 0x400076a8
.set CYDEV_PHUB_CFGMEM21_SIZE, 0x00000008
.set CYDEV_PHUB_CFGMEM21_CFG0, 0x400076a8
.set CYDEV_PHUB_CFGMEM21_CFG1, 0x400076ac
.set CYDEV_PHUB_CFGMEM22_BASE, 0x400076b0
.set CYDEV_PHUB_CFGMEM22_SIZE, 0x00000008
.set CYDEV_PHUB_CFGMEM22_CFG0, 0x400076b0
.set CYDEV_PHUB_CFGMEM22_CFG1, 0x400076b4
.set CYDEV_PHUB_CFGMEM23_BASE, 0x400076b8
.set CYDEV_PHUB_CFGMEM23_SIZE, 0x00000008
.set CYDEV_PHUB_CFGMEM23_CFG0, 0x400076b8
.set CYDEV_PHUB_CFGMEM23_CFG1, 0x400076bc
.set CYDEV_PHUB_TDMEM0_BASE, 0x40007800
.set CYDEV_PHUB_TDMEM0_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM0_ORIG_TD0, 0x40007800
.set CYDEV_PHUB_TDMEM0_ORIG_TD1, 0x40007804
.set CYDEV_PHUB_TDMEM1_BASE, 0x40007808
.set CYDEV_PHUB_TDMEM1_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM1_ORIG_TD0, 0x40007808
.set CYDEV_PHUB_TDMEM1_ORIG_TD1, 0x4000780c
.set CYDEV_PHUB_TDMEM2_BASE, 0x40007810
.set CYDEV_PHUB_TDMEM2_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM2_ORIG_TD0, 0x40007810
.set CYDEV_PHUB_TDMEM2_ORIG_TD1, 0x40007814
.set CYDEV_PHUB_TDMEM3_BASE, 0x40007818
.set CYDEV_PHUB_TDMEM3_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM3_ORIG_TD0, 0x40007818
.set CYDEV_PHUB_TDMEM3_ORIG_TD1, 0x4000781c
.set CYDEV_PHUB_TDMEM4_BASE, 0x40007820
.set CYDEV_PHUB_TDMEM4_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM4_ORIG_TD0, 0x40007820
.set CYDEV_PHUB_TDMEM4_ORIG_TD1, 0x40007824
.set CYDEV_PHUB_TDMEM5_BASE, 0x40007828
.set CYDEV_PHUB_TDMEM5_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM5_ORIG_TD0, 0x40007828
.set CYDEV_PHUB_TDMEM5_ORIG_TD1, 0x4000782c
.set CYDEV_PHUB_TDMEM6_BASE, 0x40007830
.set CYDEV_PHUB_TDMEM6_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM6_ORIG_TD0, 0x40007830
.set CYDEV_PHUB_TDMEM6_ORIG_TD1, 0x40007834
.set CYDEV_PHUB_TDMEM7_BASE, 0x40007838
.set CYDEV_PHUB_TDMEM7_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM7_ORIG_TD0, 0x40007838
.set CYDEV_PHUB_TDMEM7_ORIG_TD1, 0x4000783c
.set CYDEV_PHUB_TDMEM8_BASE, 0x40007840
.set CYDEV_PHUB_TDMEM8_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM8_ORIG_TD0, 0x40007840
.set CYDEV_PHUB_TDMEM8_ORIG_TD1, 0x40007844
.set CYDEV_PHUB_TDMEM9_BASE, 0x40007848
.set CYDEV_PHUB_TDMEM9_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM9_ORIG_TD0, 0x40007848
.set CYDEV_PHUB_TDMEM9_ORIG_TD1, 0x4000784c
.set CYDEV_PHUB_TDMEM10_BASE, 0x40007850
.set CYDEV_PHUB_TDMEM10_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM10_ORIG_TD0, 0x40007850
.set CYDEV_PHUB_TDMEM10_ORIG_TD1, 0x40007854
.set CYDEV_PHUB_TDMEM11_BASE, 0x40007858
.set CYDEV_PHUB_TDMEM11_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM11_ORIG_TD0, 0x40007858
.set CYDEV_PHUB_TDMEM11_ORIG_TD1, 0x4000785c
.set CYDEV_PHUB_TDMEM12_BASE, 0x40007860
.set CYDEV_PHUB_TDMEM12_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM12_ORIG_TD0, 0x40007860
.set CYDEV_PHUB_TDMEM12_ORIG_TD1, 0x40007864
.set CYDEV_PHUB_TDMEM13_BASE, 0x40007868
.set CYDEV_PHUB_TDMEM13_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM13_ORIG_TD0, 0x40007868
.set CYDEV_PHUB_TDMEM13_ORIG_TD1, 0x4000786c
.set CYDEV_PHUB_TDMEM14_BASE, 0x40007870
.set CYDEV_PHUB_TDMEM14_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM14_ORIG_TD0, 0x40007870
.set CYDEV_PHUB_TDMEM14_ORIG_TD1, 0x40007874
.set CYDEV_PHUB_TDMEM15_BASE, 0x40007878
.set CYDEV_PHUB_TDMEM15_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM15_ORIG_TD0, 0x40007878
.set CYDEV_PHUB_TDMEM15_ORIG_TD1, 0x4000787c
.set CYDEV_PHUB_TDMEM16_BASE, 0x40007880
.set CYDEV_PHUB_TDMEM16_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM16_ORIG_TD0, 0x40007880
.set CYDEV_PHUB_TDMEM16_ORIG_TD1, 0x40007884
.set CYDEV_PHUB_TDMEM17_BASE, 0x40007888
.set CYDEV_PHUB_TDMEM17_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM17_ORIG_TD0, 0x40007888
.set CYDEV_PHUB_TDMEM17_ORIG_TD1, 0x4000788c
.set CYDEV_PHUB_TDMEM18_BASE, 0x40007890
.set CYDEV_PHUB_TDMEM18_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM18_ORIG_TD0, 0x40007890
.set CYDEV_PHUB_TDMEM18_ORIG_TD1, 0x40007894
.set CYDEV_PHUB_TDMEM19_BASE, 0x40007898
.set CYDEV_PHUB_TDMEM19_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM19_ORIG_TD0, 0x40007898
.set CYDEV_PHUB_TDMEM19_ORIG_TD1, 0x4000789c
.set CYDEV_PHUB_TDMEM20_BASE, 0x400078a0
.set CYDEV_PHUB_TDMEM20_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM20_ORIG_TD0, 0x400078a0
.set CYDEV_PHUB_TDMEM20_ORIG_TD1, 0x400078a4
.set CYDEV_PHUB_TDMEM21_BASE, 0x400078a8
.set CYDEV_PHUB_TDMEM21_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM21_ORIG_TD0, 0x400078a8
.set CYDEV_PHUB_TDMEM21_ORIG_TD1, 0x400078ac
.set CYDEV_PHUB_TDMEM22_BASE, 0x400078b0
.set CYDEV_PHUB_TDMEM22_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM22_ORIG_TD0, 0x400078b0
.set CYDEV_PHUB_TDMEM22_ORIG_TD1, 0x400078b4
.set CYDEV_PHUB_TDMEM23_BASE, 0x400078b8
.set CYDEV_PHUB_TDMEM23_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM23_ORIG_TD0, 0x400078b8
.set CYDEV_PHUB_TDMEM23_ORIG_TD1, 0x400078bc
.set CYDEV_PHUB_TDMEM24_BASE, 0x400078c0
.set CYDEV_PHUB_TDMEM24_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM24_ORIG_TD0, 0x400078c0
.set CYDEV_PHUB_TDMEM24_ORIG_TD1, 0x400078c4
.set CYDEV_PHUB_TDMEM25_BASE, 0x400078c8
.set CYDEV_PHUB_TDMEM25_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM25_ORIG_TD0, 0x400078c8
.set CYDEV_PHUB_TDMEM25_ORIG_TD1, 0x400078cc
.set CYDEV_PHUB_TDMEM26_BASE, 0x400078d0
.set CYDEV_PHUB_TDMEM26_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM26_ORIG_TD0, 0x400078d0
.set CYDEV_PHUB_TDMEM26_ORIG_TD1, 0x400078d4
.set CYDEV_PHUB_TDMEM27_BASE, 0x400078d8
.set CYDEV_PHUB_TDMEM27_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM27_ORIG_TD0, 0x400078d8
.set CYDEV_PHUB_TDMEM27_ORIG_TD1, 0x400078dc
.set CYDEV_PHUB_TDMEM28_BASE, 0x400078e0
.set CYDEV_PHUB_TDMEM28_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM28_ORIG_TD0, 0x400078e0
.set CYDEV_PHUB_TDMEM28_ORIG_TD1, 0x400078e4
.set CYDEV_PHUB_TDMEM29_BASE, 0x400078e8
.set CYDEV_PHUB_TDMEM29_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM29_ORIG_TD0, 0x400078e8
.set CYDEV_PHUB_TDMEM29_ORIG_TD1, 0x400078ec
.set CYDEV_PHUB_TDMEM30_BASE, 0x400078f0
.set CYDEV_PHUB_TDMEM30_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM30_ORIG_TD0, 0x400078f0
.set CYDEV_PHUB_TDMEM30_ORIG_TD1, 0x400078f4
.set CYDEV_PHUB_TDMEM31_BASE, 0x400078f8
.set CYDEV_PHUB_TDMEM31_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM31_ORIG_TD0, 0x400078f8
.set CYDEV_PHUB_TDMEM31_ORIG_TD1, 0x400078fc
.set CYDEV_PHUB_TDMEM32_BASE, 0x40007900
.set CYDEV_PHUB_TDMEM32_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM32_ORIG_TD0, 0x40007900
.set CYDEV_PHUB_TDMEM32_ORIG_TD1, 0x40007904
.set CYDEV_PHUB_TDMEM33_BASE, 0x40007908
.set CYDEV_PHUB_TDMEM33_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM33_ORIG_TD0, 0x40007908
.set CYDEV_PHUB_TDMEM33_ORIG_TD1, 0x4000790c
.set CYDEV_PHUB_TDMEM34_BASE, 0x40007910
.set CYDEV_PHUB_TDMEM34_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM34_ORIG_TD0, 0x40007910
.set CYDEV_PHUB_TDMEM34_ORIG_TD1, 0x40007914
.set CYDEV_PHUB_TDMEM35_BASE, 0x40007918
.set CYDEV_PHUB_TDMEM35_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM35_ORIG_TD0, 0x40007918
.set CYDEV_PHUB_TDMEM35_ORIG_TD1, 0x4000791c
.set CYDEV_PHUB_TDMEM36_BASE, 0x40007920
.set CYDEV_PHUB_TDMEM36_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM36_ORIG_TD0, 0x40007920
.set CYDEV_PHUB_TDMEM36_ORIG_TD1, 0x40007924
.set CYDEV_PHUB_TDMEM37_BASE, 0x40007928
.set CYDEV_PHUB_TDMEM37_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM37_ORIG_TD0, 0x40007928
.set CYDEV_PHUB_TDMEM37_ORIG_TD1, 0x4000792c
.set CYDEV_PHUB_TDMEM38_BASE, 0x40007930
.set CYDEV_PHUB_TDMEM38_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM38_ORIG_TD0, 0x40007930
.set CYDEV_PHUB_TDMEM38_ORIG_TD1, 0x40007934
.set CYDEV_PHUB_TDMEM39_BASE, 0x40007938
.set CYDEV_PHUB_TDMEM39_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM39_ORIG_TD0, 0x40007938
.set CYDEV_PHUB_TDMEM39_ORIG_TD1, 0x4000793c
.set CYDEV_PHUB_TDMEM40_BASE, 0x40007940
.set CYDEV_PHUB_TDMEM40_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM40_ORIG_TD0, 0x40007940
.set CYDEV_PHUB_TDMEM40_ORIG_TD1, 0x40007944
.set CYDEV_PHUB_TDMEM41_BASE, 0x40007948
.set CYDEV_PHUB_TDMEM41_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM41_ORIG_TD0, 0x40007948
.set CYDEV_PHUB_TDMEM41_ORIG_TD1, 0x4000794c
.set CYDEV_PHUB_TDMEM42_BASE, 0x40007950
.set CYDEV_PHUB_TDMEM42_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM42_ORIG_TD0, 0x40007950
.set CYDEV_PHUB_TDMEM42_ORIG_TD1, 0x40007954
.set CYDEV_PHUB_TDMEM43_BASE, 0x40007958
.set CYDEV_PHUB_TDMEM43_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM43_ORIG_TD0, 0x40007958
.set CYDEV_PHUB_TDMEM43_ORIG_TD1, 0x4000795c
.set CYDEV_PHUB_TDMEM44_BASE, 0x40007960
.set CYDEV_PHUB_TDMEM44_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM44_ORIG_TD0, 0x40007960
.set CYDEV_PHUB_TDMEM44_ORIG_TD1, 0x40007964
.set CYDEV_PHUB_TDMEM45_BASE, 0x40007968
.set CYDEV_PHUB_TDMEM45_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM45_ORIG_TD0, 0x40007968
.set CYDEV_PHUB_TDMEM45_ORIG_TD1, 0x4000796c
.set CYDEV_PHUB_TDMEM46_BASE, 0x40007970
.set CYDEV_PHUB_TDMEM46_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM46_ORIG_TD0, 0x40007970
.set CYDEV_PHUB_TDMEM46_ORIG_TD1, 0x40007974
.set CYDEV_PHUB_TDMEM47_BASE, 0x40007978
.set CYDEV_PHUB_TDMEM47_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM47_ORIG_TD0, 0x40007978
.set CYDEV_PHUB_TDMEM47_ORIG_TD1, 0x4000797c
.set CYDEV_PHUB_TDMEM48_BASE, 0x40007980
.set CYDEV_PHUB_TDMEM48_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM48_ORIG_TD0, 0x40007980
.set CYDEV_PHUB_TDMEM48_ORIG_TD1, 0x40007984
.set CYDEV_PHUB_TDMEM49_BASE, 0x40007988
.set CYDEV_PHUB_TDMEM49_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM49_ORIG_TD0, 0x40007988
.set CYDEV_PHUB_TDMEM49_ORIG_TD1, 0x4000798c
.set CYDEV_PHUB_TDMEM50_BASE, 0x40007990
.set CYDEV_PHUB_TDMEM50_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM50_ORIG_TD0, 0x40007990
.set CYDEV_PHUB_TDMEM50_ORIG_TD1, 0x40007994
.set CYDEV_PHUB_TDMEM51_BASE, 0x40007998
.set CYDEV_PHUB_TDMEM51_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM51_ORIG_TD0, 0x40007998
.set CYDEV_PHUB_TDMEM51_ORIG_TD1, 0x4000799c
.set CYDEV_PHUB_TDMEM52_BASE, 0x400079a0
.set CYDEV_PHUB_TDMEM52_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM52_ORIG_TD0, 0x400079a0
.set CYDEV_PHUB_TDMEM52_ORIG_TD1, 0x400079a4
.set CYDEV_PHUB_TDMEM53_BASE, 0x400079a8
.set CYDEV_PHUB_TDMEM53_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM53_ORIG_TD0, 0x400079a8
.set CYDEV_PHUB_TDMEM53_ORIG_TD1, 0x400079ac
.set CYDEV_PHUB_TDMEM54_BASE, 0x400079b0
.set CYDEV_PHUB_TDMEM54_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM54_ORIG_TD0, 0x400079b0
.set CYDEV_PHUB_TDMEM54_ORIG_TD1, 0x400079b4
.set CYDEV_PHUB_TDMEM55_BASE, 0x400079b8
.set CYDEV_PHUB_TDMEM55_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM55_ORIG_TD0, 0x400079b8
.set CYDEV_PHUB_TDMEM55_ORIG_TD1, 0x400079bc
.set CYDEV_PHUB_TDMEM56_BASE, 0x400079c0
.set CYDEV_PHUB_TDMEM56_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM56_ORIG_TD0, 0x400079c0
.set CYDEV_PHUB_TDMEM56_ORIG_TD1, 0x400079c4
.set CYDEV_PHUB_TDMEM57_BASE, 0x400079c8
.set CYDEV_PHUB_TDMEM57_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM57_ORIG_TD0, 0x400079c8
.set CYDEV_PHUB_TDMEM57_ORIG_TD1, 0x400079cc
.set CYDEV_PHUB_TDMEM58_BASE, 0x400079d0
.set CYDEV_PHUB_TDMEM58_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM58_ORIG_TD0, 0x400079d0
.set CYDEV_PHUB_TDMEM58_ORIG_TD1, 0x400079d4
.set CYDEV_PHUB_TDMEM59_BASE, 0x400079d8
.set CYDEV_PHUB_TDMEM59_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM59_ORIG_TD0, 0x400079d8
.set CYDEV_PHUB_TDMEM59_ORIG_TD1, 0x400079dc
.set CYDEV_PHUB_TDMEM60_BASE, 0x400079e0
.set CYDEV_PHUB_TDMEM60_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM60_ORIG_TD0, 0x400079e0
.set CYDEV_PHUB_TDMEM60_ORIG_TD1, 0x400079e4
.set CYDEV_PHUB_TDMEM61_BASE, 0x400079e8
.set CYDEV_PHUB_TDMEM61_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM61_ORIG_TD0, 0x400079e8
.set CYDEV_PHUB_TDMEM61_ORIG_TD1, 0x400079ec
.set CYDEV_PHUB_TDMEM62_BASE, 0x400079f0
.set CYDEV_PHUB_TDMEM62_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM62_ORIG_TD0, 0x400079f0
.set CYDEV_PHUB_TDMEM62_ORIG_TD1, 0x400079f4
.set CYDEV_PHUB_TDMEM63_BASE, 0x400079f8
.set CYDEV_PHUB_TDMEM63_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM63_ORIG_TD0, 0x400079f8
.set CYDEV_PHUB_TDMEM63_ORIG_TD1, 0x400079fc
.set CYDEV_PHUB_TDMEM64_BASE, 0x40007a00
.set CYDEV_PHUB_TDMEM64_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM64_ORIG_TD0, 0x40007a00
.set CYDEV_PHUB_TDMEM64_ORIG_TD1, 0x40007a04
.set CYDEV_PHUB_TDMEM65_BASE, 0x40007a08
.set CYDEV_PHUB_TDMEM65_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM65_ORIG_TD0, 0x40007a08
.set CYDEV_PHUB_TDMEM65_ORIG_TD1, 0x40007a0c
.set CYDEV_PHUB_TDMEM66_BASE, 0x40007a10
.set CYDEV_PHUB_TDMEM66_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM66_ORIG_TD0, 0x40007a10
.set CYDEV_PHUB_TDMEM66_ORIG_TD1, 0x40007a14
.set CYDEV_PHUB_TDMEM67_BASE, 0x40007a18
.set CYDEV_PHUB_TDMEM67_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM67_ORIG_TD0, 0x40007a18
.set CYDEV_PHUB_TDMEM67_ORIG_TD1, 0x40007a1c
.set CYDEV_PHUB_TDMEM68_BASE, 0x40007a20
.set CYDEV_PHUB_TDMEM68_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM68_ORIG_TD0, 0x40007a20
.set CYDEV_PHUB_TDMEM68_ORIG_TD1, 0x40007a24
.set CYDEV_PHUB_TDMEM69_BASE, 0x40007a28
.set CYDEV_PHUB_TDMEM69_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM69_ORIG_TD0, 0x40007a28
.set CYDEV_PHUB_TDMEM69_ORIG_TD1, 0x40007a2c
.set CYDEV_PHUB_TDMEM70_BASE, 0x40007a30
.set CYDEV_PHUB_TDMEM70_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM70_ORIG_TD0, 0x40007a30
.set CYDEV_PHUB_TDMEM70_ORIG_TD1, 0x40007a34
.set CYDEV_PHUB_TDMEM71_BASE, 0x40007a38
.set CYDEV_PHUB_TDMEM71_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM71_ORIG_TD0, 0x40007a38
.set CYDEV_PHUB_TDMEM71_ORIG_TD1, 0x40007a3c
.set CYDEV_PHUB_TDMEM72_BASE, 0x40007a40
.set CYDEV_PHUB_TDMEM72_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM72_ORIG_TD0, 0x40007a40
.set CYDEV_PHUB_TDMEM72_ORIG_TD1, 0x40007a44
.set CYDEV_PHUB_TDMEM73_BASE, 0x40007a48
.set CYDEV_PHUB_TDMEM73_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM73_ORIG_TD0, 0x40007a48
.set CYDEV_PHUB_TDMEM73_ORIG_TD1, 0x40007a4c
.set CYDEV_PHUB_TDMEM74_BASE, 0x40007a50
.set CYDEV_PHUB_TDMEM74_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM74_ORIG_TD0, 0x40007a50
.set CYDEV_PHUB_TDMEM74_ORIG_TD1, 0x40007a54
.set CYDEV_PHUB_TDMEM75_BASE, 0x40007a58
.set CYDEV_PHUB_TDMEM75_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM75_ORIG_TD0, 0x40007a58
.set CYDEV_PHUB_TDMEM75_ORIG_TD1, 0x40007a5c
.set CYDEV_PHUB_TDMEM76_BASE, 0x40007a60
.set CYDEV_PHUB_TDMEM76_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM76_ORIG_TD0, 0x40007a60
.set CYDEV_PHUB_TDMEM76_ORIG_TD1, 0x40007a64
.set CYDEV_PHUB_TDMEM77_BASE, 0x40007a68
.set CYDEV_PHUB_TDMEM77_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM77_ORIG_TD0, 0x40007a68
.set CYDEV_PHUB_TDMEM77_ORIG_TD1, 0x40007a6c
.set CYDEV_PHUB_TDMEM78_BASE, 0x40007a70
.set CYDEV_PHUB_TDMEM78_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM78_ORIG_TD0, 0x40007a70
.set CYDEV_PHUB_TDMEM78_ORIG_TD1, 0x40007a74
.set CYDEV_PHUB_TDMEM79_BASE, 0x40007a78
.set CYDEV_PHUB_TDMEM79_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM79_ORIG_TD0, 0x40007a78
.set CYDEV_PHUB_TDMEM79_ORIG_TD1, 0x40007a7c
.set CYDEV_PHUB_TDMEM80_BASE, 0x40007a80
.set CYDEV_PHUB_TDMEM80_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM80_ORIG_TD0, 0x40007a80
.set CYDEV_PHUB_TDMEM80_ORIG_TD1, 0x40007a84
.set CYDEV_PHUB_TDMEM81_BASE, 0x40007a88
.set CYDEV_PHUB_TDMEM81_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM81_ORIG_TD0, 0x40007a88
.set CYDEV_PHUB_TDMEM81_ORIG_TD1, 0x40007a8c
.set CYDEV_PHUB_TDMEM82_BASE, 0x40007a90
.set CYDEV_PHUB_TDMEM82_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM82_ORIG_TD0, 0x40007a90
.set CYDEV_PHUB_TDMEM82_ORIG_TD1, 0x40007a94
.set CYDEV_PHUB_TDMEM83_BASE, 0x40007a98
.set CYDEV_PHUB_TDMEM83_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM83_ORIG_TD0, 0x40007a98
.set CYDEV_PHUB_TDMEM83_ORIG_TD1, 0x40007a9c
.set CYDEV_PHUB_TDMEM84_BASE, 0x40007aa0
.set CYDEV_PHUB_TDMEM84_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM84_ORIG_TD0, 0x40007aa0
.set CYDEV_PHUB_TDMEM84_ORIG_TD1, 0x40007aa4
.set CYDEV_PHUB_TDMEM85_BASE, 0x40007aa8
.set CYDEV_PHUB_TDMEM85_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM85_ORIG_TD0, 0x40007aa8
.set CYDEV_PHUB_TDMEM85_ORIG_TD1, 0x40007aac
.set CYDEV_PHUB_TDMEM86_BASE, 0x40007ab0
.set CYDEV_PHUB_TDMEM86_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM86_ORIG_TD0, 0x40007ab0
.set CYDEV_PHUB_TDMEM86_ORIG_TD1, 0x40007ab4
.set CYDEV_PHUB_TDMEM87_BASE, 0x40007ab8
.set CYDEV_PHUB_TDMEM87_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM87_ORIG_TD0, 0x40007ab8
.set CYDEV_PHUB_TDMEM87_ORIG_TD1, 0x40007abc
.set CYDEV_PHUB_TDMEM88_BASE, 0x40007ac0
.set CYDEV_PHUB_TDMEM88_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM88_ORIG_TD0, 0x40007ac0
.set CYDEV_PHUB_TDMEM88_ORIG_TD1, 0x40007ac4
.set CYDEV_PHUB_TDMEM89_BASE, 0x40007ac8
.set CYDEV_PHUB_TDMEM89_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM89_ORIG_TD0, 0x40007ac8
.set CYDEV_PHUB_TDMEM89_ORIG_TD1, 0x40007acc
.set CYDEV_PHUB_TDMEM90_BASE, 0x40007ad0
.set CYDEV_PHUB_TDMEM90_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM90_ORIG_TD0, 0x40007ad0
.set CYDEV_PHUB_TDMEM90_ORIG_TD1, 0x40007ad4
.set CYDEV_PHUB_TDMEM91_BASE, 0x40007ad8
.set CYDEV_PHUB_TDMEM91_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM91_ORIG_TD0, 0x40007ad8
.set CYDEV_PHUB_TDMEM91_ORIG_TD1, 0x40007adc
.set CYDEV_PHUB_TDMEM92_BASE, 0x40007ae0
.set CYDEV_PHUB_TDMEM92_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM92_ORIG_TD0, 0x40007ae0
.set CYDEV_PHUB_TDMEM92_ORIG_TD1, 0x40007ae4
.set CYDEV_PHUB_TDMEM93_BASE, 0x40007ae8
.set CYDEV_PHUB_TDMEM93_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM93_ORIG_TD0, 0x40007ae8
.set CYDEV_PHUB_TDMEM93_ORIG_TD1, 0x40007aec
.set CYDEV_PHUB_TDMEM94_BASE, 0x40007af0
.set CYDEV_PHUB_TDMEM94_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM94_ORIG_TD0, 0x40007af0
.set CYDEV_PHUB_TDMEM94_ORIG_TD1, 0x40007af4
.set CYDEV_PHUB_TDMEM95_BASE, 0x40007af8
.set CYDEV_PHUB_TDMEM95_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM95_ORIG_TD0, 0x40007af8
.set CYDEV_PHUB_TDMEM95_ORIG_TD1, 0x40007afc
.set CYDEV_PHUB_TDMEM96_BASE, 0x40007b00
.set CYDEV_PHUB_TDMEM96_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM96_ORIG_TD0, 0x40007b00
.set CYDEV_PHUB_TDMEM96_ORIG_TD1, 0x40007b04
.set CYDEV_PHUB_TDMEM97_BASE, 0x40007b08
.set CYDEV_PHUB_TDMEM97_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM97_ORIG_TD0, 0x40007b08
.set CYDEV_PHUB_TDMEM97_ORIG_TD1, 0x40007b0c
.set CYDEV_PHUB_TDMEM98_BASE, 0x40007b10
.set CYDEV_PHUB_TDMEM98_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM98_ORIG_TD0, 0x40007b10
.set CYDEV_PHUB_TDMEM98_ORIG_TD1, 0x40007b14
.set CYDEV_PHUB_TDMEM99_BASE, 0x40007b18
.set CYDEV_PHUB_TDMEM99_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM99_ORIG_TD0, 0x40007b18
.set CYDEV_PHUB_TDMEM99_ORIG_TD1, 0x40007b1c
.set CYDEV_PHUB_TDMEM100_BASE, 0x40007b20
.set CYDEV_PHUB_TDMEM100_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM100_ORIG_TD0, 0x40007b20
.set CYDEV_PHUB_TDMEM100_ORIG_TD1, 0x40007b24
.set CYDEV_PHUB_TDMEM101_BASE, 0x40007b28
.set CYDEV_PHUB_TDMEM101_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM101_ORIG_TD0, 0x40007b28
.set CYDEV_PHUB_TDMEM101_ORIG_TD1, 0x40007b2c
.set CYDEV_PHUB_TDMEM102_BASE, 0x40007b30
.set CYDEV_PHUB_TDMEM102_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM102_ORIG_TD0, 0x40007b30
.set CYDEV_PHUB_TDMEM102_ORIG_TD1, 0x40007b34
.set CYDEV_PHUB_TDMEM103_BASE, 0x40007b38
.set CYDEV_PHUB_TDMEM103_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM103_ORIG_TD0, 0x40007b38
.set CYDEV_PHUB_TDMEM103_ORIG_TD1, 0x40007b3c
.set CYDEV_PHUB_TDMEM104_BASE, 0x40007b40
.set CYDEV_PHUB_TDMEM104_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM104_ORIG_TD0, 0x40007b40
.set CYDEV_PHUB_TDMEM104_ORIG_TD1, 0x40007b44
.set CYDEV_PHUB_TDMEM105_BASE, 0x40007b48
.set CYDEV_PHUB_TDMEM105_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM105_ORIG_TD0, 0x40007b48
.set CYDEV_PHUB_TDMEM105_ORIG_TD1, 0x40007b4c
.set CYDEV_PHUB_TDMEM106_BASE, 0x40007b50
.set CYDEV_PHUB_TDMEM106_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM106_ORIG_TD0, 0x40007b50
.set CYDEV_PHUB_TDMEM106_ORIG_TD1, 0x40007b54
.set CYDEV_PHUB_TDMEM107_BASE, 0x40007b58
.set CYDEV_PHUB_TDMEM107_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM107_ORIG_TD0, 0x40007b58
.set CYDEV_PHUB_TDMEM107_ORIG_TD1, 0x40007b5c
.set CYDEV_PHUB_TDMEM108_BASE, 0x40007b60
.set CYDEV_PHUB_TDMEM108_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM108_ORIG_TD0, 0x40007b60
.set CYDEV_PHUB_TDMEM108_ORIG_TD1, 0x40007b64
.set CYDEV_PHUB_TDMEM109_BASE, 0x40007b68
.set CYDEV_PHUB_TDMEM109_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM109_ORIG_TD0, 0x40007b68
.set CYDEV_PHUB_TDMEM109_ORIG_TD1, 0x40007b6c
.set CYDEV_PHUB_TDMEM110_BASE, 0x40007b70
.set CYDEV_PHUB_TDMEM110_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM110_ORIG_TD0, 0x40007b70
.set CYDEV_PHUB_TDMEM110_ORIG_TD1, 0x40007b74
.set CYDEV_PHUB_TDMEM111_BASE, 0x40007b78
.set CYDEV_PHUB_TDMEM111_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM111_ORIG_TD0, 0x40007b78
.set CYDEV_PHUB_TDMEM111_ORIG_TD1, 0x40007b7c
.set CYDEV_PHUB_TDMEM112_BASE, 0x40007b80
.set CYDEV_PHUB_TDMEM112_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM112_ORIG_TD0, 0x40007b80
.set CYDEV_PHUB_TDMEM112_ORIG_TD1, 0x40007b84
.set CYDEV_PHUB_TDMEM113_BASE, 0x40007b88
.set CYDEV_PHUB_TDMEM113_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM113_ORIG_TD0, 0x40007b88
.set CYDEV_PHUB_TDMEM113_ORIG_TD1, 0x40007b8c
.set CYDEV_PHUB_TDMEM114_BASE, 0x40007b90
.set CYDEV_PHUB_TDMEM114_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM114_ORIG_TD0, 0x40007b90
.set CYDEV_PHUB_TDMEM114_ORIG_TD1, 0x40007b94
.set CYDEV_PHUB_TDMEM115_BASE, 0x40007b98
.set CYDEV_PHUB_TDMEM115_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM115_ORIG_TD0, 0x40007b98
.set CYDEV_PHUB_TDMEM115_ORIG_TD1, 0x40007b9c
.set CYDEV_PHUB_TDMEM116_BASE, 0x40007ba0
.set CYDEV_PHUB_TDMEM116_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM116_ORIG_TD0, 0x40007ba0
.set CYDEV_PHUB_TDMEM116_ORIG_TD1, 0x40007ba4
.set CYDEV_PHUB_TDMEM117_BASE, 0x40007ba8
.set CYDEV_PHUB_TDMEM117_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM117_ORIG_TD0, 0x40007ba8
.set CYDEV_PHUB_TDMEM117_ORIG_TD1, 0x40007bac
.set CYDEV_PHUB_TDMEM118_BASE, 0x40007bb0
.set CYDEV_PHUB_TDMEM118_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM118_ORIG_TD0, 0x40007bb0
.set CYDEV_PHUB_TDMEM118_ORIG_TD1, 0x40007bb4
.set CYDEV_PHUB_TDMEM119_BASE, 0x40007bb8
.set CYDEV_PHUB_TDMEM119_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM119_ORIG_TD0, 0x40007bb8
.set CYDEV_PHUB_TDMEM119_ORIG_TD1, 0x40007bbc
.set CYDEV_PHUB_TDMEM120_BASE, 0x40007bc0
.set CYDEV_PHUB_TDMEM120_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM120_ORIG_TD0, 0x40007bc0
.set CYDEV_PHUB_TDMEM120_ORIG_TD1, 0x40007bc4
.set CYDEV_PHUB_TDMEM121_BASE, 0x40007bc8
.set CYDEV_PHUB_TDMEM121_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM121_ORIG_TD0, 0x40007bc8
.set CYDEV_PHUB_TDMEM121_ORIG_TD1, 0x40007bcc
.set CYDEV_PHUB_TDMEM122_BASE, 0x40007bd0
.set CYDEV_PHUB_TDMEM122_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM122_ORIG_TD0, 0x40007bd0
.set CYDEV_PHUB_TDMEM122_ORIG_TD1, 0x40007bd4
.set CYDEV_PHUB_TDMEM123_BASE, 0x40007bd8
.set CYDEV_PHUB_TDMEM123_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM123_ORIG_TD0, 0x40007bd8
.set CYDEV_PHUB_TDMEM123_ORIG_TD1, 0x40007bdc
.set CYDEV_PHUB_TDMEM124_BASE, 0x40007be0
.set CYDEV_PHUB_TDMEM124_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM124_ORIG_TD0, 0x40007be0
.set CYDEV_PHUB_TDMEM124_ORIG_TD1, 0x40007be4
.set CYDEV_PHUB_TDMEM125_BASE, 0x40007be8
.set CYDEV_PHUB_TDMEM125_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM125_ORIG_TD0, 0x40007be8
.set CYDEV_PHUB_TDMEM125_ORIG_TD1, 0x40007bec
.set CYDEV_PHUB_TDMEM126_BASE, 0x40007bf0
.set CYDEV_PHUB_TDMEM126_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM126_ORIG_TD0, 0x40007bf0
.set CYDEV_PHUB_TDMEM126_ORIG_TD1, 0x40007bf4
.set CYDEV_PHUB_TDMEM127_BASE, 0x40007bf8
.set CYDEV_PHUB_TDMEM127_SIZE, 0x00000008
.set CYDEV_PHUB_TDMEM127_ORIG_TD0, 0x40007bf8
.set CYDEV_PHUB_TDMEM127_ORIG_TD1, 0x40007bfc
.set CYDEV_EE_BASE, 0x40008000
.set CYDEV_EE_SIZE, 0x00000800
.set CYDEV_EE_DATA_MBASE, 0x40008000
.set CYDEV_EE_DATA_MSIZE, 0x00000800
.set CYDEV_CAN0_BASE, 0x4000a000
.set CYDEV_CAN0_SIZE, 0x000002a0
.set CYDEV_CAN0_CSR_BASE, 0x4000a000
.set CYDEV_CAN0_CSR_SIZE, 0x00000018
.set CYDEV_CAN0_CSR_INT_SR, 0x4000a000
.set CYDEV_CAN0_CSR_INT_EN, 0x4000a004
.set CYDEV_CAN0_CSR_BUF_SR, 0x4000a008
.set CYDEV_CAN0_CSR_ERR_SR, 0x4000a00c
.set CYDEV_CAN0_CSR_CMD, 0x4000a010
.set CYDEV_CAN0_CSR_CFG, 0x4000a014
.set CYDEV_CAN0_TX0_BASE, 0x4000a020
.set CYDEV_CAN0_TX0_SIZE, 0x00000010
.set CYDEV_CAN0_TX0_CMD, 0x4000a020
.set CYDEV_CAN0_TX0_ID, 0x4000a024
.set CYDEV_CAN0_TX0_DH, 0x4000a028
.set CYDEV_CAN0_TX0_DL, 0x4000a02c
.set CYDEV_CAN0_TX1_BASE, 0x4000a030
.set CYDEV_CAN0_TX1_SIZE, 0x00000010
.set CYDEV_CAN0_TX1_CMD, 0x4000a030
.set CYDEV_CAN0_TX1_ID, 0x4000a034
.set CYDEV_CAN0_TX1_DH, 0x4000a038
.set CYDEV_CAN0_TX1_DL, 0x4000a03c
.set CYDEV_CAN0_TX2_BASE, 0x4000a040
.set CYDEV_CAN0_TX2_SIZE, 0x00000010
.set CYDEV_CAN0_TX2_CMD, 0x4000a040
.set CYDEV_CAN0_TX2_ID, 0x4000a044
.set CYDEV_CAN0_TX2_DH, 0x4000a048
.set CYDEV_CAN0_TX2_DL, 0x4000a04c
.set CYDEV_CAN0_TX3_BASE, 0x4000a050
.set CYDEV_CAN0_TX3_SIZE, 0x00000010
.set CYDEV_CAN0_TX3_CMD, 0x4000a050
.set CYDEV_CAN0_TX3_ID, 0x4000a054
.set CYDEV_CAN0_TX3_DH, 0x4000a058
.set CYDEV_CAN0_TX3_DL, 0x4000a05c
.set CYDEV_CAN0_TX4_BASE, 0x4000a060
.set CYDEV_CAN0_TX4_SIZE, 0x00000010
.set CYDEV_CAN0_TX4_CMD, 0x4000a060
.set CYDEV_CAN0_TX4_ID, 0x4000a064
.set CYDEV_CAN0_TX4_DH, 0x4000a068
.set CYDEV_CAN0_TX4_DL, 0x4000a06c
.set CYDEV_CAN0_TX5_BASE, 0x4000a070
.set CYDEV_CAN0_TX5_SIZE, 0x00000010
.set CYDEV_CAN0_TX5_CMD, 0x4000a070
.set CYDEV_CAN0_TX5_ID, 0x4000a074
.set CYDEV_CAN0_TX5_DH, 0x4000a078
.set CYDEV_CAN0_TX5_DL, 0x4000a07c
.set CYDEV_CAN0_TX6_BASE, 0x4000a080
.set CYDEV_CAN0_TX6_SIZE, 0x00000010
.set CYDEV_CAN0_TX6_CMD, 0x4000a080
.set CYDEV_CAN0_TX6_ID, 0x4000a084
.set CYDEV_CAN0_TX6_DH, 0x4000a088
.set CYDEV_CAN0_TX6_DL, 0x4000a08c
.set CYDEV_CAN0_TX7_BASE, 0x4000a090
.set CYDEV_CAN0_TX7_SIZE, 0x00000010
.set CYDEV_CAN0_TX7_CMD, 0x4000a090
.set CYDEV_CAN0_TX7_ID, 0x4000a094
.set CYDEV_CAN0_TX7_DH, 0x4000a098
.set CYDEV_CAN0_TX7_DL, 0x4000a09c
.set CYDEV_CAN0_RX0_BASE, 0x4000a0a0
.set CYDEV_CAN0_RX0_SIZE, 0x00000020
.set CYDEV_CAN0_RX0_CMD, 0x4000a0a0
.set CYDEV_CAN0_RX0_ID, 0x4000a0a4
.set CYDEV_CAN0_RX0_DH, 0x4000a0a8
.set CYDEV_CAN0_RX0_DL, 0x4000a0ac
.set CYDEV_CAN0_RX0_AMR, 0x4000a0b0
.set CYDEV_CAN0_RX0_ACR, 0x4000a0b4
.set CYDEV_CAN0_RX0_AMRD, 0x4000a0b8
.set CYDEV_CAN0_RX0_ACRD, 0x4000a0bc
.set CYDEV_CAN0_RX1_BASE, 0x4000a0c0
.set CYDEV_CAN0_RX1_SIZE, 0x00000020
.set CYDEV_CAN0_RX1_CMD, 0x4000a0c0
.set CYDEV_CAN0_RX1_ID, 0x4000a0c4
.set CYDEV_CAN0_RX1_DH, 0x4000a0c8
.set CYDEV_CAN0_RX1_DL, 0x4000a0cc
.set CYDEV_CAN0_RX1_AMR, 0x4000a0d0
.set CYDEV_CAN0_RX1_ACR, 0x4000a0d4
.set CYDEV_CAN0_RX1_AMRD, 0x4000a0d8
.set CYDEV_CAN0_RX1_ACRD, 0x4000a0dc
.set CYDEV_CAN0_RX2_BASE, 0x4000a0e0
.set CYDEV_CAN0_RX2_SIZE, 0x00000020
.set CYDEV_CAN0_RX2_CMD, 0x4000a0e0
.set CYDEV_CAN0_RX2_ID, 0x4000a0e4
.set CYDEV_CAN0_RX2_DH, 0x4000a0e8
.set CYDEV_CAN0_RX2_DL, 0x4000a0ec
.set CYDEV_CAN0_RX2_AMR, 0x4000a0f0
.set CYDEV_CAN0_RX2_ACR, 0x4000a0f4
.set CYDEV_CAN0_RX2_AMRD, 0x4000a0f8
.set CYDEV_CAN0_RX2_ACRD, 0x4000a0fc
.set CYDEV_CAN0_RX3_BASE, 0x4000a100
.set CYDEV_CAN0_RX3_SIZE, 0x00000020
.set CYDEV_CAN0_RX3_CMD, 0x4000a100
.set CYDEV_CAN0_RX3_ID, 0x4000a104
.set CYDEV_CAN0_RX3_DH, 0x4000a108
.set CYDEV_CAN0_RX3_DL, 0x4000a10c
.set CYDEV_CAN0_RX3_AMR, 0x4000a110
.set CYDEV_CAN0_RX3_ACR, 0x4000a114
.set CYDEV_CAN0_RX3_AMRD, 0x4000a118
.set CYDEV_CAN0_RX3_ACRD, 0x4000a11c
.set CYDEV_CAN0_RX4_BASE, 0x4000a120
.set CYDEV_CAN0_RX4_SIZE, 0x00000020
.set CYDEV_CAN0_RX4_CMD, 0x4000a120
.set CYDEV_CAN0_RX4_ID, 0x4000a124
.set CYDEV_CAN0_RX4_DH, 0x4000a128
.set CYDEV_CAN0_RX4_DL, 0x4000a12c
.set CYDEV_CAN0_RX4_AMR, 0x4000a130
.set CYDEV_CAN0_RX4_ACR, 0x4000a134
.set CYDEV_CAN0_RX4_AMRD, 0x4000a138
.set CYDEV_CAN0_RX4_ACRD, 0x4000a13c
.set CYDEV_CAN0_RX5_BASE, 0x4000a140
.set CYDEV_CAN0_RX5_SIZE, 0x00000020
.set CYDEV_CAN0_RX5_CMD, 0x4000a140
.set CYDEV_CAN0_RX5_ID, 0x4000a144
.set CYDEV_CAN0_RX5_DH, 0x4000a148
.set CYDEV_CAN0_RX5_DL, 0x4000a14c
.set CYDEV_CAN0_RX5_AMR, 0x4000a150
.set CYDEV_CAN0_RX5_ACR, 0x4000a154
.set CYDEV_CAN0_RX5_AMRD, 0x4000a158
.set CYDEV_CAN0_RX5_ACRD, 0x4000a15c
.set CYDEV_CAN0_RX6_BASE, 0x4000a160
.set CYDEV_CAN0_RX6_SIZE, 0x00000020
.set CYDEV_CAN0_RX6_CMD, 0x4000a160
.set CYDEV_CAN0_RX6_ID, 0x4000a164
.set CYDEV_CAN0_RX6_DH, 0x4000a168
.set CYDEV_CAN0_RX6_DL, 0x4000a16c
.set CYDEV_CAN0_RX6_AMR, 0x4000a170
.set CYDEV_CAN0_RX6_ACR, 0x4000a174
.set CYDEV_CAN0_RX6_AMRD, 0x4000a178
.set CYDEV_CAN0_RX6_ACRD, 0x4000a17c
.set CYDEV_CAN0_RX7_BASE, 0x4000a180
.set CYDEV_CAN0_RX7_SIZE, 0x00000020
.set CYDEV_CAN0_RX7_CMD, 0x4000a180
.set CYDEV_CAN0_RX7_ID, 0x4000a184
.set CYDEV_CAN0_RX7_DH, 0x4000a188
.set CYDEV_CAN0_RX7_DL, 0x4000a18c
.set CYDEV_CAN0_RX7_AMR, 0x4000a190
.set CYDEV_CAN0_RX7_ACR, 0x4000a194
.set CYDEV_CAN0_RX7_AMRD, 0x4000a198
.set CYDEV_CAN0_RX7_ACRD, 0x4000a19c
.set CYDEV_CAN0_RX8_BASE, 0x4000a1a0
.set CYDEV_CAN0_RX8_SIZE, 0x00000020
.set CYDEV_CAN0_RX8_CMD, 0x4000a1a0
.set CYDEV_CAN0_RX8_ID, 0x4000a1a4
.set CYDEV_CAN0_RX8_DH, 0x4000a1a8
.set CYDEV_CAN0_RX8_DL, 0x4000a1ac
.set CYDEV_CAN0_RX8_AMR, 0x4000a1b0
.set CYDEV_CAN0_RX8_ACR, 0x4000a1b4
.set CYDEV_CAN0_RX8_AMRD, 0x4000a1b8
.set CYDEV_CAN0_RX8_ACRD, 0x4000a1bc
.set CYDEV_CAN0_RX9_BASE, 0x4000a1c0
.set CYDEV_CAN0_RX9_SIZE, 0x00000020
.set CYDEV_CAN0_RX9_CMD, 0x4000a1c0
.set CYDEV_CAN0_RX9_ID, 0x4000a1c4
.set CYDEV_CAN0_RX9_DH, 0x4000a1c8
.set CYDEV_CAN0_RX9_DL, 0x4000a1cc
.set CYDEV_CAN0_RX9_AMR, 0x4000a1d0
.set CYDEV_CAN0_RX9_ACR, 0x4000a1d4
.set CYDEV_CAN0_RX9_AMRD, 0x4000a1d8
.set CYDEV_CAN0_RX9_ACRD, 0x4000a1dc
.set CYDEV_CAN0_RX10_BASE, 0x4000a1e0
.set CYDEV_CAN0_RX10_SIZE, 0x00000020
.set CYDEV_CAN0_RX10_CMD, 0x4000a1e0
.set CYDEV_CAN0_RX10_ID, 0x4000a1e4
.set CYDEV_CAN0_RX10_DH, 0x4000a1e8
.set CYDEV_CAN0_RX10_DL, 0x4000a1ec
.set CYDEV_CAN0_RX10_AMR, 0x4000a1f0
.set CYDEV_CAN0_RX10_ACR, 0x4000a1f4
.set CYDEV_CAN0_RX10_AMRD, 0x4000a1f8
.set CYDEV_CAN0_RX10_ACRD, 0x4000a1fc
.set CYDEV_CAN0_RX11_BASE, 0x4000a200
.set CYDEV_CAN0_RX11_SIZE, 0x00000020
.set CYDEV_CAN0_RX11_CMD, 0x4000a200
.set CYDEV_CAN0_RX11_ID, 0x4000a204
.set CYDEV_CAN0_RX11_DH, 0x4000a208
.set CYDEV_CAN0_RX11_DL, 0x4000a20c
.set CYDEV_CAN0_RX11_AMR, 0x4000a210
.set CYDEV_CAN0_RX11_ACR, 0x4000a214
.set CYDEV_CAN0_RX11_AMRD, 0x4000a218
.set CYDEV_CAN0_RX11_ACRD, 0x4000a21c
.set CYDEV_CAN0_RX12_BASE, 0x4000a220
.set CYDEV_CAN0_RX12_SIZE, 0x00000020
.set CYDEV_CAN0_RX12_CMD, 0x4000a220
.set CYDEV_CAN0_RX12_ID, 0x4000a224
.set CYDEV_CAN0_RX12_DH, 0x4000a228
.set CYDEV_CAN0_RX12_DL, 0x4000a22c
.set CYDEV_CAN0_RX12_AMR, 0x4000a230
.set CYDEV_CAN0_RX12_ACR, 0x4000a234
.set CYDEV_CAN0_RX12_AMRD, 0x4000a238
.set CYDEV_CAN0_RX12_ACRD, 0x4000a23c
.set CYDEV_CAN0_RX13_BASE, 0x4000a240
.set CYDEV_CAN0_RX13_SIZE, 0x00000020
.set CYDEV_CAN0_RX13_CMD, 0x4000a240
.set CYDEV_CAN0_RX13_ID, 0x4000a244
.set CYDEV_CAN0_RX13_DH, 0x4000a248
.set CYDEV_CAN0_RX13_DL, 0x4000a24c
.set CYDEV_CAN0_RX13_AMR, 0x4000a250
.set CYDEV_CAN0_RX13_ACR, 0x4000a254
.set CYDEV_CAN0_RX13_AMRD, 0x4000a258
.set CYDEV_CAN0_RX13_ACRD, 0x4000a25c
.set CYDEV_CAN0_RX14_BASE, 0x4000a260
.set CYDEV_CAN0_RX14_SIZE, 0x00000020
.set CYDEV_CAN0_RX14_CMD, 0x4000a260
.set CYDEV_CAN0_RX14_ID, 0x4000a264
.set CYDEV_CAN0_RX14_DH, 0x4000a268
.set CYDEV_CAN0_RX14_DL, 0x4000a26c
.set CYDEV_CAN0_RX14_AMR, 0x4000a270
.set CYDEV_CAN0_RX14_ACR, 0x4000a274
.set CYDEV_CAN0_RX14_AMRD, 0x4000a278
.set CYDEV_CAN0_RX14_ACRD, 0x4000a27c
.set CYDEV_CAN0_RX15_BASE, 0x4000a280
.set CYDEV_CAN0_RX15_SIZE, 0x00000020
.set CYDEV_CAN0_RX15_CMD, 0x4000a280
.set CYDEV_CAN0_RX15_ID, 0x4000a284
.set CYDEV_CAN0_RX15_DH, 0x4000a288
.set CYDEV_CAN0_RX15_DL, 0x4000a28c
.set CYDEV_CAN0_RX15_AMR, 0x4000a290
.set CYDEV_CAN0_RX15_ACR, 0x4000a294
.set CYDEV_CAN0_RX15_AMRD, 0x4000a298
.set CYDEV_CAN0_RX15_ACRD, 0x4000a29c
.set CYDEV_DFB0_BASE, 0x4000c000
.set CYDEV_DFB0_SIZE, 0x000007b5
.set CYDEV_DFB0_DPA_SRAM_BASE, 0x4000c000
.set CYDEV_DFB0_DPA_SRAM_SIZE, 0x00000200
.set CYDEV_DFB0_DPA_SRAM_DATA_MBASE, 0x4000c000
.set CYDEV_DFB0_DPA_SRAM_DATA_MSIZE, 0x00000200
.set CYDEV_DFB0_DPB_SRAM_BASE, 0x4000c200
.set CYDEV_DFB0_DPB_SRAM_SIZE, 0x00000200
.set CYDEV_DFB0_DPB_SRAM_DATA_MBASE, 0x4000c200
.set CYDEV_DFB0_DPB_SRAM_DATA_MSIZE, 0x00000200
.set CYDEV_DFB0_CSA_SRAM_BASE, 0x4000c400
.set CYDEV_DFB0_CSA_SRAM_SIZE, 0x00000100
.set CYDEV_DFB0_CSA_SRAM_DATA_MBASE, 0x4000c400
.set CYDEV_DFB0_CSA_SRAM_DATA_MSIZE, 0x00000100
.set CYDEV_DFB0_CSB_SRAM_BASE, 0x4000c500
.set CYDEV_DFB0_CSB_SRAM_SIZE, 0x00000100
.set CYDEV_DFB0_CSB_SRAM_DATA_MBASE, 0x4000c500
.set CYDEV_DFB0_CSB_SRAM_DATA_MSIZE, 0x00000100
.set CYDEV_DFB0_FSM_SRAM_BASE, 0x4000c600
.set CYDEV_DFB0_FSM_SRAM_SIZE, 0x00000100
.set CYDEV_DFB0_FSM_SRAM_DATA_MBASE, 0x4000c600
.set CYDEV_DFB0_FSM_SRAM_DATA_MSIZE, 0x00000100
.set CYDEV_DFB0_ACU_SRAM_BASE, 0x4000c700
.set CYDEV_DFB0_ACU_SRAM_SIZE, 0x00000040
.set CYDEV_DFB0_ACU_SRAM_DATA_MBASE, 0x4000c700
.set CYDEV_DFB0_ACU_SRAM_DATA_MSIZE, 0x00000040
.set CYDEV_DFB0_CR, 0x4000c780
.set CYDEV_DFB0_SR, 0x4000c784
.set CYDEV_DFB0_RAM_EN, 0x4000c788
.set CYDEV_DFB0_RAM_DIR, 0x4000c78c
.set CYDEV_DFB0_SEMA, 0x4000c790
.set CYDEV_DFB0_DSI_CTRL, 0x4000c794
.set CYDEV_DFB0_INT_CTRL, 0x4000c798
.set CYDEV_DFB0_DMA_CTRL, 0x4000c79c
.set CYDEV_DFB0_STAGEA, 0x4000c7a0
.set CYDEV_DFB0_STAGEAM, 0x4000c7a1
.set CYDEV_DFB0_STAGEAH, 0x4000c7a2
.set CYDEV_DFB0_STAGEB, 0x4000c7a4
.set CYDEV_DFB0_STAGEBM, 0x4000c7a5
.set CYDEV_DFB0_STAGEBH, 0x4000c7a6
.set CYDEV_DFB0_HOLDA, 0x4000c7a8
.set CYDEV_DFB0_HOLDAM, 0x4000c7a9
.set CYDEV_DFB0_HOLDAH, 0x4000c7aa
.set CYDEV_DFB0_HOLDAS, 0x4000c7ab
.set CYDEV_DFB0_HOLDB, 0x4000c7ac
.set CYDEV_DFB0_HOLDBM, 0x4000c7ad
.set CYDEV_DFB0_HOLDBH, 0x4000c7ae
.set CYDEV_DFB0_HOLDBS, 0x4000c7af
.set CYDEV_DFB0_COHER, 0x4000c7b0
.set CYDEV_DFB0_DALIGN, 0x4000c7b4
.set CYDEV_UCFG_BASE, 0x40010000
.set CYDEV_UCFG_SIZE, 0x00005040
.set CYDEV_UCFG_B0_BASE, 0x40010000
.set CYDEV_UCFG_B0_SIZE, 0x00000fef
.set CYDEV_UCFG_B0_P0_BASE, 0x40010000
.set CYDEV_UCFG_B0_P0_SIZE, 0x000001ef
.set CYDEV_UCFG_B0_P0_U0_BASE, 0x40010000
.set CYDEV_UCFG_B0_P0_U0_SIZE, 0x00000070
.set CYDEV_UCFG_B0_P0_U0_PLD_IT0, 0x40010000
.set CYDEV_UCFG_B0_P0_U0_PLD_IT1, 0x40010004
.set CYDEV_UCFG_B0_P0_U0_PLD_IT2, 0x40010008
.set CYDEV_UCFG_B0_P0_U0_PLD_IT3, 0x4001000c
.set CYDEV_UCFG_B0_P0_U0_PLD_IT4, 0x40010010
.set CYDEV_UCFG_B0_P0_U0_PLD_IT5, 0x40010014
.set CYDEV_UCFG_B0_P0_U0_PLD_IT6, 0x40010018
.set CYDEV_UCFG_B0_P0_U0_PLD_IT7, 0x4001001c
.set CYDEV_UCFG_B0_P0_U0_PLD_IT8, 0x40010020
.set CYDEV_UCFG_B0_P0_U0_PLD_IT9, 0x40010024
.set CYDEV_UCFG_B0_P0_U0_PLD_IT10, 0x40010028
.set CYDEV_UCFG_B0_P0_U0_PLD_IT11, 0x4001002c
.set CYDEV_UCFG_B0_P0_U0_PLD_ORT0, 0x40010030
.set CYDEV_UCFG_B0_P0_U0_PLD_ORT1, 0x40010032
.set CYDEV_UCFG_B0_P0_U0_PLD_ORT2, 0x40010034
.set CYDEV_UCFG_B0_P0_U0_PLD_ORT3, 0x40010036
.set CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST, 0x40010038
.set CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB, 0x4001003a
.set CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET, 0x4001003c
.set CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS, 0x4001003e
.set CYDEV_UCFG_B0_P0_U0_CFG0, 0x40010040
.set CYDEV_UCFG_B0_P0_U0_CFG1, 0x40010041
.set CYDEV_UCFG_B0_P0_U0_CFG2, 0x40010042
.set CYDEV_UCFG_B0_P0_U0_CFG3, 0x40010043
.set CYDEV_UCFG_B0_P0_U0_CFG4, 0x40010044
.set CYDEV_UCFG_B0_P0_U0_CFG5, 0x40010045
.set CYDEV_UCFG_B0_P0_U0_CFG6, 0x40010046
.set CYDEV_UCFG_B0_P0_U0_CFG7, 0x40010047
.set CYDEV_UCFG_B0_P0_U0_CFG8, 0x40010048
.set CYDEV_UCFG_B0_P0_U0_CFG9, 0x40010049
.set CYDEV_UCFG_B0_P0_U0_CFG10, 0x4001004a
.set CYDEV_UCFG_B0_P0_U0_CFG11, 0x4001004b
.set CYDEV_UCFG_B0_P0_U0_CFG12, 0x4001004c
.set CYDEV_UCFG_B0_P0_U0_CFG13, 0x4001004d
.set CYDEV_UCFG_B0_P0_U0_CFG14, 0x4001004e
.set CYDEV_UCFG_B0_P0_U0_CFG15, 0x4001004f
.set CYDEV_UCFG_B0_P0_U0_CFG16, 0x40010050
.set CYDEV_UCFG_B0_P0_U0_CFG17, 0x40010051
.set CYDEV_UCFG_B0_P0_U0_CFG18, 0x40010052
.set CYDEV_UCFG_B0_P0_U0_CFG19, 0x40010053
.set CYDEV_UCFG_B0_P0_U0_CFG20, 0x40010054
.set CYDEV_UCFG_B0_P0_U0_CFG21, 0x40010055
.set CYDEV_UCFG_B0_P0_U0_CFG22, 0x40010056
.set CYDEV_UCFG_B0_P0_U0_CFG23, 0x40010057
.set CYDEV_UCFG_B0_P0_U0_CFG24, 0x40010058
.set CYDEV_UCFG_B0_P0_U0_CFG25, 0x40010059
.set CYDEV_UCFG_B0_P0_U0_CFG26, 0x4001005a
.set CYDEV_UCFG_B0_P0_U0_CFG27, 0x4001005b
.set CYDEV_UCFG_B0_P0_U0_CFG28, 0x4001005c
.set CYDEV_UCFG_B0_P0_U0_CFG29, 0x4001005d
.set CYDEV_UCFG_B0_P0_U0_CFG30, 0x4001005e
.set CYDEV_UCFG_B0_P0_U0_CFG31, 0x4001005f
.set CYDEV_UCFG_B0_P0_U0_DCFG0, 0x40010060
.set CYDEV_UCFG_B0_P0_U0_DCFG1, 0x40010062
.set CYDEV_UCFG_B0_P0_U0_DCFG2, 0x40010064
.set CYDEV_UCFG_B0_P0_U0_DCFG3, 0x40010066
.set CYDEV_UCFG_B0_P0_U0_DCFG4, 0x40010068
.set CYDEV_UCFG_B0_P0_U0_DCFG5, 0x4001006a
.set CYDEV_UCFG_B0_P0_U0_DCFG6, 0x4001006c
.set CYDEV_UCFG_B0_P0_U0_DCFG7, 0x4001006e
.set CYDEV_UCFG_B0_P0_U1_BASE, 0x40010080
.set CYDEV_UCFG_B0_P0_U1_SIZE, 0x00000070
.set CYDEV_UCFG_B0_P0_U1_PLD_IT0, 0x40010080
.set CYDEV_UCFG_B0_P0_U1_PLD_IT1, 0x40010084
.set CYDEV_UCFG_B0_P0_U1_PLD_IT2, 0x40010088
.set CYDEV_UCFG_B0_P0_U1_PLD_IT3, 0x4001008c
.set CYDEV_UCFG_B0_P0_U1_PLD_IT4, 0x40010090
.set CYDEV_UCFG_B0_P0_U1_PLD_IT5, 0x40010094
.set CYDEV_UCFG_B0_P0_U1_PLD_IT6, 0x40010098
.set CYDEV_UCFG_B0_P0_U1_PLD_IT7, 0x4001009c
.set CYDEV_UCFG_B0_P0_U1_PLD_IT8, 0x400100a0
.set CYDEV_UCFG_B0_P0_U1_PLD_IT9, 0x400100a4
.set CYDEV_UCFG_B0_P0_U1_PLD_IT10, 0x400100a8
.set CYDEV_UCFG_B0_P0_U1_PLD_IT11, 0x400100ac
.set CYDEV_UCFG_B0_P0_U1_PLD_ORT0, 0x400100b0
.set CYDEV_UCFG_B0_P0_U1_PLD_ORT1, 0x400100b2
.set CYDEV_UCFG_B0_P0_U1_PLD_ORT2, 0x400100b4
.set CYDEV_UCFG_B0_P0_U1_PLD_ORT3, 0x400100b6
.set CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST, 0x400100b8
.set CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB, 0x400100ba
.set CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET, 0x400100bc
.set CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS, 0x400100be
.set CYDEV_UCFG_B0_P0_U1_CFG0, 0x400100c0
.set CYDEV_UCFG_B0_P0_U1_CFG1, 0x400100c1
.set CYDEV_UCFG_B0_P0_U1_CFG2, 0x400100c2
.set CYDEV_UCFG_B0_P0_U1_CFG3, 0x400100c3
.set CYDEV_UCFG_B0_P0_U1_CFG4, 0x400100c4
.set CYDEV_UCFG_B0_P0_U1_CFG5, 0x400100c5
.set CYDEV_UCFG_B0_P0_U1_CFG6, 0x400100c6
.set CYDEV_UCFG_B0_P0_U1_CFG7, 0x400100c7
.set CYDEV_UCFG_B0_P0_U1_CFG8, 0x400100c8
.set CYDEV_UCFG_B0_P0_U1_CFG9, 0x400100c9
.set CYDEV_UCFG_B0_P0_U1_CFG10, 0x400100ca
.set CYDEV_UCFG_B0_P0_U1_CFG11, 0x400100cb
.set CYDEV_UCFG_B0_P0_U1_CFG12, 0x400100cc
.set CYDEV_UCFG_B0_P0_U1_CFG13, 0x400100cd
.set CYDEV_UCFG_B0_P0_U1_CFG14, 0x400100ce
.set CYDEV_UCFG_B0_P0_U1_CFG15, 0x400100cf
.set CYDEV_UCFG_B0_P0_U1_CFG16, 0x400100d0
.set CYDEV_UCFG_B0_P0_U1_CFG17, 0x400100d1
.set CYDEV_UCFG_B0_P0_U1_CFG18, 0x400100d2
.set CYDEV_UCFG_B0_P0_U1_CFG19, 0x400100d3
.set CYDEV_UCFG_B0_P0_U1_CFG20, 0x400100d4
.set CYDEV_UCFG_B0_P0_U1_CFG21, 0x400100d5
.set CYDEV_UCFG_B0_P0_U1_CFG22, 0x400100d6
.set CYDEV_UCFG_B0_P0_U1_CFG23, 0x400100d7
.set CYDEV_UCFG_B0_P0_U1_CFG24, 0x400100d8
.set CYDEV_UCFG_B0_P0_U1_CFG25, 0x400100d9
.set CYDEV_UCFG_B0_P0_U1_CFG26, 0x400100da
.set CYDEV_UCFG_B0_P0_U1_CFG27, 0x400100db
.set CYDEV_UCFG_B0_P0_U1_CFG28, 0x400100dc
.set CYDEV_UCFG_B0_P0_U1_CFG29, 0x400100dd
.set CYDEV_UCFG_B0_P0_U1_CFG30, 0x400100de
.set CYDEV_UCFG_B0_P0_U1_CFG31, 0x400100df
.set CYDEV_UCFG_B0_P0_U1_DCFG0, 0x400100e0
.set CYDEV_UCFG_B0_P0_U1_DCFG1, 0x400100e2
.set CYDEV_UCFG_B0_P0_U1_DCFG2, 0x400100e4
.set CYDEV_UCFG_B0_P0_U1_DCFG3, 0x400100e6
.set CYDEV_UCFG_B0_P0_U1_DCFG4, 0x400100e8
.set CYDEV_UCFG_B0_P0_U1_DCFG5, 0x400100ea
.set CYDEV_UCFG_B0_P0_U1_DCFG6, 0x400100ec
.set CYDEV_UCFG_B0_P0_U1_DCFG7, 0x400100ee
.set CYDEV_UCFG_B0_P0_ROUTE_BASE, 0x40010100
.set CYDEV_UCFG_B0_P0_ROUTE_SIZE, 0x000000ef
.set CYDEV_UCFG_B0_P1_BASE, 0x40010200
.set CYDEV_UCFG_B0_P1_SIZE, 0x000001ef
.set CYDEV_UCFG_B0_P1_U0_BASE, 0x40010200
.set CYDEV_UCFG_B0_P1_U0_SIZE, 0x00000070
.set CYDEV_UCFG_B0_P1_U0_PLD_IT0, 0x40010200
.set CYDEV_UCFG_B0_P1_U0_PLD_IT1, 0x40010204
.set CYDEV_UCFG_B0_P1_U0_PLD_IT2, 0x40010208
.set CYDEV_UCFG_B0_P1_U0_PLD_IT3, 0x4001020c
.set CYDEV_UCFG_B0_P1_U0_PLD_IT4, 0x40010210
.set CYDEV_UCFG_B0_P1_U0_PLD_IT5, 0x40010214
.set CYDEV_UCFG_B0_P1_U0_PLD_IT6, 0x40010218
.set CYDEV_UCFG_B0_P1_U0_PLD_IT7, 0x4001021c
.set CYDEV_UCFG_B0_P1_U0_PLD_IT8, 0x40010220
.set CYDEV_UCFG_B0_P1_U0_PLD_IT9, 0x40010224
.set CYDEV_UCFG_B0_P1_U0_PLD_IT10, 0x40010228
.set CYDEV_UCFG_B0_P1_U0_PLD_IT11, 0x4001022c
.set CYDEV_UCFG_B0_P1_U0_PLD_ORT0, 0x40010230
.set CYDEV_UCFG_B0_P1_U0_PLD_ORT1, 0x40010232
.set CYDEV_UCFG_B0_P1_U0_PLD_ORT2, 0x40010234
.set CYDEV_UCFG_B0_P1_U0_PLD_ORT3, 0x40010236
.set CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST, 0x40010238
.set CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB, 0x4001023a
.set CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET, 0x4001023c
.set CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS, 0x4001023e
.set CYDEV_UCFG_B0_P1_U0_CFG0, 0x40010240
.set CYDEV_UCFG_B0_P1_U0_CFG1, 0x40010241
.set CYDEV_UCFG_B0_P1_U0_CFG2, 0x40010242
.set CYDEV_UCFG_B0_P1_U0_CFG3, 0x40010243
.set CYDEV_UCFG_B0_P1_U0_CFG4, 0x40010244
.set CYDEV_UCFG_B0_P1_U0_CFG5, 0x40010245
.set CYDEV_UCFG_B0_P1_U0_CFG6, 0x40010246
.set CYDEV_UCFG_B0_P1_U0_CFG7, 0x40010247
.set CYDEV_UCFG_B0_P1_U0_CFG8, 0x40010248
.set CYDEV_UCFG_B0_P1_U0_CFG9, 0x40010249
.set CYDEV_UCFG_B0_P1_U0_CFG10, 0x4001024a
.set CYDEV_UCFG_B0_P1_U0_CFG11, 0x4001024b
.set CYDEV_UCFG_B0_P1_U0_CFG12, 0x4001024c
.set CYDEV_UCFG_B0_P1_U0_CFG13, 0x4001024d
.set CYDEV_UCFG_B0_P1_U0_CFG14, 0x4001024e
.set CYDEV_UCFG_B0_P1_U0_CFG15, 0x4001024f
.set CYDEV_UCFG_B0_P1_U0_CFG16, 0x40010250
.set CYDEV_UCFG_B0_P1_U0_CFG17, 0x40010251
.set CYDEV_UCFG_B0_P1_U0_CFG18, 0x40010252
.set CYDEV_UCFG_B0_P1_U0_CFG19, 0x40010253
.set CYDEV_UCFG_B0_P1_U0_CFG20, 0x40010254
.set CYDEV_UCFG_B0_P1_U0_CFG21, 0x40010255
.set CYDEV_UCFG_B0_P1_U0_CFG22, 0x40010256
.set CYDEV_UCFG_B0_P1_U0_CFG23, 0x40010257
.set CYDEV_UCFG_B0_P1_U0_CFG24, 0x40010258
.set CYDEV_UCFG_B0_P1_U0_CFG25, 0x40010259
.set CYDEV_UCFG_B0_P1_U0_CFG26, 0x4001025a
.set CYDEV_UCFG_B0_P1_U0_CFG27, 0x4001025b
.set CYDEV_UCFG_B0_P1_U0_CFG28, 0x4001025c
.set CYDEV_UCFG_B0_P1_U0_CFG29, 0x4001025d
.set CYDEV_UCFG_B0_P1_U0_CFG30, 0x4001025e
.set CYDEV_UCFG_B0_P1_U0_CFG31, 0x4001025f
.set CYDEV_UCFG_B0_P1_U0_DCFG0, 0x40010260
.set CYDEV_UCFG_B0_P1_U0_DCFG1, 0x40010262
.set CYDEV_UCFG_B0_P1_U0_DCFG2, 0x40010264
.set CYDEV_UCFG_B0_P1_U0_DCFG3, 0x40010266
.set CYDEV_UCFG_B0_P1_U0_DCFG4, 0x40010268
.set CYDEV_UCFG_B0_P1_U0_DCFG5, 0x4001026a
.set CYDEV_UCFG_B0_P1_U0_DCFG6, 0x4001026c
.set CYDEV_UCFG_B0_P1_U0_DCFG7, 0x4001026e
.set CYDEV_UCFG_B0_P1_U1_BASE, 0x40010280
.set CYDEV_UCFG_B0_P1_U1_SIZE, 0x00000070
.set CYDEV_UCFG_B0_P1_U1_PLD_IT0, 0x40010280
.set CYDEV_UCFG_B0_P1_U1_PLD_IT1, 0x40010284
.set CYDEV_UCFG_B0_P1_U1_PLD_IT2, 0x40010288
.set CYDEV_UCFG_B0_P1_U1_PLD_IT3, 0x4001028c
.set CYDEV_UCFG_B0_P1_U1_PLD_IT4, 0x40010290
.set CYDEV_UCFG_B0_P1_U1_PLD_IT5, 0x40010294
.set CYDEV_UCFG_B0_P1_U1_PLD_IT6, 0x40010298
.set CYDEV_UCFG_B0_P1_U1_PLD_IT7, 0x4001029c
.set CYDEV_UCFG_B0_P1_U1_PLD_IT8, 0x400102a0
.set CYDEV_UCFG_B0_P1_U1_PLD_IT9, 0x400102a4
.set CYDEV_UCFG_B0_P1_U1_PLD_IT10, 0x400102a8
.set CYDEV_UCFG_B0_P1_U1_PLD_IT11, 0x400102ac
.set CYDEV_UCFG_B0_P1_U1_PLD_ORT0, 0x400102b0
.set CYDEV_UCFG_B0_P1_U1_PLD_ORT1, 0x400102b2
.set CYDEV_UCFG_B0_P1_U1_PLD_ORT2, 0x400102b4
.set CYDEV_UCFG_B0_P1_U1_PLD_ORT3, 0x400102b6
.set CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST, 0x400102b8
.set CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB, 0x400102ba
.set CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET, 0x400102bc
.set CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS, 0x400102be
.set CYDEV_UCFG_B0_P1_U1_CFG0, 0x400102c0
.set CYDEV_UCFG_B0_P1_U1_CFG1, 0x400102c1
.set CYDEV_UCFG_B0_P1_U1_CFG2, 0x400102c2
.set CYDEV_UCFG_B0_P1_U1_CFG3, 0x400102c3
.set CYDEV_UCFG_B0_P1_U1_CFG4, 0x400102c4
.set CYDEV_UCFG_B0_P1_U1_CFG5, 0x400102c5
.set CYDEV_UCFG_B0_P1_U1_CFG6, 0x400102c6
.set CYDEV_UCFG_B0_P1_U1_CFG7, 0x400102c7
.set CYDEV_UCFG_B0_P1_U1_CFG8, 0x400102c8
.set CYDEV_UCFG_B0_P1_U1_CFG9, 0x400102c9
.set CYDEV_UCFG_B0_P1_U1_CFG10, 0x400102ca
.set CYDEV_UCFG_B0_P1_U1_CFG11, 0x400102cb
.set CYDEV_UCFG_B0_P1_U1_CFG12, 0x400102cc
.set CYDEV_UCFG_B0_P1_U1_CFG13, 0x400102cd
.set CYDEV_UCFG_B0_P1_U1_CFG14, 0x400102ce
.set CYDEV_UCFG_B0_P1_U1_CFG15, 0x400102cf
.set CYDEV_UCFG_B0_P1_U1_CFG16, 0x400102d0
.set CYDEV_UCFG_B0_P1_U1_CFG17, 0x400102d1
.set CYDEV_UCFG_B0_P1_U1_CFG18, 0x400102d2
.set CYDEV_UCFG_B0_P1_U1_CFG19, 0x400102d3
.set CYDEV_UCFG_B0_P1_U1_CFG20, 0x400102d4
.set CYDEV_UCFG_B0_P1_U1_CFG21, 0x400102d5
.set CYDEV_UCFG_B0_P1_U1_CFG22, 0x400102d6
.set CYDEV_UCFG_B0_P1_U1_CFG23, 0x400102d7
.set CYDEV_UCFG_B0_P1_U1_CFG24, 0x400102d8
.set CYDEV_UCFG_B0_P1_U1_CFG25, 0x400102d9
.set CYDEV_UCFG_B0_P1_U1_CFG26, 0x400102da
.set CYDEV_UCFG_B0_P1_U1_CFG27, 0x400102db
.set CYDEV_UCFG_B0_P1_U1_CFG28, 0x400102dc
.set CYDEV_UCFG_B0_P1_U1_CFG29, 0x400102dd
.set CYDEV_UCFG_B0_P1_U1_CFG30, 0x400102de
.set CYDEV_UCFG_B0_P1_U1_CFG31, 0x400102df
.set CYDEV_UCFG_B0_P1_U1_DCFG0, 0x400102e0
.set CYDEV_UCFG_B0_P1_U1_DCFG1, 0x400102e2
.set CYDEV_UCFG_B0_P1_U1_DCFG2, 0x400102e4
.set CYDEV_UCFG_B0_P1_U1_DCFG3, 0x400102e6
.set CYDEV_UCFG_B0_P1_U1_DCFG4, 0x400102e8
.set CYDEV_UCFG_B0_P1_U1_DCFG5, 0x400102ea
.set CYDEV_UCFG_B0_P1_U1_DCFG6, 0x400102ec
.set CYDEV_UCFG_B0_P1_U1_DCFG7, 0x400102ee
.set CYDEV_UCFG_B0_P1_ROUTE_BASE, 0x40010300
.set CYDEV_UCFG_B0_P1_ROUTE_SIZE, 0x000000ef
.set CYDEV_UCFG_B0_P2_BASE, 0x40010400
.set CYDEV_UCFG_B0_P2_SIZE, 0x000001ef
.set CYDEV_UCFG_B0_P2_U0_BASE, 0x40010400
.set CYDEV_UCFG_B0_P2_U0_SIZE, 0x00000070
.set CYDEV_UCFG_B0_P2_U0_PLD_IT0, 0x40010400
.set CYDEV_UCFG_B0_P2_U0_PLD_IT1, 0x40010404
.set CYDEV_UCFG_B0_P2_U0_PLD_IT2, 0x40010408
.set CYDEV_UCFG_B0_P2_U0_PLD_IT3, 0x4001040c
.set CYDEV_UCFG_B0_P2_U0_PLD_IT4, 0x40010410
.set CYDEV_UCFG_B0_P2_U0_PLD_IT5, 0x40010414
.set CYDEV_UCFG_B0_P2_U0_PLD_IT6, 0x40010418
.set CYDEV_UCFG_B0_P2_U0_PLD_IT7, 0x4001041c
.set CYDEV_UCFG_B0_P2_U0_PLD_IT8, 0x40010420
.set CYDEV_UCFG_B0_P2_U0_PLD_IT9, 0x40010424
.set CYDEV_UCFG_B0_P2_U0_PLD_IT10, 0x40010428
.set CYDEV_UCFG_B0_P2_U0_PLD_IT11, 0x4001042c
.set CYDEV_UCFG_B0_P2_U0_PLD_ORT0, 0x40010430
.set CYDEV_UCFG_B0_P2_U0_PLD_ORT1, 0x40010432
.set CYDEV_UCFG_B0_P2_U0_PLD_ORT2, 0x40010434
.set CYDEV_UCFG_B0_P2_U0_PLD_ORT3, 0x40010436
.set CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST, 0x40010438
.set CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB, 0x4001043a
.set CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET, 0x4001043c
.set CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS, 0x4001043e
.set CYDEV_UCFG_B0_P2_U0_CFG0, 0x40010440
.set CYDEV_UCFG_B0_P2_U0_CFG1, 0x40010441
.set CYDEV_UCFG_B0_P2_U0_CFG2, 0x40010442
.set CYDEV_UCFG_B0_P2_U0_CFG3, 0x40010443
.set CYDEV_UCFG_B0_P2_U0_CFG4, 0x40010444
.set CYDEV_UCFG_B0_P2_U0_CFG5, 0x40010445
.set CYDEV_UCFG_B0_P2_U0_CFG6, 0x40010446
.set CYDEV_UCFG_B0_P2_U0_CFG7, 0x40010447
.set CYDEV_UCFG_B0_P2_U0_CFG8, 0x40010448
.set CYDEV_UCFG_B0_P2_U0_CFG9, 0x40010449
.set CYDEV_UCFG_B0_P2_U0_CFG10, 0x4001044a
.set CYDEV_UCFG_B0_P2_U0_CFG11, 0x4001044b
.set CYDEV_UCFG_B0_P2_U0_CFG12, 0x4001044c
.set CYDEV_UCFG_B0_P2_U0_CFG13, 0x4001044d
.set CYDEV_UCFG_B0_P2_U0_CFG14, 0x4001044e
.set CYDEV_UCFG_B0_P2_U0_CFG15, 0x4001044f
.set CYDEV_UCFG_B0_P2_U0_CFG16, 0x40010450
.set CYDEV_UCFG_B0_P2_U0_CFG17, 0x40010451
.set CYDEV_UCFG_B0_P2_U0_CFG18, 0x40010452
.set CYDEV_UCFG_B0_P2_U0_CFG19, 0x40010453
.set CYDEV_UCFG_B0_P2_U0_CFG20, 0x40010454
.set CYDEV_UCFG_B0_P2_U0_CFG21, 0x40010455
.set CYDEV_UCFG_B0_P2_U0_CFG22, 0x40010456
.set CYDEV_UCFG_B0_P2_U0_CFG23, 0x40010457
.set CYDEV_UCFG_B0_P2_U0_CFG24, 0x40010458
.set CYDEV_UCFG_B0_P2_U0_CFG25, 0x40010459
.set CYDEV_UCFG_B0_P2_U0_CFG26, 0x4001045a
.set CYDEV_UCFG_B0_P2_U0_CFG27, 0x4001045b
.set CYDEV_UCFG_B0_P2_U0_CFG28, 0x4001045c
.set CYDEV_UCFG_B0_P2_U0_CFG29, 0x4001045d
.set CYDEV_UCFG_B0_P2_U0_CFG30, 0x4001045e
.set CYDEV_UCFG_B0_P2_U0_CFG31, 0x4001045f
.set CYDEV_UCFG_B0_P2_U0_DCFG0, 0x40010460
.set CYDEV_UCFG_B0_P2_U0_DCFG1, 0x40010462
.set CYDEV_UCFG_B0_P2_U0_DCFG2, 0x40010464
.set CYDEV_UCFG_B0_P2_U0_DCFG3, 0x40010466
.set CYDEV_UCFG_B0_P2_U0_DCFG4, 0x40010468
.set CYDEV_UCFG_B0_P2_U0_DCFG5, 0x4001046a
.set CYDEV_UCFG_B0_P2_U0_DCFG6, 0x4001046c
.set CYDEV_UCFG_B0_P2_U0_DCFG7, 0x4001046e
.set CYDEV_UCFG_B0_P2_U1_BASE, 0x40010480
.set CYDEV_UCFG_B0_P2_U1_SIZE, 0x00000070
.set CYDEV_UCFG_B0_P2_U1_PLD_IT0, 0x40010480
.set CYDEV_UCFG_B0_P2_U1_PLD_IT1, 0x40010484
.set CYDEV_UCFG_B0_P2_U1_PLD_IT2, 0x40010488
.set CYDEV_UCFG_B0_P2_U1_PLD_IT3, 0x4001048c
.set CYDEV_UCFG_B0_P2_U1_PLD_IT4, 0x40010490
.set CYDEV_UCFG_B0_P2_U1_PLD_IT5, 0x40010494
.set CYDEV_UCFG_B0_P2_U1_PLD_IT6, 0x40010498
.set CYDEV_UCFG_B0_P2_U1_PLD_IT7, 0x4001049c
.set CYDEV_UCFG_B0_P2_U1_PLD_IT8, 0x400104a0
.set CYDEV_UCFG_B0_P2_U1_PLD_IT9, 0x400104a4
.set CYDEV_UCFG_B0_P2_U1_PLD_IT10, 0x400104a8
.set CYDEV_UCFG_B0_P2_U1_PLD_IT11, 0x400104ac
.set CYDEV_UCFG_B0_P2_U1_PLD_ORT0, 0x400104b0
.set CYDEV_UCFG_B0_P2_U1_PLD_ORT1, 0x400104b2
.set CYDEV_UCFG_B0_P2_U1_PLD_ORT2, 0x400104b4
.set CYDEV_UCFG_B0_P2_U1_PLD_ORT3, 0x400104b6
.set CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST, 0x400104b8
.set CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB, 0x400104ba
.set CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET, 0x400104bc
.set CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS, 0x400104be
.set CYDEV_UCFG_B0_P2_U1_CFG0, 0x400104c0
.set CYDEV_UCFG_B0_P2_U1_CFG1, 0x400104c1
.set CYDEV_UCFG_B0_P2_U1_CFG2, 0x400104c2
.set CYDEV_UCFG_B0_P2_U1_CFG3, 0x400104c3
.set CYDEV_UCFG_B0_P2_U1_CFG4, 0x400104c4
.set CYDEV_UCFG_B0_P2_U1_CFG5, 0x400104c5
.set CYDEV_UCFG_B0_P2_U1_CFG6, 0x400104c6
.set CYDEV_UCFG_B0_P2_U1_CFG7, 0x400104c7
.set CYDEV_UCFG_B0_P2_U1_CFG8, 0x400104c8
.set CYDEV_UCFG_B0_P2_U1_CFG9, 0x400104c9
.set CYDEV_UCFG_B0_P2_U1_CFG10, 0x400104ca
.set CYDEV_UCFG_B0_P2_U1_CFG11, 0x400104cb
.set CYDEV_UCFG_B0_P2_U1_CFG12, 0x400104cc
.set CYDEV_UCFG_B0_P2_U1_CFG13, 0x400104cd
.set CYDEV_UCFG_B0_P2_U1_CFG14, 0x400104ce
.set CYDEV_UCFG_B0_P2_U1_CFG15, 0x400104cf
.set CYDEV_UCFG_B0_P2_U1_CFG16, 0x400104d0
.set CYDEV_UCFG_B0_P2_U1_CFG17, 0x400104d1
.set CYDEV_UCFG_B0_P2_U1_CFG18, 0x400104d2
.set CYDEV_UCFG_B0_P2_U1_CFG19, 0x400104d3
.set CYDEV_UCFG_B0_P2_U1_CFG20, 0x400104d4
.set CYDEV_UCFG_B0_P2_U1_CFG21, 0x400104d5
.set CYDEV_UCFG_B0_P2_U1_CFG22, 0x400104d6
.set CYDEV_UCFG_B0_P2_U1_CFG23, 0x400104d7
.set CYDEV_UCFG_B0_P2_U1_CFG24, 0x400104d8
.set CYDEV_UCFG_B0_P2_U1_CFG25, 0x400104d9
.set CYDEV_UCFG_B0_P2_U1_CFG26, 0x400104da
.set CYDEV_UCFG_B0_P2_U1_CFG27, 0x400104db
.set CYDEV_UCFG_B0_P2_U1_CFG28, 0x400104dc
.set CYDEV_UCFG_B0_P2_U1_CFG29, 0x400104dd
.set CYDEV_UCFG_B0_P2_U1_CFG30, 0x400104de
.set CYDEV_UCFG_B0_P2_U1_CFG31, 0x400104df
.set CYDEV_UCFG_B0_P2_U1_DCFG0, 0x400104e0
.set CYDEV_UCFG_B0_P2_U1_DCFG1, 0x400104e2
.set CYDEV_UCFG_B0_P2_U1_DCFG2, 0x400104e4
.set CYDEV_UCFG_B0_P2_U1_DCFG3, 0x400104e6
.set CYDEV_UCFG_B0_P2_U1_DCFG4, 0x400104e8
.set CYDEV_UCFG_B0_P2_U1_DCFG5, 0x400104ea
.set CYDEV_UCFG_B0_P2_U1_DCFG6, 0x400104ec
.set CYDEV_UCFG_B0_P2_U1_DCFG7, 0x400104ee
.set CYDEV_UCFG_B0_P2_ROUTE_BASE, 0x40010500
.set CYDEV_UCFG_B0_P2_ROUTE_SIZE, 0x000000ef
.set CYDEV_UCFG_B0_P3_BASE, 0x40010600
.set CYDEV_UCFG_B0_P3_SIZE, 0x000001ef
.set CYDEV_UCFG_B0_P3_U0_BASE, 0x40010600
.set CYDEV_UCFG_B0_P3_U0_SIZE, 0x00000070
.set CYDEV_UCFG_B0_P3_U0_PLD_IT0, 0x40010600
.set CYDEV_UCFG_B0_P3_U0_PLD_IT1, 0x40010604
.set CYDEV_UCFG_B0_P3_U0_PLD_IT2, 0x40010608
.set CYDEV_UCFG_B0_P3_U0_PLD_IT3, 0x4001060c
.set CYDEV_UCFG_B0_P3_U0_PLD_IT4, 0x40010610
.set CYDEV_UCFG_B0_P3_U0_PLD_IT5, 0x40010614
.set CYDEV_UCFG_B0_P3_U0_PLD_IT6, 0x40010618
.set CYDEV_UCFG_B0_P3_U0_PLD_IT7, 0x4001061c
.set CYDEV_UCFG_B0_P3_U0_PLD_IT8, 0x40010620
.set CYDEV_UCFG_B0_P3_U0_PLD_IT9, 0x40010624
.set CYDEV_UCFG_B0_P3_U0_PLD_IT10, 0x40010628
.set CYDEV_UCFG_B0_P3_U0_PLD_IT11, 0x4001062c
.set CYDEV_UCFG_B0_P3_U0_PLD_ORT0, 0x40010630
.set CYDEV_UCFG_B0_P3_U0_PLD_ORT1, 0x40010632
.set CYDEV_UCFG_B0_P3_U0_PLD_ORT2, 0x40010634
.set CYDEV_UCFG_B0_P3_U0_PLD_ORT3, 0x40010636
.set CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST, 0x40010638
.set CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB, 0x4001063a
.set CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET, 0x4001063c
.set CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS, 0x4001063e
.set CYDEV_UCFG_B0_P3_U0_CFG0, 0x40010640
.set CYDEV_UCFG_B0_P3_U0_CFG1, 0x40010641
.set CYDEV_UCFG_B0_P3_U0_CFG2, 0x40010642
.set CYDEV_UCFG_B0_P3_U0_CFG3, 0x40010643
.set CYDEV_UCFG_B0_P3_U0_CFG4, 0x40010644
.set CYDEV_UCFG_B0_P3_U0_CFG5, 0x40010645
.set CYDEV_UCFG_B0_P3_U0_CFG6, 0x40010646
.set CYDEV_UCFG_B0_P3_U0_CFG7, 0x40010647
.set CYDEV_UCFG_B0_P3_U0_CFG8, 0x40010648
.set CYDEV_UCFG_B0_P3_U0_CFG9, 0x40010649
.set CYDEV_UCFG_B0_P3_U0_CFG10, 0x4001064a
.set CYDEV_UCFG_B0_P3_U0_CFG11, 0x4001064b
.set CYDEV_UCFG_B0_P3_U0_CFG12, 0x4001064c
.set CYDEV_UCFG_B0_P3_U0_CFG13, 0x4001064d
.set CYDEV_UCFG_B0_P3_U0_CFG14, 0x4001064e
.set CYDEV_UCFG_B0_P3_U0_CFG15, 0x4001064f
.set CYDEV_UCFG_B0_P3_U0_CFG16, 0x40010650
.set CYDEV_UCFG_B0_P3_U0_CFG17, 0x40010651
.set CYDEV_UCFG_B0_P3_U0_CFG18, 0x40010652
.set CYDEV_UCFG_B0_P3_U0_CFG19, 0x40010653
.set CYDEV_UCFG_B0_P3_U0_CFG20, 0x40010654
.set CYDEV_UCFG_B0_P3_U0_CFG21, 0x40010655
.set CYDEV_UCFG_B0_P3_U0_CFG22, 0x40010656
.set CYDEV_UCFG_B0_P3_U0_CFG23, 0x40010657
.set CYDEV_UCFG_B0_P3_U0_CFG24, 0x40010658
.set CYDEV_UCFG_B0_P3_U0_CFG25, 0x40010659
.set CYDEV_UCFG_B0_P3_U0_CFG26, 0x4001065a
.set CYDEV_UCFG_B0_P3_U0_CFG27, 0x4001065b
.set CYDEV_UCFG_B0_P3_U0_CFG28, 0x4001065c
.set CYDEV_UCFG_B0_P3_U0_CFG29, 0x4001065d
.set CYDEV_UCFG_B0_P3_U0_CFG30, 0x4001065e
.set CYDEV_UCFG_B0_P3_U0_CFG31, 0x4001065f
.set CYDEV_UCFG_B0_P3_U0_DCFG0, 0x40010660
.set CYDEV_UCFG_B0_P3_U0_DCFG1, 0x40010662
.set CYDEV_UCFG_B0_P3_U0_DCFG2, 0x40010664
.set CYDEV_UCFG_B0_P3_U0_DCFG3, 0x40010666
.set CYDEV_UCFG_B0_P3_U0_DCFG4, 0x40010668
.set CYDEV_UCFG_B0_P3_U0_DCFG5, 0x4001066a
.set CYDEV_UCFG_B0_P3_U0_DCFG6, 0x4001066c
.set CYDEV_UCFG_B0_P3_U0_DCFG7, 0x4001066e
.set CYDEV_UCFG_B0_P3_U1_BASE, 0x40010680
.set CYDEV_UCFG_B0_P3_U1_SIZE, 0x00000070
.set CYDEV_UCFG_B0_P3_U1_PLD_IT0, 0x40010680
.set CYDEV_UCFG_B0_P3_U1_PLD_IT1, 0x40010684
.set CYDEV_UCFG_B0_P3_U1_PLD_IT2, 0x40010688
.set CYDEV_UCFG_B0_P3_U1_PLD_IT3, 0x4001068c
.set CYDEV_UCFG_B0_P3_U1_PLD_IT4, 0x40010690
.set CYDEV_UCFG_B0_P3_U1_PLD_IT5, 0x40010694
.set CYDEV_UCFG_B0_P3_U1_PLD_IT6, 0x40010698
.set CYDEV_UCFG_B0_P3_U1_PLD_IT7, 0x4001069c
.set CYDEV_UCFG_B0_P3_U1_PLD_IT8, 0x400106a0
.set CYDEV_UCFG_B0_P3_U1_PLD_IT9, 0x400106a4
.set CYDEV_UCFG_B0_P3_U1_PLD_IT10, 0x400106a8
.set CYDEV_UCFG_B0_P3_U1_PLD_IT11, 0x400106ac
.set CYDEV_UCFG_B0_P3_U1_PLD_ORT0, 0x400106b0
.set CYDEV_UCFG_B0_P3_U1_PLD_ORT1, 0x400106b2
.set CYDEV_UCFG_B0_P3_U1_PLD_ORT2, 0x400106b4
.set CYDEV_UCFG_B0_P3_U1_PLD_ORT3, 0x400106b6
.set CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST, 0x400106b8
.set CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB, 0x400106ba
.set CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET, 0x400106bc
.set CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS, 0x400106be
.set CYDEV_UCFG_B0_P3_U1_CFG0, 0x400106c0
.set CYDEV_UCFG_B0_P3_U1_CFG1, 0x400106c1
.set CYDEV_UCFG_B0_P3_U1_CFG2, 0x400106c2
.set CYDEV_UCFG_B0_P3_U1_CFG3, 0x400106c3
.set CYDEV_UCFG_B0_P3_U1_CFG4, 0x400106c4
.set CYDEV_UCFG_B0_P3_U1_CFG5, 0x400106c5
.set CYDEV_UCFG_B0_P3_U1_CFG6, 0x400106c6
.set CYDEV_UCFG_B0_P3_U1_CFG7, 0x400106c7
.set CYDEV_UCFG_B0_P3_U1_CFG8, 0x400106c8
.set CYDEV_UCFG_B0_P3_U1_CFG9, 0x400106c9
.set CYDEV_UCFG_B0_P3_U1_CFG10, 0x400106ca
.set CYDEV_UCFG_B0_P3_U1_CFG11, 0x400106cb
.set CYDEV_UCFG_B0_P3_U1_CFG12, 0x400106cc
.set CYDEV_UCFG_B0_P3_U1_CFG13, 0x400106cd
.set CYDEV_UCFG_B0_P3_U1_CFG14, 0x400106ce
.set CYDEV_UCFG_B0_P3_U1_CFG15, 0x400106cf
.set CYDEV_UCFG_B0_P3_U1_CFG16, 0x400106d0
.set CYDEV_UCFG_B0_P3_U1_CFG17, 0x400106d1
.set CYDEV_UCFG_B0_P3_U1_CFG18, 0x400106d2
.set CYDEV_UCFG_B0_P3_U1_CFG19, 0x400106d3
.set CYDEV_UCFG_B0_P3_U1_CFG20, 0x400106d4
.set CYDEV_UCFG_B0_P3_U1_CFG21, 0x400106d5
.set CYDEV_UCFG_B0_P3_U1_CFG22, 0x400106d6
.set CYDEV_UCFG_B0_P3_U1_CFG23, 0x400106d7
.set CYDEV_UCFG_B0_P3_U1_CFG24, 0x400106d8
.set CYDEV_UCFG_B0_P3_U1_CFG25, 0x400106d9
.set CYDEV_UCFG_B0_P3_U1_CFG26, 0x400106da
.set CYDEV_UCFG_B0_P3_U1_CFG27, 0x400106db
.set CYDEV_UCFG_B0_P3_U1_CFG28, 0x400106dc
.set CYDEV_UCFG_B0_P3_U1_CFG29, 0x400106dd
.set CYDEV_UCFG_B0_P3_U1_CFG30, 0x400106de
.set CYDEV_UCFG_B0_P3_U1_CFG31, 0x400106df
.set CYDEV_UCFG_B0_P3_U1_DCFG0, 0x400106e0
.set CYDEV_UCFG_B0_P3_U1_DCFG1, 0x400106e2
.set CYDEV_UCFG_B0_P3_U1_DCFG2, 0x400106e4
.set CYDEV_UCFG_B0_P3_U1_DCFG3, 0x400106e6
.set CYDEV_UCFG_B0_P3_U1_DCFG4, 0x400106e8
.set CYDEV_UCFG_B0_P3_U1_DCFG5, 0x400106ea
.set CYDEV_UCFG_B0_P3_U1_DCFG6, 0x400106ec
.set CYDEV_UCFG_B0_P3_U1_DCFG7, 0x400106ee
.set CYDEV_UCFG_B0_P3_ROUTE_BASE, 0x40010700
.set CYDEV_UCFG_B0_P3_ROUTE_SIZE, 0x000000ef
.set CYDEV_UCFG_B0_P4_BASE, 0x40010800
.set CYDEV_UCFG_B0_P4_SIZE, 0x000001ef
.set CYDEV_UCFG_B0_P4_U0_BASE, 0x40010800
.set CYDEV_UCFG_B0_P4_U0_SIZE, 0x00000070
.set CYDEV_UCFG_B0_P4_U0_PLD_IT0, 0x40010800
.set CYDEV_UCFG_B0_P4_U0_PLD_IT1, 0x40010804
.set CYDEV_UCFG_B0_P4_U0_PLD_IT2, 0x40010808
.set CYDEV_UCFG_B0_P4_U0_PLD_IT3, 0x4001080c
.set CYDEV_UCFG_B0_P4_U0_PLD_IT4, 0x40010810
.set CYDEV_UCFG_B0_P4_U0_PLD_IT5, 0x40010814
.set CYDEV_UCFG_B0_P4_U0_PLD_IT6, 0x40010818
.set CYDEV_UCFG_B0_P4_U0_PLD_IT7, 0x4001081c
.set CYDEV_UCFG_B0_P4_U0_PLD_IT8, 0x40010820
.set CYDEV_UCFG_B0_P4_U0_PLD_IT9, 0x40010824
.set CYDEV_UCFG_B0_P4_U0_PLD_IT10, 0x40010828
.set CYDEV_UCFG_B0_P4_U0_PLD_IT11, 0x4001082c
.set CYDEV_UCFG_B0_P4_U0_PLD_ORT0, 0x40010830
.set CYDEV_UCFG_B0_P4_U0_PLD_ORT1, 0x40010832
.set CYDEV_UCFG_B0_P4_U0_PLD_ORT2, 0x40010834
.set CYDEV_UCFG_B0_P4_U0_PLD_ORT3, 0x40010836
.set CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST, 0x40010838
.set CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB, 0x4001083a
.set CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET, 0x4001083c
.set CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS, 0x4001083e
.set CYDEV_UCFG_B0_P4_U0_CFG0, 0x40010840
.set CYDEV_UCFG_B0_P4_U0_CFG1, 0x40010841
.set CYDEV_UCFG_B0_P4_U0_CFG2, 0x40010842
.set CYDEV_UCFG_B0_P4_U0_CFG3, 0x40010843
.set CYDEV_UCFG_B0_P4_U0_CFG4, 0x40010844
.set CYDEV_UCFG_B0_P4_U0_CFG5, 0x40010845
.set CYDEV_UCFG_B0_P4_U0_CFG6, 0x40010846
.set CYDEV_UCFG_B0_P4_U0_CFG7, 0x40010847
.set CYDEV_UCFG_B0_P4_U0_CFG8, 0x40010848
.set CYDEV_UCFG_B0_P4_U0_CFG9, 0x40010849
.set CYDEV_UCFG_B0_P4_U0_CFG10, 0x4001084a
.set CYDEV_UCFG_B0_P4_U0_CFG11, 0x4001084b
.set CYDEV_UCFG_B0_P4_U0_CFG12, 0x4001084c
.set CYDEV_UCFG_B0_P4_U0_CFG13, 0x4001084d
.set CYDEV_UCFG_B0_P4_U0_CFG14, 0x4001084e
.set CYDEV_UCFG_B0_P4_U0_CFG15, 0x4001084f
.set CYDEV_UCFG_B0_P4_U0_CFG16, 0x40010850
.set CYDEV_UCFG_B0_P4_U0_CFG17, 0x40010851
.set CYDEV_UCFG_B0_P4_U0_CFG18, 0x40010852
.set CYDEV_UCFG_B0_P4_U0_CFG19, 0x40010853
.set CYDEV_UCFG_B0_P4_U0_CFG20, 0x40010854
.set CYDEV_UCFG_B0_P4_U0_CFG21, 0x40010855
.set CYDEV_UCFG_B0_P4_U0_CFG22, 0x40010856
.set CYDEV_UCFG_B0_P4_U0_CFG23, 0x40010857
.set CYDEV_UCFG_B0_P4_U0_CFG24, 0x40010858
.set CYDEV_UCFG_B0_P4_U0_CFG25, 0x40010859
.set CYDEV_UCFG_B0_P4_U0_CFG26, 0x4001085a
.set CYDEV_UCFG_B0_P4_U0_CFG27, 0x4001085b
.set CYDEV_UCFG_B0_P4_U0_CFG28, 0x4001085c
.set CYDEV_UCFG_B0_P4_U0_CFG29, 0x4001085d
.set CYDEV_UCFG_B0_P4_U0_CFG30, 0x4001085e
.set CYDEV_UCFG_B0_P4_U0_CFG31, 0x4001085f
.set CYDEV_UCFG_B0_P4_U0_DCFG0, 0x40010860
.set CYDEV_UCFG_B0_P4_U0_DCFG1, 0x40010862
.set CYDEV_UCFG_B0_P4_U0_DCFG2, 0x40010864
.set CYDEV_UCFG_B0_P4_U0_DCFG3, 0x40010866
.set CYDEV_UCFG_B0_P4_U0_DCFG4, 0x40010868
.set CYDEV_UCFG_B0_P4_U0_DCFG5, 0x4001086a
.set CYDEV_UCFG_B0_P4_U0_DCFG6, 0x4001086c
.set CYDEV_UCFG_B0_P4_U0_DCFG7, 0x4001086e
.set CYDEV_UCFG_B0_P4_U1_BASE, 0x40010880
.set CYDEV_UCFG_B0_P4_U1_SIZE, 0x00000070
.set CYDEV_UCFG_B0_P4_U1_PLD_IT0, 0x40010880
.set CYDEV_UCFG_B0_P4_U1_PLD_IT1, 0x40010884
.set CYDEV_UCFG_B0_P4_U1_PLD_IT2, 0x40010888
.set CYDEV_UCFG_B0_P4_U1_PLD_IT3, 0x4001088c
.set CYDEV_UCFG_B0_P4_U1_PLD_IT4, 0x40010890
.set CYDEV_UCFG_B0_P4_U1_PLD_IT5, 0x40010894
.set CYDEV_UCFG_B0_P4_U1_PLD_IT6, 0x40010898
.set CYDEV_UCFG_B0_P4_U1_PLD_IT7, 0x4001089c
.set CYDEV_UCFG_B0_P4_U1_PLD_IT8, 0x400108a0
.set CYDEV_UCFG_B0_P4_U1_PLD_IT9, 0x400108a4
.set CYDEV_UCFG_B0_P4_U1_PLD_IT10, 0x400108a8
.set CYDEV_UCFG_B0_P4_U1_PLD_IT11, 0x400108ac
.set CYDEV_UCFG_B0_P4_U1_PLD_ORT0, 0x400108b0
.set CYDEV_UCFG_B0_P4_U1_PLD_ORT1, 0x400108b2
.set CYDEV_UCFG_B0_P4_U1_PLD_ORT2, 0x400108b4
.set CYDEV_UCFG_B0_P4_U1_PLD_ORT3, 0x400108b6
.set CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST, 0x400108b8
.set CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB, 0x400108ba
.set CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET, 0x400108bc
.set CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS, 0x400108be
.set CYDEV_UCFG_B0_P4_U1_CFG0, 0x400108c0
.set CYDEV_UCFG_B0_P4_U1_CFG1, 0x400108c1
.set CYDEV_UCFG_B0_P4_U1_CFG2, 0x400108c2
.set CYDEV_UCFG_B0_P4_U1_CFG3, 0x400108c3
.set CYDEV_UCFG_B0_P4_U1_CFG4, 0x400108c4
.set CYDEV_UCFG_B0_P4_U1_CFG5, 0x400108c5
.set CYDEV_UCFG_B0_P4_U1_CFG6, 0x400108c6
.set CYDEV_UCFG_B0_P4_U1_CFG7, 0x400108c7
.set CYDEV_UCFG_B0_P4_U1_CFG8, 0x400108c8
.set CYDEV_UCFG_B0_P4_U1_CFG9, 0x400108c9
.set CYDEV_UCFG_B0_P4_U1_CFG10, 0x400108ca
.set CYDEV_UCFG_B0_P4_U1_CFG11, 0x400108cb
.set CYDEV_UCFG_B0_P4_U1_CFG12, 0x400108cc
.set CYDEV_UCFG_B0_P4_U1_CFG13, 0x400108cd
.set CYDEV_UCFG_B0_P4_U1_CFG14, 0x400108ce
.set CYDEV_UCFG_B0_P4_U1_CFG15, 0x400108cf
.set CYDEV_UCFG_B0_P4_U1_CFG16, 0x400108d0
.set CYDEV_UCFG_B0_P4_U1_CFG17, 0x400108d1
.set CYDEV_UCFG_B0_P4_U1_CFG18, 0x400108d2
.set CYDEV_UCFG_B0_P4_U1_CFG19, 0x400108d3
.set CYDEV_UCFG_B0_P4_U1_CFG20, 0x400108d4
.set CYDEV_UCFG_B0_P4_U1_CFG21, 0x400108d5
.set CYDEV_UCFG_B0_P4_U1_CFG22, 0x400108d6
.set CYDEV_UCFG_B0_P4_U1_CFG23, 0x400108d7
.set CYDEV_UCFG_B0_P4_U1_CFG24, 0x400108d8
.set CYDEV_UCFG_B0_P4_U1_CFG25, 0x400108d9
.set CYDEV_UCFG_B0_P4_U1_CFG26, 0x400108da
.set CYDEV_UCFG_B0_P4_U1_CFG27, 0x400108db
.set CYDEV_UCFG_B0_P4_U1_CFG28, 0x400108dc
.set CYDEV_UCFG_B0_P4_U1_CFG29, 0x400108dd
.set CYDEV_UCFG_B0_P4_U1_CFG30, 0x400108de
.set CYDEV_UCFG_B0_P4_U1_CFG31, 0x400108df
.set CYDEV_UCFG_B0_P4_U1_DCFG0, 0x400108e0
.set CYDEV_UCFG_B0_P4_U1_DCFG1, 0x400108e2
.set CYDEV_UCFG_B0_P4_U1_DCFG2, 0x400108e4
.set CYDEV_UCFG_B0_P4_U1_DCFG3, 0x400108e6
.set CYDEV_UCFG_B0_P4_U1_DCFG4, 0x400108e8
.set CYDEV_UCFG_B0_P4_U1_DCFG5, 0x400108ea
.set CYDEV_UCFG_B0_P4_U1_DCFG6, 0x400108ec
.set CYDEV_UCFG_B0_P4_U1_DCFG7, 0x400108ee
.set CYDEV_UCFG_B0_P4_ROUTE_BASE, 0x40010900
.set CYDEV_UCFG_B0_P4_ROUTE_SIZE, 0x000000ef
.set CYDEV_UCFG_B0_P5_BASE, 0x40010a00
.set CYDEV_UCFG_B0_P5_SIZE, 0x000001ef
.set CYDEV_UCFG_B0_P5_U0_BASE, 0x40010a00
.set CYDEV_UCFG_B0_P5_U0_SIZE, 0x00000070
.set CYDEV_UCFG_B0_P5_U0_PLD_IT0, 0x40010a00
.set CYDEV_UCFG_B0_P5_U0_PLD_IT1, 0x40010a04
.set CYDEV_UCFG_B0_P5_U0_PLD_IT2, 0x40010a08
.set CYDEV_UCFG_B0_P5_U0_PLD_IT3, 0x40010a0c
.set CYDEV_UCFG_B0_P5_U0_PLD_IT4, 0x40010a10
.set CYDEV_UCFG_B0_P5_U0_PLD_IT5, 0x40010a14
.set CYDEV_UCFG_B0_P5_U0_PLD_IT6, 0x40010a18
.set CYDEV_UCFG_B0_P5_U0_PLD_IT7, 0x40010a1c
.set CYDEV_UCFG_B0_P5_U0_PLD_IT8, 0x40010a20
.set CYDEV_UCFG_B0_P5_U0_PLD_IT9, 0x40010a24
.set CYDEV_UCFG_B0_P5_U0_PLD_IT10, 0x40010a28
.set CYDEV_UCFG_B0_P5_U0_PLD_IT11, 0x40010a2c
.set CYDEV_UCFG_B0_P5_U0_PLD_ORT0, 0x40010a30
.set CYDEV_UCFG_B0_P5_U0_PLD_ORT1, 0x40010a32
.set CYDEV_UCFG_B0_P5_U0_PLD_ORT2, 0x40010a34
.set CYDEV_UCFG_B0_P5_U0_PLD_ORT3, 0x40010a36
.set CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST, 0x40010a38
.set CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB, 0x40010a3a
.set CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET, 0x40010a3c
.set CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS, 0x40010a3e
.set CYDEV_UCFG_B0_P5_U0_CFG0, 0x40010a40
.set CYDEV_UCFG_B0_P5_U0_CFG1, 0x40010a41
.set CYDEV_UCFG_B0_P5_U0_CFG2, 0x40010a42
.set CYDEV_UCFG_B0_P5_U0_CFG3, 0x40010a43
.set CYDEV_UCFG_B0_P5_U0_CFG4, 0x40010a44
.set CYDEV_UCFG_B0_P5_U0_CFG5, 0x40010a45
.set CYDEV_UCFG_B0_P5_U0_CFG6, 0x40010a46
.set CYDEV_UCFG_B0_P5_U0_CFG7, 0x40010a47
.set CYDEV_UCFG_B0_P5_U0_CFG8, 0x40010a48
.set CYDEV_UCFG_B0_P5_U0_CFG9, 0x40010a49
.set CYDEV_UCFG_B0_P5_U0_CFG10, 0x40010a4a
.set CYDEV_UCFG_B0_P5_U0_CFG11, 0x40010a4b
.set CYDEV_UCFG_B0_P5_U0_CFG12, 0x40010a4c
.set CYDEV_UCFG_B0_P5_U0_CFG13, 0x40010a4d
.set CYDEV_UCFG_B0_P5_U0_CFG14, 0x40010a4e
.set CYDEV_UCFG_B0_P5_U0_CFG15, 0x40010a4f
.set CYDEV_UCFG_B0_P5_U0_CFG16, 0x40010a50
.set CYDEV_UCFG_B0_P5_U0_CFG17, 0x40010a51
.set CYDEV_UCFG_B0_P5_U0_CFG18, 0x40010a52
.set CYDEV_UCFG_B0_P5_U0_CFG19, 0x40010a53
.set CYDEV_UCFG_B0_P5_U0_CFG20, 0x40010a54
.set CYDEV_UCFG_B0_P5_U0_CFG21, 0x40010a55
.set CYDEV_UCFG_B0_P5_U0_CFG22, 0x40010a56
.set CYDEV_UCFG_B0_P5_U0_CFG23, 0x40010a57
.set CYDEV_UCFG_B0_P5_U0_CFG24, 0x40010a58
.set CYDEV_UCFG_B0_P5_U0_CFG25, 0x40010a59
.set CYDEV_UCFG_B0_P5_U0_CFG26, 0x40010a5a
.set CYDEV_UCFG_B0_P5_U0_CFG27, 0x40010a5b
.set CYDEV_UCFG_B0_P5_U0_CFG28, 0x40010a5c
.set CYDEV_UCFG_B0_P5_U0_CFG29, 0x40010a5d
.set CYDEV_UCFG_B0_P5_U0_CFG30, 0x40010a5e
.set CYDEV_UCFG_B0_P5_U0_CFG31, 0x40010a5f
.set CYDEV_UCFG_B0_P5_U0_DCFG0, 0x40010a60
.set CYDEV_UCFG_B0_P5_U0_DCFG1, 0x40010a62
.set CYDEV_UCFG_B0_P5_U0_DCFG2, 0x40010a64
.set CYDEV_UCFG_B0_P5_U0_DCFG3, 0x40010a66
.set CYDEV_UCFG_B0_P5_U0_DCFG4, 0x40010a68
.set CYDEV_UCFG_B0_P5_U0_DCFG5, 0x40010a6a
.set CYDEV_UCFG_B0_P5_U0_DCFG6, 0x40010a6c
.set CYDEV_UCFG_B0_P5_U0_DCFG7, 0x40010a6e
.set CYDEV_UCFG_B0_P5_U1_BASE, 0x40010a80
.set CYDEV_UCFG_B0_P5_U1_SIZE, 0x00000070
.set CYDEV_UCFG_B0_P5_U1_PLD_IT0, 0x40010a80
.set CYDEV_UCFG_B0_P5_U1_PLD_IT1, 0x40010a84
.set CYDEV_UCFG_B0_P5_U1_PLD_IT2, 0x40010a88
.set CYDEV_UCFG_B0_P5_U1_PLD_IT3, 0x40010a8c
.set CYDEV_UCFG_B0_P5_U1_PLD_IT4, 0x40010a90
.set CYDEV_UCFG_B0_P5_U1_PLD_IT5, 0x40010a94
.set CYDEV_UCFG_B0_P5_U1_PLD_IT6, 0x40010a98
.set CYDEV_UCFG_B0_P5_U1_PLD_IT7, 0x40010a9c
.set CYDEV_UCFG_B0_P5_U1_PLD_IT8, 0x40010aa0
.set CYDEV_UCFG_B0_P5_U1_PLD_IT9, 0x40010aa4
.set CYDEV_UCFG_B0_P5_U1_PLD_IT10, 0x40010aa8
.set CYDEV_UCFG_B0_P5_U1_PLD_IT11, 0x40010aac
.set CYDEV_UCFG_B0_P5_U1_PLD_ORT0, 0x40010ab0
.set CYDEV_UCFG_B0_P5_U1_PLD_ORT1, 0x40010ab2
.set CYDEV_UCFG_B0_P5_U1_PLD_ORT2, 0x40010ab4
.set CYDEV_UCFG_B0_P5_U1_PLD_ORT3, 0x40010ab6
.set CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST, 0x40010ab8
.set CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB, 0x40010aba
.set CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET, 0x40010abc
.set CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS, 0x40010abe
.set CYDEV_UCFG_B0_P5_U1_CFG0, 0x40010ac0
.set CYDEV_UCFG_B0_P5_U1_CFG1, 0x40010ac1
.set CYDEV_UCFG_B0_P5_U1_CFG2, 0x40010ac2
.set CYDEV_UCFG_B0_P5_U1_CFG3, 0x40010ac3
.set CYDEV_UCFG_B0_P5_U1_CFG4, 0x40010ac4
.set CYDEV_UCFG_B0_P5_U1_CFG5, 0x40010ac5
.set CYDEV_UCFG_B0_P5_U1_CFG6, 0x40010ac6
.set CYDEV_UCFG_B0_P5_U1_CFG7, 0x40010ac7
.set CYDEV_UCFG_B0_P5_U1_CFG8, 0x40010ac8
.set CYDEV_UCFG_B0_P5_U1_CFG9, 0x40010ac9
.set CYDEV_UCFG_B0_P5_U1_CFG10, 0x40010aca
.set CYDEV_UCFG_B0_P5_U1_CFG11, 0x40010acb
.set CYDEV_UCFG_B0_P5_U1_CFG12, 0x40010acc
.set CYDEV_UCFG_B0_P5_U1_CFG13, 0x40010acd
.set CYDEV_UCFG_B0_P5_U1_CFG14, 0x40010ace
.set CYDEV_UCFG_B0_P5_U1_CFG15, 0x40010acf
.set CYDEV_UCFG_B0_P5_U1_CFG16, 0x40010ad0
.set CYDEV_UCFG_B0_P5_U1_CFG17, 0x40010ad1
.set CYDEV_UCFG_B0_P5_U1_CFG18, 0x40010ad2
.set CYDEV_UCFG_B0_P5_U1_CFG19, 0x40010ad3
.set CYDEV_UCFG_B0_P5_U1_CFG20, 0x40010ad4
.set CYDEV_UCFG_B0_P5_U1_CFG21, 0x40010ad5
.set CYDEV_UCFG_B0_P5_U1_CFG22, 0x40010ad6
.set CYDEV_UCFG_B0_P5_U1_CFG23, 0x40010ad7
.set CYDEV_UCFG_B0_P5_U1_CFG24, 0x40010ad8
.set CYDEV_UCFG_B0_P5_U1_CFG25, 0x40010ad9
.set CYDEV_UCFG_B0_P5_U1_CFG26, 0x40010ada
.set CYDEV_UCFG_B0_P5_U1_CFG27, 0x40010adb
.set CYDEV_UCFG_B0_P5_U1_CFG28, 0x40010adc
.set CYDEV_UCFG_B0_P5_U1_CFG29, 0x40010add
.set CYDEV_UCFG_B0_P5_U1_CFG30, 0x40010ade
.set CYDEV_UCFG_B0_P5_U1_CFG31, 0x40010adf
.set CYDEV_UCFG_B0_P5_U1_DCFG0, 0x40010ae0
.set CYDEV_UCFG_B0_P5_U1_DCFG1, 0x40010ae2
.set CYDEV_UCFG_B0_P5_U1_DCFG2, 0x40010ae4
.set CYDEV_UCFG_B0_P5_U1_DCFG3, 0x40010ae6
.set CYDEV_UCFG_B0_P5_U1_DCFG4, 0x40010ae8
.set CYDEV_UCFG_B0_P5_U1_DCFG5, 0x40010aea
.set CYDEV_UCFG_B0_P5_U1_DCFG6, 0x40010aec
.set CYDEV_UCFG_B0_P5_U1_DCFG7, 0x40010aee
.set CYDEV_UCFG_B0_P5_ROUTE_BASE, 0x40010b00
.set CYDEV_UCFG_B0_P5_ROUTE_SIZE, 0x000000ef
.set CYDEV_UCFG_B0_P6_BASE, 0x40010c00
.set CYDEV_UCFG_B0_P6_SIZE, 0x000001ef
.set CYDEV_UCFG_B0_P6_U0_BASE, 0x40010c00
.set CYDEV_UCFG_B0_P6_U0_SIZE, 0x00000070
.set CYDEV_UCFG_B0_P6_U0_PLD_IT0, 0x40010c00
.set CYDEV_UCFG_B0_P6_U0_PLD_IT1, 0x40010c04
.set CYDEV_UCFG_B0_P6_U0_PLD_IT2, 0x40010c08
.set CYDEV_UCFG_B0_P6_U0_PLD_IT3, 0x40010c0c
.set CYDEV_UCFG_B0_P6_U0_PLD_IT4, 0x40010c10
.set CYDEV_UCFG_B0_P6_U0_PLD_IT5, 0x40010c14
.set CYDEV_UCFG_B0_P6_U0_PLD_IT6, 0x40010c18
.set CYDEV_UCFG_B0_P6_U0_PLD_IT7, 0x40010c1c
.set CYDEV_UCFG_B0_P6_U0_PLD_IT8, 0x40010c20
.set CYDEV_UCFG_B0_P6_U0_PLD_IT9, 0x40010c24
.set CYDEV_UCFG_B0_P6_U0_PLD_IT10, 0x40010c28
.set CYDEV_UCFG_B0_P6_U0_PLD_IT11, 0x40010c2c
.set CYDEV_UCFG_B0_P6_U0_PLD_ORT0, 0x40010c30
.set CYDEV_UCFG_B0_P6_U0_PLD_ORT1, 0x40010c32
.set CYDEV_UCFG_B0_P6_U0_PLD_ORT2, 0x40010c34
.set CYDEV_UCFG_B0_P6_U0_PLD_ORT3, 0x40010c36
.set CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST, 0x40010c38
.set CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB, 0x40010c3a
.set CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET, 0x40010c3c
.set CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS, 0x40010c3e
.set CYDEV_UCFG_B0_P6_U0_CFG0, 0x40010c40
.set CYDEV_UCFG_B0_P6_U0_CFG1, 0x40010c41
.set CYDEV_UCFG_B0_P6_U0_CFG2, 0x40010c42
.set CYDEV_UCFG_B0_P6_U0_CFG3, 0x40010c43
.set CYDEV_UCFG_B0_P6_U0_CFG4, 0x40010c44
.set CYDEV_UCFG_B0_P6_U0_CFG5, 0x40010c45
.set CYDEV_UCFG_B0_P6_U0_CFG6, 0x40010c46
.set CYDEV_UCFG_B0_P6_U0_CFG7, 0x40010c47
.set CYDEV_UCFG_B0_P6_U0_CFG8, 0x40010c48
.set CYDEV_UCFG_B0_P6_U0_CFG9, 0x40010c49
.set CYDEV_UCFG_B0_P6_U0_CFG10, 0x40010c4a
.set CYDEV_UCFG_B0_P6_U0_CFG11, 0x40010c4b
.set CYDEV_UCFG_B0_P6_U0_CFG12, 0x40010c4c
.set CYDEV_UCFG_B0_P6_U0_CFG13, 0x40010c4d
.set CYDEV_UCFG_B0_P6_U0_CFG14, 0x40010c4e
.set CYDEV_UCFG_B0_P6_U0_CFG15, 0x40010c4f
.set CYDEV_UCFG_B0_P6_U0_CFG16, 0x40010c50
.set CYDEV_UCFG_B0_P6_U0_CFG17, 0x40010c51
.set CYDEV_UCFG_B0_P6_U0_CFG18, 0x40010c52
.set CYDEV_UCFG_B0_P6_U0_CFG19, 0x40010c53
.set CYDEV_UCFG_B0_P6_U0_CFG20, 0x40010c54
.set CYDEV_UCFG_B0_P6_U0_CFG21, 0x40010c55
.set CYDEV_UCFG_B0_P6_U0_CFG22, 0x40010c56
.set CYDEV_UCFG_B0_P6_U0_CFG23, 0x40010c57
.set CYDEV_UCFG_B0_P6_U0_CFG24, 0x40010c58
.set CYDEV_UCFG_B0_P6_U0_CFG25, 0x40010c59
.set CYDEV_UCFG_B0_P6_U0_CFG26, 0x40010c5a
.set CYDEV_UCFG_B0_P6_U0_CFG27, 0x40010c5b
.set CYDEV_UCFG_B0_P6_U0_CFG28, 0x40010c5c
.set CYDEV_UCFG_B0_P6_U0_CFG29, 0x40010c5d
.set CYDEV_UCFG_B0_P6_U0_CFG30, 0x40010c5e
.set CYDEV_UCFG_B0_P6_U0_CFG31, 0x40010c5f
.set CYDEV_UCFG_B0_P6_U0_DCFG0, 0x40010c60
.set CYDEV_UCFG_B0_P6_U0_DCFG1, 0x40010c62
.set CYDEV_UCFG_B0_P6_U0_DCFG2, 0x40010c64
.set CYDEV_UCFG_B0_P6_U0_DCFG3, 0x40010c66
.set CYDEV_UCFG_B0_P6_U0_DCFG4, 0x40010c68
.set CYDEV_UCFG_B0_P6_U0_DCFG5, 0x40010c6a
.set CYDEV_UCFG_B0_P6_U0_DCFG6, 0x40010c6c
.set CYDEV_UCFG_B0_P6_U0_DCFG7, 0x40010c6e
.set CYDEV_UCFG_B0_P6_U1_BASE, 0x40010c80
.set CYDEV_UCFG_B0_P6_U1_SIZE, 0x00000070
.set CYDEV_UCFG_B0_P6_U1_PLD_IT0, 0x40010c80
.set CYDEV_UCFG_B0_P6_U1_PLD_IT1, 0x40010c84
.set CYDEV_UCFG_B0_P6_U1_PLD_IT2, 0x40010c88
.set CYDEV_UCFG_B0_P6_U1_PLD_IT3, 0x40010c8c
.set CYDEV_UCFG_B0_P6_U1_PLD_IT4, 0x40010c90
.set CYDEV_UCFG_B0_P6_U1_PLD_IT5, 0x40010c94
.set CYDEV_UCFG_B0_P6_U1_PLD_IT6, 0x40010c98
.set CYDEV_UCFG_B0_P6_U1_PLD_IT7, 0x40010c9c
.set CYDEV_UCFG_B0_P6_U1_PLD_IT8, 0x40010ca0
.set CYDEV_UCFG_B0_P6_U1_PLD_IT9, 0x40010ca4
.set CYDEV_UCFG_B0_P6_U1_PLD_IT10, 0x40010ca8
.set CYDEV_UCFG_B0_P6_U1_PLD_IT11, 0x40010cac
.set CYDEV_UCFG_B0_P6_U1_PLD_ORT0, 0x40010cb0
.set CYDEV_UCFG_B0_P6_U1_PLD_ORT1, 0x40010cb2
.set CYDEV_UCFG_B0_P6_U1_PLD_ORT2, 0x40010cb4
.set CYDEV_UCFG_B0_P6_U1_PLD_ORT3, 0x40010cb6
.set CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST, 0x40010cb8
.set CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB, 0x40010cba
.set CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET, 0x40010cbc
.set CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS, 0x40010cbe
.set CYDEV_UCFG_B0_P6_U1_CFG0, 0x40010cc0
.set CYDEV_UCFG_B0_P6_U1_CFG1, 0x40010cc1
.set CYDEV_UCFG_B0_P6_U1_CFG2, 0x40010cc2
.set CYDEV_UCFG_B0_P6_U1_CFG3, 0x40010cc3
.set CYDEV_UCFG_B0_P6_U1_CFG4, 0x40010cc4
.set CYDEV_UCFG_B0_P6_U1_CFG5, 0x40010cc5
.set CYDEV_UCFG_B0_P6_U1_CFG6, 0x40010cc6
.set CYDEV_UCFG_B0_P6_U1_CFG7, 0x40010cc7
.set CYDEV_UCFG_B0_P6_U1_CFG8, 0x40010cc8
.set CYDEV_UCFG_B0_P6_U1_CFG9, 0x40010cc9
.set CYDEV_UCFG_B0_P6_U1_CFG10, 0x40010cca
.set CYDEV_UCFG_B0_P6_U1_CFG11, 0x40010ccb
.set CYDEV_UCFG_B0_P6_U1_CFG12, 0x40010ccc
.set CYDEV_UCFG_B0_P6_U1_CFG13, 0x40010ccd
.set CYDEV_UCFG_B0_P6_U1_CFG14, 0x40010cce
.set CYDEV_UCFG_B0_P6_U1_CFG15, 0x40010ccf
.set CYDEV_UCFG_B0_P6_U1_CFG16, 0x40010cd0
.set CYDEV_UCFG_B0_P6_U1_CFG17, 0x40010cd1
.set CYDEV_UCFG_B0_P6_U1_CFG18, 0x40010cd2
.set CYDEV_UCFG_B0_P6_U1_CFG19, 0x40010cd3
.set CYDEV_UCFG_B0_P6_U1_CFG20, 0x40010cd4
.set CYDEV_UCFG_B0_P6_U1_CFG21, 0x40010cd5
.set CYDEV_UCFG_B0_P6_U1_CFG22, 0x40010cd6
.set CYDEV_UCFG_B0_P6_U1_CFG23, 0x40010cd7
.set CYDEV_UCFG_B0_P6_U1_CFG24, 0x40010cd8
.set CYDEV_UCFG_B0_P6_U1_CFG25, 0x40010cd9
.set CYDEV_UCFG_B0_P6_U1_CFG26, 0x40010cda
.set CYDEV_UCFG_B0_P6_U1_CFG27, 0x40010cdb
.set CYDEV_UCFG_B0_P6_U1_CFG28, 0x40010cdc
.set CYDEV_UCFG_B0_P6_U1_CFG29, 0x40010cdd
.set CYDEV_UCFG_B0_P6_U1_CFG30, 0x40010cde
.set CYDEV_UCFG_B0_P6_U1_CFG31, 0x40010cdf
.set CYDEV_UCFG_B0_P6_U1_DCFG0, 0x40010ce0
.set CYDEV_UCFG_B0_P6_U1_DCFG1, 0x40010ce2
.set CYDEV_UCFG_B0_P6_U1_DCFG2, 0x40010ce4
.set CYDEV_UCFG_B0_P6_U1_DCFG3, 0x40010ce6
.set CYDEV_UCFG_B0_P6_U1_DCFG4, 0x40010ce8
.set CYDEV_UCFG_B0_P6_U1_DCFG5, 0x40010cea
.set CYDEV_UCFG_B0_P6_U1_DCFG6, 0x40010cec
.set CYDEV_UCFG_B0_P6_U1_DCFG7, 0x40010cee
.set CYDEV_UCFG_B0_P6_ROUTE_BASE, 0x40010d00
.set CYDEV_UCFG_B0_P6_ROUTE_SIZE, 0x000000ef
.set CYDEV_UCFG_B0_P7_BASE, 0x40010e00
.set CYDEV_UCFG_B0_P7_SIZE, 0x000001ef
.set CYDEV_UCFG_B0_P7_U0_BASE, 0x40010e00
.set CYDEV_UCFG_B0_P7_U0_SIZE, 0x00000070
.set CYDEV_UCFG_B0_P7_U0_PLD_IT0, 0x40010e00
.set CYDEV_UCFG_B0_P7_U0_PLD_IT1, 0x40010e04
.set CYDEV_UCFG_B0_P7_U0_PLD_IT2, 0x40010e08
.set CYDEV_UCFG_B0_P7_U0_PLD_IT3, 0x40010e0c
.set CYDEV_UCFG_B0_P7_U0_PLD_IT4, 0x40010e10
.set CYDEV_UCFG_B0_P7_U0_PLD_IT5, 0x40010e14
.set CYDEV_UCFG_B0_P7_U0_PLD_IT6, 0x40010e18
.set CYDEV_UCFG_B0_P7_U0_PLD_IT7, 0x40010e1c
.set CYDEV_UCFG_B0_P7_U0_PLD_IT8, 0x40010e20
.set CYDEV_UCFG_B0_P7_U0_PLD_IT9, 0x40010e24
.set CYDEV_UCFG_B0_P7_U0_PLD_IT10, 0x40010e28
.set CYDEV_UCFG_B0_P7_U0_PLD_IT11, 0x40010e2c
.set CYDEV_UCFG_B0_P7_U0_PLD_ORT0, 0x40010e30
.set CYDEV_UCFG_B0_P7_U0_PLD_ORT1, 0x40010e32
.set CYDEV_UCFG_B0_P7_U0_PLD_ORT2, 0x40010e34
.set CYDEV_UCFG_B0_P7_U0_PLD_ORT3, 0x40010e36
.set CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST, 0x40010e38
.set CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB, 0x40010e3a
.set CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET, 0x40010e3c
.set CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS, 0x40010e3e
.set CYDEV_UCFG_B0_P7_U0_CFG0, 0x40010e40
.set CYDEV_UCFG_B0_P7_U0_CFG1, 0x40010e41
.set CYDEV_UCFG_B0_P7_U0_CFG2, 0x40010e42
.set CYDEV_UCFG_B0_P7_U0_CFG3, 0x40010e43
.set CYDEV_UCFG_B0_P7_U0_CFG4, 0x40010e44
.set CYDEV_UCFG_B0_P7_U0_CFG5, 0x40010e45
.set CYDEV_UCFG_B0_P7_U0_CFG6, 0x40010e46
.set CYDEV_UCFG_B0_P7_U0_CFG7, 0x40010e47
.set CYDEV_UCFG_B0_P7_U0_CFG8, 0x40010e48
.set CYDEV_UCFG_B0_P7_U0_CFG9, 0x40010e49
.set CYDEV_UCFG_B0_P7_U0_CFG10, 0x40010e4a
.set CYDEV_UCFG_B0_P7_U0_CFG11, 0x40010e4b
.set CYDEV_UCFG_B0_P7_U0_CFG12, 0x40010e4c
.set CYDEV_UCFG_B0_P7_U0_CFG13, 0x40010e4d
.set CYDEV_UCFG_B0_P7_U0_CFG14, 0x40010e4e
.set CYDEV_UCFG_B0_P7_U0_CFG15, 0x40010e4f
.set CYDEV_UCFG_B0_P7_U0_CFG16, 0x40010e50
.set CYDEV_UCFG_B0_P7_U0_CFG17, 0x40010e51
.set CYDEV_UCFG_B0_P7_U0_CFG18, 0x40010e52
.set CYDEV_UCFG_B0_P7_U0_CFG19, 0x40010e53
.set CYDEV_UCFG_B0_P7_U0_CFG20, 0x40010e54
.set CYDEV_UCFG_B0_P7_U0_CFG21, 0x40010e55
.set CYDEV_UCFG_B0_P7_U0_CFG22, 0x40010e56
.set CYDEV_UCFG_B0_P7_U0_CFG23, 0x40010e57
.set CYDEV_UCFG_B0_P7_U0_CFG24, 0x40010e58
.set CYDEV_UCFG_B0_P7_U0_CFG25, 0x40010e59
.set CYDEV_UCFG_B0_P7_U0_CFG26, 0x40010e5a
.set CYDEV_UCFG_B0_P7_U0_CFG27, 0x40010e5b
.set CYDEV_UCFG_B0_P7_U0_CFG28, 0x40010e5c
.set CYDEV_UCFG_B0_P7_U0_CFG29, 0x40010e5d
.set CYDEV_UCFG_B0_P7_U0_CFG30, 0x40010e5e
.set CYDEV_UCFG_B0_P7_U0_CFG31, 0x40010e5f
.set CYDEV_UCFG_B0_P7_U0_DCFG0, 0x40010e60
.set CYDEV_UCFG_B0_P7_U0_DCFG1, 0x40010e62
.set CYDEV_UCFG_B0_P7_U0_DCFG2, 0x40010e64
.set CYDEV_UCFG_B0_P7_U0_DCFG3, 0x40010e66
.set CYDEV_UCFG_B0_P7_U0_DCFG4, 0x40010e68
.set CYDEV_UCFG_B0_P7_U0_DCFG5, 0x40010e6a
.set CYDEV_UCFG_B0_P7_U0_DCFG6, 0x40010e6c
.set CYDEV_UCFG_B0_P7_U0_DCFG7, 0x40010e6e
.set CYDEV_UCFG_B0_P7_U1_BASE, 0x40010e80
.set CYDEV_UCFG_B0_P7_U1_SIZE, 0x00000070
.set CYDEV_UCFG_B0_P7_U1_PLD_IT0, 0x40010e80
.set CYDEV_UCFG_B0_P7_U1_PLD_IT1, 0x40010e84
.set CYDEV_UCFG_B0_P7_U1_PLD_IT2, 0x40010e88
.set CYDEV_UCFG_B0_P7_U1_PLD_IT3, 0x40010e8c
.set CYDEV_UCFG_B0_P7_U1_PLD_IT4, 0x40010e90
.set CYDEV_UCFG_B0_P7_U1_PLD_IT5, 0x40010e94
.set CYDEV_UCFG_B0_P7_U1_PLD_IT6, 0x40010e98
.set CYDEV_UCFG_B0_P7_U1_PLD_IT7, 0x40010e9c
.set CYDEV_UCFG_B0_P7_U1_PLD_IT8, 0x40010ea0
.set CYDEV_UCFG_B0_P7_U1_PLD_IT9, 0x40010ea4
.set CYDEV_UCFG_B0_P7_U1_PLD_IT10, 0x40010ea8
.set CYDEV_UCFG_B0_P7_U1_PLD_IT11, 0x40010eac
.set CYDEV_UCFG_B0_P7_U1_PLD_ORT0, 0x40010eb0
.set CYDEV_UCFG_B0_P7_U1_PLD_ORT1, 0x40010eb2
.set CYDEV_UCFG_B0_P7_U1_PLD_ORT2, 0x40010eb4
.set CYDEV_UCFG_B0_P7_U1_PLD_ORT3, 0x40010eb6
.set CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST, 0x40010eb8
.set CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB, 0x40010eba
.set CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET, 0x40010ebc
.set CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS, 0x40010ebe
.set CYDEV_UCFG_B0_P7_U1_CFG0, 0x40010ec0
.set CYDEV_UCFG_B0_P7_U1_CFG1, 0x40010ec1
.set CYDEV_UCFG_B0_P7_U1_CFG2, 0x40010ec2
.set CYDEV_UCFG_B0_P7_U1_CFG3, 0x40010ec3
.set CYDEV_UCFG_B0_P7_U1_CFG4, 0x40010ec4
.set CYDEV_UCFG_B0_P7_U1_CFG5, 0x40010ec5
.set CYDEV_UCFG_B0_P7_U1_CFG6, 0x40010ec6
.set CYDEV_UCFG_B0_P7_U1_CFG7, 0x40010ec7
.set CYDEV_UCFG_B0_P7_U1_CFG8, 0x40010ec8
.set CYDEV_UCFG_B0_P7_U1_CFG9, 0x40010ec9
.set CYDEV_UCFG_B0_P7_U1_CFG10, 0x40010eca
.set CYDEV_UCFG_B0_P7_U1_CFG11, 0x40010ecb
.set CYDEV_UCFG_B0_P7_U1_CFG12, 0x40010ecc
.set CYDEV_UCFG_B0_P7_U1_CFG13, 0x40010ecd
.set CYDEV_UCFG_B0_P7_U1_CFG14, 0x40010ece
.set CYDEV_UCFG_B0_P7_U1_CFG15, 0x40010ecf
.set CYDEV_UCFG_B0_P7_U1_CFG16, 0x40010ed0
.set CYDEV_UCFG_B0_P7_U1_CFG17, 0x40010ed1
.set CYDEV_UCFG_B0_P7_U1_CFG18, 0x40010ed2
.set CYDEV_UCFG_B0_P7_U1_CFG19, 0x40010ed3
.set CYDEV_UCFG_B0_P7_U1_CFG20, 0x40010ed4
.set CYDEV_UCFG_B0_P7_U1_CFG21, 0x40010ed5
.set CYDEV_UCFG_B0_P7_U1_CFG22, 0x40010ed6
.set CYDEV_UCFG_B0_P7_U1_CFG23, 0x40010ed7
.set CYDEV_UCFG_B0_P7_U1_CFG24, 0x40010ed8
.set CYDEV_UCFG_B0_P7_U1_CFG25, 0x40010ed9
.set CYDEV_UCFG_B0_P7_U1_CFG26, 0x40010eda
.set CYDEV_UCFG_B0_P7_U1_CFG27, 0x40010edb
.set CYDEV_UCFG_B0_P7_U1_CFG28, 0x40010edc
.set CYDEV_UCFG_B0_P7_U1_CFG29, 0x40010edd
.set CYDEV_UCFG_B0_P7_U1_CFG30, 0x40010ede
.set CYDEV_UCFG_B0_P7_U1_CFG31, 0x40010edf
.set CYDEV_UCFG_B0_P7_U1_DCFG0, 0x40010ee0
.set CYDEV_UCFG_B0_P7_U1_DCFG1, 0x40010ee2
.set CYDEV_UCFG_B0_P7_U1_DCFG2, 0x40010ee4
.set CYDEV_UCFG_B0_P7_U1_DCFG3, 0x40010ee6
.set CYDEV_UCFG_B0_P7_U1_DCFG4, 0x40010ee8
.set CYDEV_UCFG_B0_P7_U1_DCFG5, 0x40010eea
.set CYDEV_UCFG_B0_P7_U1_DCFG6, 0x40010eec
.set CYDEV_UCFG_B0_P7_U1_DCFG7, 0x40010eee
.set CYDEV_UCFG_B0_P7_ROUTE_BASE, 0x40010f00
.set CYDEV_UCFG_B0_P7_ROUTE_SIZE, 0x000000ef
.set CYDEV_UCFG_B1_BASE, 0x40011000
.set CYDEV_UCFG_B1_SIZE, 0x00000fef
.set CYDEV_UCFG_B1_P2_BASE, 0x40011400
.set CYDEV_UCFG_B1_P2_SIZE, 0x000001ef
.set CYDEV_UCFG_B1_P2_U0_BASE, 0x40011400
.set CYDEV_UCFG_B1_P2_U0_SIZE, 0x00000070
.set CYDEV_UCFG_B1_P2_U0_PLD_IT0, 0x40011400
.set CYDEV_UCFG_B1_P2_U0_PLD_IT1, 0x40011404
.set CYDEV_UCFG_B1_P2_U0_PLD_IT2, 0x40011408
.set CYDEV_UCFG_B1_P2_U0_PLD_IT3, 0x4001140c
.set CYDEV_UCFG_B1_P2_U0_PLD_IT4, 0x40011410
.set CYDEV_UCFG_B1_P2_U0_PLD_IT5, 0x40011414
.set CYDEV_UCFG_B1_P2_U0_PLD_IT6, 0x40011418
.set CYDEV_UCFG_B1_P2_U0_PLD_IT7, 0x4001141c
.set CYDEV_UCFG_B1_P2_U0_PLD_IT8, 0x40011420
.set CYDEV_UCFG_B1_P2_U0_PLD_IT9, 0x40011424
.set CYDEV_UCFG_B1_P2_U0_PLD_IT10, 0x40011428
.set CYDEV_UCFG_B1_P2_U0_PLD_IT11, 0x4001142c
.set CYDEV_UCFG_B1_P2_U0_PLD_ORT0, 0x40011430
.set CYDEV_UCFG_B1_P2_U0_PLD_ORT1, 0x40011432
.set CYDEV_UCFG_B1_P2_U0_PLD_ORT2, 0x40011434
.set CYDEV_UCFG_B1_P2_U0_PLD_ORT3, 0x40011436
.set CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST, 0x40011438
.set CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB, 0x4001143a
.set CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET, 0x4001143c
.set CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS, 0x4001143e
.set CYDEV_UCFG_B1_P2_U0_CFG0, 0x40011440
.set CYDEV_UCFG_B1_P2_U0_CFG1, 0x40011441
.set CYDEV_UCFG_B1_P2_U0_CFG2, 0x40011442
.set CYDEV_UCFG_B1_P2_U0_CFG3, 0x40011443
.set CYDEV_UCFG_B1_P2_U0_CFG4, 0x40011444
.set CYDEV_UCFG_B1_P2_U0_CFG5, 0x40011445
.set CYDEV_UCFG_B1_P2_U0_CFG6, 0x40011446
.set CYDEV_UCFG_B1_P2_U0_CFG7, 0x40011447
.set CYDEV_UCFG_B1_P2_U0_CFG8, 0x40011448
.set CYDEV_UCFG_B1_P2_U0_CFG9, 0x40011449
.set CYDEV_UCFG_B1_P2_U0_CFG10, 0x4001144a
.set CYDEV_UCFG_B1_P2_U0_CFG11, 0x4001144b
.set CYDEV_UCFG_B1_P2_U0_CFG12, 0x4001144c
.set CYDEV_UCFG_B1_P2_U0_CFG13, 0x4001144d
.set CYDEV_UCFG_B1_P2_U0_CFG14, 0x4001144e
.set CYDEV_UCFG_B1_P2_U0_CFG15, 0x4001144f
.set CYDEV_UCFG_B1_P2_U0_CFG16, 0x40011450
.set CYDEV_UCFG_B1_P2_U0_CFG17, 0x40011451
.set CYDEV_UCFG_B1_P2_U0_CFG18, 0x40011452
.set CYDEV_UCFG_B1_P2_U0_CFG19, 0x40011453
.set CYDEV_UCFG_B1_P2_U0_CFG20, 0x40011454
.set CYDEV_UCFG_B1_P2_U0_CFG21, 0x40011455
.set CYDEV_UCFG_B1_P2_U0_CFG22, 0x40011456
.set CYDEV_UCFG_B1_P2_U0_CFG23, 0x40011457
.set CYDEV_UCFG_B1_P2_U0_CFG24, 0x40011458
.set CYDEV_UCFG_B1_P2_U0_CFG25, 0x40011459
.set CYDEV_UCFG_B1_P2_U0_CFG26, 0x4001145a
.set CYDEV_UCFG_B1_P2_U0_CFG27, 0x4001145b
.set CYDEV_UCFG_B1_P2_U0_CFG28, 0x4001145c
.set CYDEV_UCFG_B1_P2_U0_CFG29, 0x4001145d
.set CYDEV_UCFG_B1_P2_U0_CFG30, 0x4001145e
.set CYDEV_UCFG_B1_P2_U0_CFG31, 0x4001145f
.set CYDEV_UCFG_B1_P2_U0_DCFG0, 0x40011460
.set CYDEV_UCFG_B1_P2_U0_DCFG1, 0x40011462
.set CYDEV_UCFG_B1_P2_U0_DCFG2, 0x40011464
.set CYDEV_UCFG_B1_P2_U0_DCFG3, 0x40011466
.set CYDEV_UCFG_B1_P2_U0_DCFG4, 0x40011468
.set CYDEV_UCFG_B1_P2_U0_DCFG5, 0x4001146a
.set CYDEV_UCFG_B1_P2_U0_DCFG6, 0x4001146c
.set CYDEV_UCFG_B1_P2_U0_DCFG7, 0x4001146e
.set CYDEV_UCFG_B1_P2_U1_BASE, 0x40011480
.set CYDEV_UCFG_B1_P2_U1_SIZE, 0x00000070
.set CYDEV_UCFG_B1_P2_U1_PLD_IT0, 0x40011480
.set CYDEV_UCFG_B1_P2_U1_PLD_IT1, 0x40011484
.set CYDEV_UCFG_B1_P2_U1_PLD_IT2, 0x40011488
.set CYDEV_UCFG_B1_P2_U1_PLD_IT3, 0x4001148c
.set CYDEV_UCFG_B1_P2_U1_PLD_IT4, 0x40011490
.set CYDEV_UCFG_B1_P2_U1_PLD_IT5, 0x40011494
.set CYDEV_UCFG_B1_P2_U1_PLD_IT6, 0x40011498
.set CYDEV_UCFG_B1_P2_U1_PLD_IT7, 0x4001149c
.set CYDEV_UCFG_B1_P2_U1_PLD_IT8, 0x400114a0
.set CYDEV_UCFG_B1_P2_U1_PLD_IT9, 0x400114a4
.set CYDEV_UCFG_B1_P2_U1_PLD_IT10, 0x400114a8
.set CYDEV_UCFG_B1_P2_U1_PLD_IT11, 0x400114ac
.set CYDEV_UCFG_B1_P2_U1_PLD_ORT0, 0x400114b0
.set CYDEV_UCFG_B1_P2_U1_PLD_ORT1, 0x400114b2
.set CYDEV_UCFG_B1_P2_U1_PLD_ORT2, 0x400114b4
.set CYDEV_UCFG_B1_P2_U1_PLD_ORT3, 0x400114b6
.set CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST, 0x400114b8
.set CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB, 0x400114ba
.set CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET, 0x400114bc
.set CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS, 0x400114be
.set CYDEV_UCFG_B1_P2_U1_CFG0, 0x400114c0
.set CYDEV_UCFG_B1_P2_U1_CFG1, 0x400114c1
.set CYDEV_UCFG_B1_P2_U1_CFG2, 0x400114c2
.set CYDEV_UCFG_B1_P2_U1_CFG3, 0x400114c3
.set CYDEV_UCFG_B1_P2_U1_CFG4, 0x400114c4
.set CYDEV_UCFG_B1_P2_U1_CFG5, 0x400114c5
.set CYDEV_UCFG_B1_P2_U1_CFG6, 0x400114c6
.set CYDEV_UCFG_B1_P2_U1_CFG7, 0x400114c7
.set CYDEV_UCFG_B1_P2_U1_CFG8, 0x400114c8
.set CYDEV_UCFG_B1_P2_U1_CFG9, 0x400114c9
.set CYDEV_UCFG_B1_P2_U1_CFG10, 0x400114ca
.set CYDEV_UCFG_B1_P2_U1_CFG11, 0x400114cb
.set CYDEV_UCFG_B1_P2_U1_CFG12, 0x400114cc
.set CYDEV_UCFG_B1_P2_U1_CFG13, 0x400114cd
.set CYDEV_UCFG_B1_P2_U1_CFG14, 0x400114ce
.set CYDEV_UCFG_B1_P2_U1_CFG15, 0x400114cf
.set CYDEV_UCFG_B1_P2_U1_CFG16, 0x400114d0
.set CYDEV_UCFG_B1_P2_U1_CFG17, 0x400114d1
.set CYDEV_UCFG_B1_P2_U1_CFG18, 0x400114d2
.set CYDEV_UCFG_B1_P2_U1_CFG19, 0x400114d3
.set CYDEV_UCFG_B1_P2_U1_CFG20, 0x400114d4
.set CYDEV_UCFG_B1_P2_U1_CFG21, 0x400114d5
.set CYDEV_UCFG_B1_P2_U1_CFG22, 0x400114d6
.set CYDEV_UCFG_B1_P2_U1_CFG23, 0x400114d7
.set CYDEV_UCFG_B1_P2_U1_CFG24, 0x400114d8
.set CYDEV_UCFG_B1_P2_U1_CFG25, 0x400114d9
.set CYDEV_UCFG_B1_P2_U1_CFG26, 0x400114da
.set CYDEV_UCFG_B1_P2_U1_CFG27, 0x400114db
.set CYDEV_UCFG_B1_P2_U1_CFG28, 0x400114dc
.set CYDEV_UCFG_B1_P2_U1_CFG29, 0x400114dd
.set CYDEV_UCFG_B1_P2_U1_CFG30, 0x400114de
.set CYDEV_UCFG_B1_P2_U1_CFG31, 0x400114df
.set CYDEV_UCFG_B1_P2_U1_DCFG0, 0x400114e0
.set CYDEV_UCFG_B1_P2_U1_DCFG1, 0x400114e2
.set CYDEV_UCFG_B1_P2_U1_DCFG2, 0x400114e4
.set CYDEV_UCFG_B1_P2_U1_DCFG3, 0x400114e6
.set CYDEV_UCFG_B1_P2_U1_DCFG4, 0x400114e8
.set CYDEV_UCFG_B1_P2_U1_DCFG5, 0x400114ea
.set CYDEV_UCFG_B1_P2_U1_DCFG6, 0x400114ec
.set CYDEV_UCFG_B1_P2_U1_DCFG7, 0x400114ee
.set CYDEV_UCFG_B1_P2_ROUTE_BASE, 0x40011500
.set CYDEV_UCFG_B1_P2_ROUTE_SIZE, 0x000000ef
.set CYDEV_UCFG_B1_P3_BASE, 0x40011600
.set CYDEV_UCFG_B1_P3_SIZE, 0x000001ef
.set CYDEV_UCFG_B1_P3_U0_BASE, 0x40011600
.set CYDEV_UCFG_B1_P3_U0_SIZE, 0x00000070
.set CYDEV_UCFG_B1_P3_U0_PLD_IT0, 0x40011600
.set CYDEV_UCFG_B1_P3_U0_PLD_IT1, 0x40011604
.set CYDEV_UCFG_B1_P3_U0_PLD_IT2, 0x40011608
.set CYDEV_UCFG_B1_P3_U0_PLD_IT3, 0x4001160c
.set CYDEV_UCFG_B1_P3_U0_PLD_IT4, 0x40011610
.set CYDEV_UCFG_B1_P3_U0_PLD_IT5, 0x40011614
.set CYDEV_UCFG_B1_P3_U0_PLD_IT6, 0x40011618
.set CYDEV_UCFG_B1_P3_U0_PLD_IT7, 0x4001161c
.set CYDEV_UCFG_B1_P3_U0_PLD_IT8, 0x40011620
.set CYDEV_UCFG_B1_P3_U0_PLD_IT9, 0x40011624
.set CYDEV_UCFG_B1_P3_U0_PLD_IT10, 0x40011628
.set CYDEV_UCFG_B1_P3_U0_PLD_IT11, 0x4001162c
.set CYDEV_UCFG_B1_P3_U0_PLD_ORT0, 0x40011630
.set CYDEV_UCFG_B1_P3_U0_PLD_ORT1, 0x40011632
.set CYDEV_UCFG_B1_P3_U0_PLD_ORT2, 0x40011634
.set CYDEV_UCFG_B1_P3_U0_PLD_ORT3, 0x40011636
.set CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST, 0x40011638
.set CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB, 0x4001163a
.set CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET, 0x4001163c
.set CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS, 0x4001163e
.set CYDEV_UCFG_B1_P3_U0_CFG0, 0x40011640
.set CYDEV_UCFG_B1_P3_U0_CFG1, 0x40011641
.set CYDEV_UCFG_B1_P3_U0_CFG2, 0x40011642
.set CYDEV_UCFG_B1_P3_U0_CFG3, 0x40011643
.set CYDEV_UCFG_B1_P3_U0_CFG4, 0x40011644
.set CYDEV_UCFG_B1_P3_U0_CFG5, 0x40011645
.set CYDEV_UCFG_B1_P3_U0_CFG6, 0x40011646
.set CYDEV_UCFG_B1_P3_U0_CFG7, 0x40011647
.set CYDEV_UCFG_B1_P3_U0_CFG8, 0x40011648
.set CYDEV_UCFG_B1_P3_U0_CFG9, 0x40011649
.set CYDEV_UCFG_B1_P3_U0_CFG10, 0x4001164a
.set CYDEV_UCFG_B1_P3_U0_CFG11, 0x4001164b
.set CYDEV_UCFG_B1_P3_U0_CFG12, 0x4001164c
.set CYDEV_UCFG_B1_P3_U0_CFG13, 0x4001164d
.set CYDEV_UCFG_B1_P3_U0_CFG14, 0x4001164e
.set CYDEV_UCFG_B1_P3_U0_CFG15, 0x4001164f
.set CYDEV_UCFG_B1_P3_U0_CFG16, 0x40011650
.set CYDEV_UCFG_B1_P3_U0_CFG17, 0x40011651
.set CYDEV_UCFG_B1_P3_U0_CFG18, 0x40011652
.set CYDEV_UCFG_B1_P3_U0_CFG19, 0x40011653
.set CYDEV_UCFG_B1_P3_U0_CFG20, 0x40011654
.set CYDEV_UCFG_B1_P3_U0_CFG21, 0x40011655
.set CYDEV_UCFG_B1_P3_U0_CFG22, 0x40011656
.set CYDEV_UCFG_B1_P3_U0_CFG23, 0x40011657
.set CYDEV_UCFG_B1_P3_U0_CFG24, 0x40011658
.set CYDEV_UCFG_B1_P3_U0_CFG25, 0x40011659
.set CYDEV_UCFG_B1_P3_U0_CFG26, 0x4001165a
.set CYDEV_UCFG_B1_P3_U0_CFG27, 0x4001165b
.set CYDEV_UCFG_B1_P3_U0_CFG28, 0x4001165c
.set CYDEV_UCFG_B1_P3_U0_CFG29, 0x4001165d
.set CYDEV_UCFG_B1_P3_U0_CFG30, 0x4001165e
.set CYDEV_UCFG_B1_P3_U0_CFG31, 0x4001165f
.set CYDEV_UCFG_B1_P3_U0_DCFG0, 0x40011660
.set CYDEV_UCFG_B1_P3_U0_DCFG1, 0x40011662
.set CYDEV_UCFG_B1_P3_U0_DCFG2, 0x40011664
.set CYDEV_UCFG_B1_P3_U0_DCFG3, 0x40011666
.set CYDEV_UCFG_B1_P3_U0_DCFG4, 0x40011668
.set CYDEV_UCFG_B1_P3_U0_DCFG5, 0x4001166a
.set CYDEV_UCFG_B1_P3_U0_DCFG6, 0x4001166c
.set CYDEV_UCFG_B1_P3_U0_DCFG7, 0x4001166e
.set CYDEV_UCFG_B1_P3_U1_BASE, 0x40011680
.set CYDEV_UCFG_B1_P3_U1_SIZE, 0x00000070
.set CYDEV_UCFG_B1_P3_U1_PLD_IT0, 0x40011680
.set CYDEV_UCFG_B1_P3_U1_PLD_IT1, 0x40011684
.set CYDEV_UCFG_B1_P3_U1_PLD_IT2, 0x40011688
.set CYDEV_UCFG_B1_P3_U1_PLD_IT3, 0x4001168c
.set CYDEV_UCFG_B1_P3_U1_PLD_IT4, 0x40011690
.set CYDEV_UCFG_B1_P3_U1_PLD_IT5, 0x40011694
.set CYDEV_UCFG_B1_P3_U1_PLD_IT6, 0x40011698
.set CYDEV_UCFG_B1_P3_U1_PLD_IT7, 0x4001169c
.set CYDEV_UCFG_B1_P3_U1_PLD_IT8, 0x400116a0
.set CYDEV_UCFG_B1_P3_U1_PLD_IT9, 0x400116a4
.set CYDEV_UCFG_B1_P3_U1_PLD_IT10, 0x400116a8
.set CYDEV_UCFG_B1_P3_U1_PLD_IT11, 0x400116ac
.set CYDEV_UCFG_B1_P3_U1_PLD_ORT0, 0x400116b0
.set CYDEV_UCFG_B1_P3_U1_PLD_ORT1, 0x400116b2
.set CYDEV_UCFG_B1_P3_U1_PLD_ORT2, 0x400116b4
.set CYDEV_UCFG_B1_P3_U1_PLD_ORT3, 0x400116b6
.set CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST, 0x400116b8
.set CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB, 0x400116ba
.set CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET, 0x400116bc
.set CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS, 0x400116be
.set CYDEV_UCFG_B1_P3_U1_CFG0, 0x400116c0
.set CYDEV_UCFG_B1_P3_U1_CFG1, 0x400116c1
.set CYDEV_UCFG_B1_P3_U1_CFG2, 0x400116c2
.set CYDEV_UCFG_B1_P3_U1_CFG3, 0x400116c3
.set CYDEV_UCFG_B1_P3_U1_CFG4, 0x400116c4
.set CYDEV_UCFG_B1_P3_U1_CFG5, 0x400116c5
.set CYDEV_UCFG_B1_P3_U1_CFG6, 0x400116c6
.set CYDEV_UCFG_B1_P3_U1_CFG7, 0x400116c7
.set CYDEV_UCFG_B1_P3_U1_CFG8, 0x400116c8
.set CYDEV_UCFG_B1_P3_U1_CFG9, 0x400116c9
.set CYDEV_UCFG_B1_P3_U1_CFG10, 0x400116ca
.set CYDEV_UCFG_B1_P3_U1_CFG11, 0x400116cb
.set CYDEV_UCFG_B1_P3_U1_CFG12, 0x400116cc
.set CYDEV_UCFG_B1_P3_U1_CFG13, 0x400116cd
.set CYDEV_UCFG_B1_P3_U1_CFG14, 0x400116ce
.set CYDEV_UCFG_B1_P3_U1_CFG15, 0x400116cf
.set CYDEV_UCFG_B1_P3_U1_CFG16, 0x400116d0
.set CYDEV_UCFG_B1_P3_U1_CFG17, 0x400116d1
.set CYDEV_UCFG_B1_P3_U1_CFG18, 0x400116d2
.set CYDEV_UCFG_B1_P3_U1_CFG19, 0x400116d3
.set CYDEV_UCFG_B1_P3_U1_CFG20, 0x400116d4
.set CYDEV_UCFG_B1_P3_U1_CFG21, 0x400116d5
.set CYDEV_UCFG_B1_P3_U1_CFG22, 0x400116d6
.set CYDEV_UCFG_B1_P3_U1_CFG23, 0x400116d7
.set CYDEV_UCFG_B1_P3_U1_CFG24, 0x400116d8
.set CYDEV_UCFG_B1_P3_U1_CFG25, 0x400116d9
.set CYDEV_UCFG_B1_P3_U1_CFG26, 0x400116da
.set CYDEV_UCFG_B1_P3_U1_CFG27, 0x400116db
.set CYDEV_UCFG_B1_P3_U1_CFG28, 0x400116dc
.set CYDEV_UCFG_B1_P3_U1_CFG29, 0x400116dd
.set CYDEV_UCFG_B1_P3_U1_CFG30, 0x400116de
.set CYDEV_UCFG_B1_P3_U1_CFG31, 0x400116df
.set CYDEV_UCFG_B1_P3_U1_DCFG0, 0x400116e0
.set CYDEV_UCFG_B1_P3_U1_DCFG1, 0x400116e2
.set CYDEV_UCFG_B1_P3_U1_DCFG2, 0x400116e4
.set CYDEV_UCFG_B1_P3_U1_DCFG3, 0x400116e6
.set CYDEV_UCFG_B1_P3_U1_DCFG4, 0x400116e8
.set CYDEV_UCFG_B1_P3_U1_DCFG5, 0x400116ea
.set CYDEV_UCFG_B1_P3_U1_DCFG6, 0x400116ec
.set CYDEV_UCFG_B1_P3_U1_DCFG7, 0x400116ee
.set CYDEV_UCFG_B1_P3_ROUTE_BASE, 0x40011700
.set CYDEV_UCFG_B1_P3_ROUTE_SIZE, 0x000000ef
.set CYDEV_UCFG_B1_P4_BASE, 0x40011800
.set CYDEV_UCFG_B1_P4_SIZE, 0x000001ef
.set CYDEV_UCFG_B1_P4_U0_BASE, 0x40011800
.set CYDEV_UCFG_B1_P4_U0_SIZE, 0x00000070
.set CYDEV_UCFG_B1_P4_U0_PLD_IT0, 0x40011800
.set CYDEV_UCFG_B1_P4_U0_PLD_IT1, 0x40011804
.set CYDEV_UCFG_B1_P4_U0_PLD_IT2, 0x40011808
.set CYDEV_UCFG_B1_P4_U0_PLD_IT3, 0x4001180c
.set CYDEV_UCFG_B1_P4_U0_PLD_IT4, 0x40011810
.set CYDEV_UCFG_B1_P4_U0_PLD_IT5, 0x40011814
.set CYDEV_UCFG_B1_P4_U0_PLD_IT6, 0x40011818
.set CYDEV_UCFG_B1_P4_U0_PLD_IT7, 0x4001181c
.set CYDEV_UCFG_B1_P4_U0_PLD_IT8, 0x40011820
.set CYDEV_UCFG_B1_P4_U0_PLD_IT9, 0x40011824
.set CYDEV_UCFG_B1_P4_U0_PLD_IT10, 0x40011828
.set CYDEV_UCFG_B1_P4_U0_PLD_IT11, 0x4001182c
.set CYDEV_UCFG_B1_P4_U0_PLD_ORT0, 0x40011830
.set CYDEV_UCFG_B1_P4_U0_PLD_ORT1, 0x40011832
.set CYDEV_UCFG_B1_P4_U0_PLD_ORT2, 0x40011834
.set CYDEV_UCFG_B1_P4_U0_PLD_ORT3, 0x40011836
.set CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST, 0x40011838
.set CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB, 0x4001183a
.set CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET, 0x4001183c
.set CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS, 0x4001183e
.set CYDEV_UCFG_B1_P4_U0_CFG0, 0x40011840
.set CYDEV_UCFG_B1_P4_U0_CFG1, 0x40011841
.set CYDEV_UCFG_B1_P4_U0_CFG2, 0x40011842
.set CYDEV_UCFG_B1_P4_U0_CFG3, 0x40011843
.set CYDEV_UCFG_B1_P4_U0_CFG4, 0x40011844
.set CYDEV_UCFG_B1_P4_U0_CFG5, 0x40011845
.set CYDEV_UCFG_B1_P4_U0_CFG6, 0x40011846
.set CYDEV_UCFG_B1_P4_U0_CFG7, 0x40011847
.set CYDEV_UCFG_B1_P4_U0_CFG8, 0x40011848
.set CYDEV_UCFG_B1_P4_U0_CFG9, 0x40011849
.set CYDEV_UCFG_B1_P4_U0_CFG10, 0x4001184a
.set CYDEV_UCFG_B1_P4_U0_CFG11, 0x4001184b
.set CYDEV_UCFG_B1_P4_U0_CFG12, 0x4001184c
.set CYDEV_UCFG_B1_P4_U0_CFG13, 0x4001184d
.set CYDEV_UCFG_B1_P4_U0_CFG14, 0x4001184e
.set CYDEV_UCFG_B1_P4_U0_CFG15, 0x4001184f
.set CYDEV_UCFG_B1_P4_U0_CFG16, 0x40011850
.set CYDEV_UCFG_B1_P4_U0_CFG17, 0x40011851
.set CYDEV_UCFG_B1_P4_U0_CFG18, 0x40011852
.set CYDEV_UCFG_B1_P4_U0_CFG19, 0x40011853
.set CYDEV_UCFG_B1_P4_U0_CFG20, 0x40011854
.set CYDEV_UCFG_B1_P4_U0_CFG21, 0x40011855
.set CYDEV_UCFG_B1_P4_U0_CFG22, 0x40011856
.set CYDEV_UCFG_B1_P4_U0_CFG23, 0x40011857
.set CYDEV_UCFG_B1_P4_U0_CFG24, 0x40011858
.set CYDEV_UCFG_B1_P4_U0_CFG25, 0x40011859
.set CYDEV_UCFG_B1_P4_U0_CFG26, 0x4001185a
.set CYDEV_UCFG_B1_P4_U0_CFG27, 0x4001185b
.set CYDEV_UCFG_B1_P4_U0_CFG28, 0x4001185c
.set CYDEV_UCFG_B1_P4_U0_CFG29, 0x4001185d
.set CYDEV_UCFG_B1_P4_U0_CFG30, 0x4001185e
.set CYDEV_UCFG_B1_P4_U0_CFG31, 0x4001185f
.set CYDEV_UCFG_B1_P4_U0_DCFG0, 0x40011860
.set CYDEV_UCFG_B1_P4_U0_DCFG1, 0x40011862
.set CYDEV_UCFG_B1_P4_U0_DCFG2, 0x40011864
.set CYDEV_UCFG_B1_P4_U0_DCFG3, 0x40011866
.set CYDEV_UCFG_B1_P4_U0_DCFG4, 0x40011868
.set CYDEV_UCFG_B1_P4_U0_DCFG5, 0x4001186a
.set CYDEV_UCFG_B1_P4_U0_DCFG6, 0x4001186c
.set CYDEV_UCFG_B1_P4_U0_DCFG7, 0x4001186e
.set CYDEV_UCFG_B1_P4_U1_BASE, 0x40011880
.set CYDEV_UCFG_B1_P4_U1_SIZE, 0x00000070
.set CYDEV_UCFG_B1_P4_U1_PLD_IT0, 0x40011880
.set CYDEV_UCFG_B1_P4_U1_PLD_IT1, 0x40011884
.set CYDEV_UCFG_B1_P4_U1_PLD_IT2, 0x40011888
.set CYDEV_UCFG_B1_P4_U1_PLD_IT3, 0x4001188c
.set CYDEV_UCFG_B1_P4_U1_PLD_IT4, 0x40011890
.set CYDEV_UCFG_B1_P4_U1_PLD_IT5, 0x40011894
.set CYDEV_UCFG_B1_P4_U1_PLD_IT6, 0x40011898
.set CYDEV_UCFG_B1_P4_U1_PLD_IT7, 0x4001189c
.set CYDEV_UCFG_B1_P4_U1_PLD_IT8, 0x400118a0
.set CYDEV_UCFG_B1_P4_U1_PLD_IT9, 0x400118a4
.set CYDEV_UCFG_B1_P4_U1_PLD_IT10, 0x400118a8
.set CYDEV_UCFG_B1_P4_U1_PLD_IT11, 0x400118ac
.set CYDEV_UCFG_B1_P4_U1_PLD_ORT0, 0x400118b0
.set CYDEV_UCFG_B1_P4_U1_PLD_ORT1, 0x400118b2
.set CYDEV_UCFG_B1_P4_U1_PLD_ORT2, 0x400118b4
.set CYDEV_UCFG_B1_P4_U1_PLD_ORT3, 0x400118b6
.set CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST, 0x400118b8
.set CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB, 0x400118ba
.set CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET, 0x400118bc
.set CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS, 0x400118be
.set CYDEV_UCFG_B1_P4_U1_CFG0, 0x400118c0
.set CYDEV_UCFG_B1_P4_U1_CFG1, 0x400118c1
.set CYDEV_UCFG_B1_P4_U1_CFG2, 0x400118c2
.set CYDEV_UCFG_B1_P4_U1_CFG3, 0x400118c3
.set CYDEV_UCFG_B1_P4_U1_CFG4, 0x400118c4
.set CYDEV_UCFG_B1_P4_U1_CFG5, 0x400118c5
.set CYDEV_UCFG_B1_P4_U1_CFG6, 0x400118c6
.set CYDEV_UCFG_B1_P4_U1_CFG7, 0x400118c7
.set CYDEV_UCFG_B1_P4_U1_CFG8, 0x400118c8
.set CYDEV_UCFG_B1_P4_U1_CFG9, 0x400118c9
.set CYDEV_UCFG_B1_P4_U1_CFG10, 0x400118ca
.set CYDEV_UCFG_B1_P4_U1_CFG11, 0x400118cb
.set CYDEV_UCFG_B1_P4_U1_CFG12, 0x400118cc
.set CYDEV_UCFG_B1_P4_U1_CFG13, 0x400118cd
.set CYDEV_UCFG_B1_P4_U1_CFG14, 0x400118ce
.set CYDEV_UCFG_B1_P4_U1_CFG15, 0x400118cf
.set CYDEV_UCFG_B1_P4_U1_CFG16, 0x400118d0
.set CYDEV_UCFG_B1_P4_U1_CFG17, 0x400118d1
.set CYDEV_UCFG_B1_P4_U1_CFG18, 0x400118d2
.set CYDEV_UCFG_B1_P4_U1_CFG19, 0x400118d3
.set CYDEV_UCFG_B1_P4_U1_CFG20, 0x400118d4
.set CYDEV_UCFG_B1_P4_U1_CFG21, 0x400118d5
.set CYDEV_UCFG_B1_P4_U1_CFG22, 0x400118d6
.set CYDEV_UCFG_B1_P4_U1_CFG23, 0x400118d7
.set CYDEV_UCFG_B1_P4_U1_CFG24, 0x400118d8
.set CYDEV_UCFG_B1_P4_U1_CFG25, 0x400118d9
.set CYDEV_UCFG_B1_P4_U1_CFG26, 0x400118da
.set CYDEV_UCFG_B1_P4_U1_CFG27, 0x400118db
.set CYDEV_UCFG_B1_P4_U1_CFG28, 0x400118dc
.set CYDEV_UCFG_B1_P4_U1_CFG29, 0x400118dd
.set CYDEV_UCFG_B1_P4_U1_CFG30, 0x400118de
.set CYDEV_UCFG_B1_P4_U1_CFG31, 0x400118df
.set CYDEV_UCFG_B1_P4_U1_DCFG0, 0x400118e0
.set CYDEV_UCFG_B1_P4_U1_DCFG1, 0x400118e2
.set CYDEV_UCFG_B1_P4_U1_DCFG2, 0x400118e4
.set CYDEV_UCFG_B1_P4_U1_DCFG3, 0x400118e6
.set CYDEV_UCFG_B1_P4_U1_DCFG4, 0x400118e8
.set CYDEV_UCFG_B1_P4_U1_DCFG5, 0x400118ea
.set CYDEV_UCFG_B1_P4_U1_DCFG6, 0x400118ec
.set CYDEV_UCFG_B1_P4_U1_DCFG7, 0x400118ee
.set CYDEV_UCFG_B1_P4_ROUTE_BASE, 0x40011900
.set CYDEV_UCFG_B1_P4_ROUTE_SIZE, 0x000000ef
.set CYDEV_UCFG_B1_P5_BASE, 0x40011a00
.set CYDEV_UCFG_B1_P5_SIZE, 0x000001ef
.set CYDEV_UCFG_B1_P5_U0_BASE, 0x40011a00
.set CYDEV_UCFG_B1_P5_U0_SIZE, 0x00000070
.set CYDEV_UCFG_B1_P5_U0_PLD_IT0, 0x40011a00
.set CYDEV_UCFG_B1_P5_U0_PLD_IT1, 0x40011a04
.set CYDEV_UCFG_B1_P5_U0_PLD_IT2, 0x40011a08
.set CYDEV_UCFG_B1_P5_U0_PLD_IT3, 0x40011a0c
.set CYDEV_UCFG_B1_P5_U0_PLD_IT4, 0x40011a10
.set CYDEV_UCFG_B1_P5_U0_PLD_IT5, 0x40011a14
.set CYDEV_UCFG_B1_P5_U0_PLD_IT6, 0x40011a18
.set CYDEV_UCFG_B1_P5_U0_PLD_IT7, 0x40011a1c
.set CYDEV_UCFG_B1_P5_U0_PLD_IT8, 0x40011a20
.set CYDEV_UCFG_B1_P5_U0_PLD_IT9, 0x40011a24
.set CYDEV_UCFG_B1_P5_U0_PLD_IT10, 0x40011a28
.set CYDEV_UCFG_B1_P5_U0_PLD_IT11, 0x40011a2c
.set CYDEV_UCFG_B1_P5_U0_PLD_ORT0, 0x40011a30
.set CYDEV_UCFG_B1_P5_U0_PLD_ORT1, 0x40011a32
.set CYDEV_UCFG_B1_P5_U0_PLD_ORT2, 0x40011a34
.set CYDEV_UCFG_B1_P5_U0_PLD_ORT3, 0x40011a36
.set CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST, 0x40011a38
.set CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB, 0x40011a3a
.set CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET, 0x40011a3c
.set CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS, 0x40011a3e
.set CYDEV_UCFG_B1_P5_U0_CFG0, 0x40011a40
.set CYDEV_UCFG_B1_P5_U0_CFG1, 0x40011a41
.set CYDEV_UCFG_B1_P5_U0_CFG2, 0x40011a42
.set CYDEV_UCFG_B1_P5_U0_CFG3, 0x40011a43
.set CYDEV_UCFG_B1_P5_U0_CFG4, 0x40011a44
.set CYDEV_UCFG_B1_P5_U0_CFG5, 0x40011a45
.set CYDEV_UCFG_B1_P5_U0_CFG6, 0x40011a46
.set CYDEV_UCFG_B1_P5_U0_CFG7, 0x40011a47
.set CYDEV_UCFG_B1_P5_U0_CFG8, 0x40011a48
.set CYDEV_UCFG_B1_P5_U0_CFG9, 0x40011a49
.set CYDEV_UCFG_B1_P5_U0_CFG10, 0x40011a4a
.set CYDEV_UCFG_B1_P5_U0_CFG11, 0x40011a4b
.set CYDEV_UCFG_B1_P5_U0_CFG12, 0x40011a4c
.set CYDEV_UCFG_B1_P5_U0_CFG13, 0x40011a4d
.set CYDEV_UCFG_B1_P5_U0_CFG14, 0x40011a4e
.set CYDEV_UCFG_B1_P5_U0_CFG15, 0x40011a4f
.set CYDEV_UCFG_B1_P5_U0_CFG16, 0x40011a50
.set CYDEV_UCFG_B1_P5_U0_CFG17, 0x40011a51
.set CYDEV_UCFG_B1_P5_U0_CFG18, 0x40011a52
.set CYDEV_UCFG_B1_P5_U0_CFG19, 0x40011a53
.set CYDEV_UCFG_B1_P5_U0_CFG20, 0x40011a54
.set CYDEV_UCFG_B1_P5_U0_CFG21, 0x40011a55
.set CYDEV_UCFG_B1_P5_U0_CFG22, 0x40011a56
.set CYDEV_UCFG_B1_P5_U0_CFG23, 0x40011a57
.set CYDEV_UCFG_B1_P5_U0_CFG24, 0x40011a58
.set CYDEV_UCFG_B1_P5_U0_CFG25, 0x40011a59
.set CYDEV_UCFG_B1_P5_U0_CFG26, 0x40011a5a
.set CYDEV_UCFG_B1_P5_U0_CFG27, 0x40011a5b
.set CYDEV_UCFG_B1_P5_U0_CFG28, 0x40011a5c
.set CYDEV_UCFG_B1_P5_U0_CFG29, 0x40011a5d
.set CYDEV_UCFG_B1_P5_U0_CFG30, 0x40011a5e
.set CYDEV_UCFG_B1_P5_U0_CFG31, 0x40011a5f
.set CYDEV_UCFG_B1_P5_U0_DCFG0, 0x40011a60
.set CYDEV_UCFG_B1_P5_U0_DCFG1, 0x40011a62
.set CYDEV_UCFG_B1_P5_U0_DCFG2, 0x40011a64
.set CYDEV_UCFG_B1_P5_U0_DCFG3, 0x40011a66
.set CYDEV_UCFG_B1_P5_U0_DCFG4, 0x40011a68
.set CYDEV_UCFG_B1_P5_U0_DCFG5, 0x40011a6a
.set CYDEV_UCFG_B1_P5_U0_DCFG6, 0x40011a6c
.set CYDEV_UCFG_B1_P5_U0_DCFG7, 0x40011a6e
.set CYDEV_UCFG_B1_P5_U1_BASE, 0x40011a80
.set CYDEV_UCFG_B1_P5_U1_SIZE, 0x00000070
.set CYDEV_UCFG_B1_P5_U1_PLD_IT0, 0x40011a80
.set CYDEV_UCFG_B1_P5_U1_PLD_IT1, 0x40011a84
.set CYDEV_UCFG_B1_P5_U1_PLD_IT2, 0x40011a88
.set CYDEV_UCFG_B1_P5_U1_PLD_IT3, 0x40011a8c
.set CYDEV_UCFG_B1_P5_U1_PLD_IT4, 0x40011a90
.set CYDEV_UCFG_B1_P5_U1_PLD_IT5, 0x40011a94
.set CYDEV_UCFG_B1_P5_U1_PLD_IT6, 0x40011a98
.set CYDEV_UCFG_B1_P5_U1_PLD_IT7, 0x40011a9c
.set CYDEV_UCFG_B1_P5_U1_PLD_IT8, 0x40011aa0
.set CYDEV_UCFG_B1_P5_U1_PLD_IT9, 0x40011aa4
.set CYDEV_UCFG_B1_P5_U1_PLD_IT10, 0x40011aa8
.set CYDEV_UCFG_B1_P5_U1_PLD_IT11, 0x40011aac
.set CYDEV_UCFG_B1_P5_U1_PLD_ORT0, 0x40011ab0
.set CYDEV_UCFG_B1_P5_U1_PLD_ORT1, 0x40011ab2
.set CYDEV_UCFG_B1_P5_U1_PLD_ORT2, 0x40011ab4
.set CYDEV_UCFG_B1_P5_U1_PLD_ORT3, 0x40011ab6
.set CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST, 0x40011ab8
.set CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB, 0x40011aba
.set CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET, 0x40011abc
.set CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS, 0x40011abe
.set CYDEV_UCFG_B1_P5_U1_CFG0, 0x40011ac0
.set CYDEV_UCFG_B1_P5_U1_CFG1, 0x40011ac1
.set CYDEV_UCFG_B1_P5_U1_CFG2, 0x40011ac2
.set CYDEV_UCFG_B1_P5_U1_CFG3, 0x40011ac3
.set CYDEV_UCFG_B1_P5_U1_CFG4, 0x40011ac4
.set CYDEV_UCFG_B1_P5_U1_CFG5, 0x40011ac5
.set CYDEV_UCFG_B1_P5_U1_CFG6, 0x40011ac6
.set CYDEV_UCFG_B1_P5_U1_CFG7, 0x40011ac7
.set CYDEV_UCFG_B1_P5_U1_CFG8, 0x40011ac8
.set CYDEV_UCFG_B1_P5_U1_CFG9, 0x40011ac9
.set CYDEV_UCFG_B1_P5_U1_CFG10, 0x40011aca
.set CYDEV_UCFG_B1_P5_U1_CFG11, 0x40011acb
.set CYDEV_UCFG_B1_P5_U1_CFG12, 0x40011acc
.set CYDEV_UCFG_B1_P5_U1_CFG13, 0x40011acd
.set CYDEV_UCFG_B1_P5_U1_CFG14, 0x40011ace
.set CYDEV_UCFG_B1_P5_U1_CFG15, 0x40011acf
.set CYDEV_UCFG_B1_P5_U1_CFG16, 0x40011ad0
.set CYDEV_UCFG_B1_P5_U1_CFG17, 0x40011ad1
.set CYDEV_UCFG_B1_P5_U1_CFG18, 0x40011ad2
.set CYDEV_UCFG_B1_P5_U1_CFG19, 0x40011ad3
.set CYDEV_UCFG_B1_P5_U1_CFG20, 0x40011ad4
.set CYDEV_UCFG_B1_P5_U1_CFG21, 0x40011ad5
.set CYDEV_UCFG_B1_P5_U1_CFG22, 0x40011ad6
.set CYDEV_UCFG_B1_P5_U1_CFG23, 0x40011ad7
.set CYDEV_UCFG_B1_P5_U1_CFG24, 0x40011ad8
.set CYDEV_UCFG_B1_P5_U1_CFG25, 0x40011ad9
.set CYDEV_UCFG_B1_P5_U1_CFG26, 0x40011ada
.set CYDEV_UCFG_B1_P5_U1_CFG27, 0x40011adb
.set CYDEV_UCFG_B1_P5_U1_CFG28, 0x40011adc
.set CYDEV_UCFG_B1_P5_U1_CFG29, 0x40011add
.set CYDEV_UCFG_B1_P5_U1_CFG30, 0x40011ade
.set CYDEV_UCFG_B1_P5_U1_CFG31, 0x40011adf
.set CYDEV_UCFG_B1_P5_U1_DCFG0, 0x40011ae0
.set CYDEV_UCFG_B1_P5_U1_DCFG1, 0x40011ae2
.set CYDEV_UCFG_B1_P5_U1_DCFG2, 0x40011ae4
.set CYDEV_UCFG_B1_P5_U1_DCFG3, 0x40011ae6
.set CYDEV_UCFG_B1_P5_U1_DCFG4, 0x40011ae8
.set CYDEV_UCFG_B1_P5_U1_DCFG5, 0x40011aea
.set CYDEV_UCFG_B1_P5_U1_DCFG6, 0x40011aec
.set CYDEV_UCFG_B1_P5_U1_DCFG7, 0x40011aee
.set CYDEV_UCFG_B1_P5_ROUTE_BASE, 0x40011b00
.set CYDEV_UCFG_B1_P5_ROUTE_SIZE, 0x000000ef
.set CYDEV_UCFG_DSI0_BASE, 0x40014000
.set CYDEV_UCFG_DSI0_SIZE, 0x000000ef
.set CYDEV_UCFG_DSI1_BASE, 0x40014100
.set CYDEV_UCFG_DSI1_SIZE, 0x000000ef
.set CYDEV_UCFG_DSI2_BASE, 0x40014200
.set CYDEV_UCFG_DSI2_SIZE, 0x000000ef
.set CYDEV_UCFG_DSI3_BASE, 0x40014300
.set CYDEV_UCFG_DSI3_SIZE, 0x000000ef
.set CYDEV_UCFG_DSI4_BASE, 0x40014400
.set CYDEV_UCFG_DSI4_SIZE, 0x000000ef
.set CYDEV_UCFG_DSI5_BASE, 0x40014500
.set CYDEV_UCFG_DSI5_SIZE, 0x000000ef
.set CYDEV_UCFG_DSI6_BASE, 0x40014600
.set CYDEV_UCFG_DSI6_SIZE, 0x000000ef
.set CYDEV_UCFG_DSI7_BASE, 0x40014700
.set CYDEV_UCFG_DSI7_SIZE, 0x000000ef
.set CYDEV_UCFG_DSI8_BASE, 0x40014800
.set CYDEV_UCFG_DSI8_SIZE, 0x000000ef
.set CYDEV_UCFG_DSI9_BASE, 0x40014900
.set CYDEV_UCFG_DSI9_SIZE, 0x000000ef
.set CYDEV_UCFG_DSI12_BASE, 0x40014c00
.set CYDEV_UCFG_DSI12_SIZE, 0x000000ef
.set CYDEV_UCFG_DSI13_BASE, 0x40014d00
.set CYDEV_UCFG_DSI13_SIZE, 0x000000ef
.set CYDEV_UCFG_BCTL0_BASE, 0x40015000
.set CYDEV_UCFG_BCTL0_SIZE, 0x00000010
.set CYDEV_UCFG_BCTL0_MDCLK_EN, 0x40015000
.set CYDEV_UCFG_BCTL0_MBCLK_EN, 0x40015001
.set CYDEV_UCFG_BCTL0_WAIT_CFG, 0x40015002
.set CYDEV_UCFG_BCTL0_BANK_CTL, 0x40015003
.set CYDEV_UCFG_BCTL0_UDB_TEST_3, 0x40015007
.set CYDEV_UCFG_BCTL0_DCLK_EN0, 0x40015008
.set CYDEV_UCFG_BCTL0_BCLK_EN0, 0x40015009
.set CYDEV_UCFG_BCTL0_DCLK_EN1, 0x4001500a
.set CYDEV_UCFG_BCTL0_BCLK_EN1, 0x4001500b
.set CYDEV_UCFG_BCTL0_DCLK_EN2, 0x4001500c
.set CYDEV_UCFG_BCTL0_BCLK_EN2, 0x4001500d
.set CYDEV_UCFG_BCTL0_DCLK_EN3, 0x4001500e
.set CYDEV_UCFG_BCTL0_BCLK_EN3, 0x4001500f
.set CYDEV_UCFG_BCTL1_BASE, 0x40015010
.set CYDEV_UCFG_BCTL1_SIZE, 0x00000010
.set CYDEV_UCFG_BCTL1_MDCLK_EN, 0x40015010
.set CYDEV_UCFG_BCTL1_MBCLK_EN, 0x40015011
.set CYDEV_UCFG_BCTL1_WAIT_CFG, 0x40015012
.set CYDEV_UCFG_BCTL1_BANK_CTL, 0x40015013
.set CYDEV_UCFG_BCTL1_UDB_TEST_3, 0x40015017
.set CYDEV_UCFG_BCTL1_DCLK_EN0, 0x40015018
.set CYDEV_UCFG_BCTL1_BCLK_EN0, 0x40015019
.set CYDEV_UCFG_BCTL1_DCLK_EN1, 0x4001501a
.set CYDEV_UCFG_BCTL1_BCLK_EN1, 0x4001501b
.set CYDEV_UCFG_BCTL1_DCLK_EN2, 0x4001501c
.set CYDEV_UCFG_BCTL1_BCLK_EN2, 0x4001501d
.set CYDEV_UCFG_BCTL1_DCLK_EN3, 0x4001501e
.set CYDEV_UCFG_BCTL1_BCLK_EN3, 0x4001501f
.set CYDEV_IDMUX_BASE, 0x40015100
.set CYDEV_IDMUX_SIZE, 0x00000016
.set CYDEV_IDMUX_IRQ_CTL0, 0x40015100
.set CYDEV_IDMUX_IRQ_CTL1, 0x40015101
.set CYDEV_IDMUX_IRQ_CTL2, 0x40015102
.set CYDEV_IDMUX_IRQ_CTL3, 0x40015103
.set CYDEV_IDMUX_IRQ_CTL4, 0x40015104
.set CYDEV_IDMUX_IRQ_CTL5, 0x40015105
.set CYDEV_IDMUX_IRQ_CTL6, 0x40015106
.set CYDEV_IDMUX_IRQ_CTL7, 0x40015107
.set CYDEV_IDMUX_DRQ_CTL0, 0x40015110
.set CYDEV_IDMUX_DRQ_CTL1, 0x40015111
.set CYDEV_IDMUX_DRQ_CTL2, 0x40015112
.set CYDEV_IDMUX_DRQ_CTL3, 0x40015113
.set CYDEV_IDMUX_DRQ_CTL4, 0x40015114
.set CYDEV_IDMUX_DRQ_CTL5, 0x40015115
.set CYDEV_CACHERAM_BASE, 0x40030000
.set CYDEV_CACHERAM_SIZE, 0x00000400
.set CYDEV_CACHERAM_DATA_MBASE, 0x40030000
.set CYDEV_CACHERAM_DATA_MSIZE, 0x00000400
.set CYDEV_SFR_BASE, 0x40050100
.set CYDEV_SFR_SIZE, 0x000000fb
.set CYDEV_SFR_GPIO0, 0x40050180
.set CYDEV_SFR_GPIRD0, 0x40050189
.set CYDEV_SFR_GPIO0_SEL, 0x4005018a
.set CYDEV_SFR_GPIO1, 0x40050190
.set CYDEV_SFR_GPIRD1, 0x40050191
.set CYDEV_SFR_GPIO2, 0x40050198
.set CYDEV_SFR_GPIRD2, 0x40050199
.set CYDEV_SFR_GPIO2_SEL, 0x4005019a
.set CYDEV_SFR_GPIO1_SEL, 0x400501a2
.set CYDEV_SFR_GPIO3, 0x400501b0
.set CYDEV_SFR_GPIRD3, 0x400501b1
.set CYDEV_SFR_GPIO3_SEL, 0x400501b2
.set CYDEV_SFR_GPIO4, 0x400501c0
.set CYDEV_SFR_GPIRD4, 0x400501c1
.set CYDEV_SFR_GPIO4_SEL, 0x400501c2
.set CYDEV_SFR_GPIO5, 0x400501c8
.set CYDEV_SFR_GPIRD5, 0x400501c9
.set CYDEV_SFR_GPIO5_SEL, 0x400501ca
.set CYDEV_SFR_GPIO6, 0x400501d8
.set CYDEV_SFR_GPIRD6, 0x400501d9
.set CYDEV_SFR_GPIO6_SEL, 0x400501da
.set CYDEV_SFR_GPIO12, 0x400501e8
.set CYDEV_SFR_GPIRD12, 0x400501e9
.set CYDEV_SFR_GPIO12_SEL, 0x400501f2
.set CYDEV_SFR_GPIO15, 0x400501f8
.set CYDEV_SFR_GPIRD15, 0x400501f9
.set CYDEV_SFR_GPIO15_SEL, 0x400501fa
.set CYDEV_P3BA_BASE, 0x40050300
.set CYDEV_P3BA_SIZE, 0x0000002b
.set CYDEV_P3BA_Y_START, 0x40050300
.set CYDEV_P3BA_YROLL, 0x40050301
.set CYDEV_P3BA_YCFG, 0x40050302
.set CYDEV_P3BA_X_START1, 0x40050303
.set CYDEV_P3BA_X_START2, 0x40050304
.set CYDEV_P3BA_XROLL1, 0x40050305
.set CYDEV_P3BA_XROLL2, 0x40050306
.set CYDEV_P3BA_XINC, 0x40050307
.set CYDEV_P3BA_XCFG, 0x40050308
.set CYDEV_P3BA_OFFSETADDR1, 0x40050309
.set CYDEV_P3BA_OFFSETADDR2, 0x4005030a
.set CYDEV_P3BA_OFFSETADDR3, 0x4005030b
.set CYDEV_P3BA_ABSADDR1, 0x4005030c
.set CYDEV_P3BA_ABSADDR2, 0x4005030d
.set CYDEV_P3BA_ABSADDR3, 0x4005030e
.set CYDEV_P3BA_ABSADDR4, 0x4005030f
.set CYDEV_P3BA_DATCFG1, 0x40050310
.set CYDEV_P3BA_DATCFG2, 0x40050311
.set CYDEV_P3BA_CMP_RSLT1, 0x40050314
.set CYDEV_P3BA_CMP_RSLT2, 0x40050315
.set CYDEV_P3BA_CMP_RSLT3, 0x40050316
.set CYDEV_P3BA_CMP_RSLT4, 0x40050317
.set CYDEV_P3BA_DATA_REG1, 0x40050318
.set CYDEV_P3BA_DATA_REG2, 0x40050319
.set CYDEV_P3BA_DATA_REG3, 0x4005031a
.set CYDEV_P3BA_DATA_REG4, 0x4005031b
.set CYDEV_P3BA_EXP_DATA1, 0x4005031c
.set CYDEV_P3BA_EXP_DATA2, 0x4005031d
.set CYDEV_P3BA_EXP_DATA3, 0x4005031e
.set CYDEV_P3BA_EXP_DATA4, 0x4005031f
.set CYDEV_P3BA_MSTR_HRDATA1, 0x40050320
.set CYDEV_P3BA_MSTR_HRDATA2, 0x40050321
.set CYDEV_P3BA_MSTR_HRDATA3, 0x40050322
.set CYDEV_P3BA_MSTR_HRDATA4, 0x40050323
.set CYDEV_P3BA_BIST_EN, 0x40050324
.set CYDEV_P3BA_PHUB_MASTER_SSR, 0x40050325
.set CYDEV_P3BA_SEQCFG1, 0x40050326
.set CYDEV_P3BA_SEQCFG2, 0x40050327
.set CYDEV_P3BA_Y_CURR, 0x40050328
.set CYDEV_P3BA_X_CURR1, 0x40050329
.set CYDEV_P3BA_X_CURR2, 0x4005032a
.set CYDEV_PANTHER_BASE, 0x40080000
.set CYDEV_PANTHER_SIZE, 0x00000020
.set CYDEV_PANTHER_STCALIB_CFG, 0x40080000
.set CYDEV_PANTHER_WAITPIPE, 0x40080004
.set CYDEV_PANTHER_TRACE_CFG, 0x40080008
.set CYDEV_PANTHER_DBG_CFG, 0x4008000c
.set CYDEV_PANTHER_CM3_LCKRST_STAT, 0x40080018
.set CYDEV_PANTHER_DEVICE_ID, 0x4008001c
.set CYDEV_FLSECC_BASE, 0x48000000
.set CYDEV_FLSECC_SIZE, 0x00008000
.set CYDEV_FLSECC_DATA_MBASE, 0x48000000
.set CYDEV_FLSECC_DATA_MSIZE, 0x00008000
.set CYDEV_FLSHID_BASE, 0x49000000
.set CYDEV_FLSHID_SIZE, 0x00000200
.set CYDEV_FLSHID_RSVD_MBASE, 0x49000000
.set CYDEV_FLSHID_RSVD_MSIZE, 0x00000080
.set CYDEV_FLSHID_CUST_MDATA_MBASE, 0x49000080
.set CYDEV_FLSHID_CUST_MDATA_MSIZE, 0x00000080
.set CYDEV_FLSHID_CUST_TABLES_BASE, 0x49000100
.set CYDEV_FLSHID_CUST_TABLES_SIZE, 0x00000040
.set CYDEV_FLSHID_CUST_TABLES_Y_LOC, 0x49000100
.set CYDEV_FLSHID_CUST_TABLES_X_LOC, 0x49000101
.set CYDEV_FLSHID_CUST_TABLES_WAFER_NUM, 0x49000102
.set CYDEV_FLSHID_CUST_TABLES_LOT_LSB, 0x49000103
.set CYDEV_FLSHID_CUST_TABLES_LOT_MSB, 0x49000104
.set CYDEV_FLSHID_CUST_TABLES_WRK_WK, 0x49000105
.set CYDEV_FLSHID_CUST_TABLES_FAB_YR, 0x49000106
.set CYDEV_FLSHID_CUST_TABLES_MINOR, 0x49000107
.set CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ, 0x49000108
.set CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ, 0x49000109
.set CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ, 0x4900010a
.set CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ, 0x4900010b
.set CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ, 0x4900010c
.set CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ, 0x4900010d
.set CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ, 0x4900010e
.set CYDEV_FLSHID_CUST_TABLES_IMO_USB, 0x4900010f
.set CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS, 0x49000110
.set CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS, 0x49000111
.set CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS, 0x49000112
.set CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS, 0x49000113
.set CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS, 0x49000114
.set CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS, 0x49000115
.set CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS, 0x49000116
.set CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS, 0x49000117
.set CYDEV_FLSHID_CUST_TABLES_DEC_M1, 0x49000118
.set CYDEV_FLSHID_CUST_TABLES_DEC_M2, 0x49000119
.set CYDEV_FLSHID_CUST_TABLES_DEC_M3, 0x4900011a
.set CYDEV_FLSHID_CUST_TABLES_DEC_M4, 0x4900011b
.set CYDEV_FLSHID_CUST_TABLES_DEC_M5, 0x4900011c
.set CYDEV_FLSHID_CUST_TABLES_DEC_M6, 0x4900011d
.set CYDEV_FLSHID_CUST_TABLES_DEC_M7, 0x4900011e
.set CYDEV_FLSHID_CUST_TABLES_DEC_M8, 0x4900011f
.set CYDEV_FLSHID_CUST_TABLES_DAC0_M1, 0x49000120
.set CYDEV_FLSHID_CUST_TABLES_DAC0_M2, 0x49000121
.set CYDEV_FLSHID_CUST_TABLES_DAC0_M3, 0x49000122
.set CYDEV_FLSHID_CUST_TABLES_DAC0_M4, 0x49000123
.set CYDEV_FLSHID_CUST_TABLES_DAC0_M5, 0x49000124
.set CYDEV_FLSHID_CUST_TABLES_DAC0_M6, 0x49000125
.set CYDEV_FLSHID_CUST_TABLES_DAC0_M7, 0x49000126
.set CYDEV_FLSHID_CUST_TABLES_DAC0_M8, 0x49000127
.set CYDEV_FLSHID_CUST_TABLES_DAC2_M1, 0x49000128
.set CYDEV_FLSHID_CUST_TABLES_DAC2_M2, 0x49000129
.set CYDEV_FLSHID_CUST_TABLES_DAC2_M3, 0x4900012a
.set CYDEV_FLSHID_CUST_TABLES_DAC2_M4, 0x4900012b
.set CYDEV_FLSHID_CUST_TABLES_DAC2_M5, 0x4900012c
.set CYDEV_FLSHID_CUST_TABLES_DAC2_M6, 0x4900012d
.set CYDEV_FLSHID_CUST_TABLES_DAC2_M7, 0x4900012e
.set CYDEV_FLSHID_CUST_TABLES_DAC2_M8, 0x4900012f
.set CYDEV_FLSHID_CUST_TABLES_DAC1_M1, 0x49000130
.set CYDEV_FLSHID_CUST_TABLES_DAC1_M2, 0x49000131
.set CYDEV_FLSHID_CUST_TABLES_DAC1_M3, 0x49000132
.set CYDEV_FLSHID_CUST_TABLES_DAC1_M4, 0x49000133
.set CYDEV_FLSHID_CUST_TABLES_DAC1_M5, 0x49000134
.set CYDEV_FLSHID_CUST_TABLES_DAC1_M6, 0x49000135
.set CYDEV_FLSHID_CUST_TABLES_DAC1_M7, 0x49000136
.set CYDEV_FLSHID_CUST_TABLES_DAC1_M8, 0x49000137
.set CYDEV_FLSHID_CUST_TABLES_DAC3_M1, 0x49000138
.set CYDEV_FLSHID_CUST_TABLES_DAC3_M2, 0x49000139
.set CYDEV_FLSHID_CUST_TABLES_DAC3_M3, 0x4900013a
.set CYDEV_FLSHID_CUST_TABLES_DAC3_M4, 0x4900013b
.set CYDEV_FLSHID_CUST_TABLES_DAC3_M5, 0x4900013c
.set CYDEV_FLSHID_CUST_TABLES_DAC3_M6, 0x4900013d
.set CYDEV_FLSHID_CUST_TABLES_DAC3_M7, 0x4900013e
.set CYDEV_FLSHID_CUST_TABLES_DAC3_M8, 0x4900013f
.set CYDEV_FLSHID_MFG_CFG_BASE, 0x49000180
.set CYDEV_FLSHID_MFG_CFG_SIZE, 0x00000080
.set CYDEV_FLSHID_MFG_CFG_IMO_TR1, 0x49000188
.set CYDEV_FLSHID_MFG_CFG_CMP0_TR0, 0x490001ac
.set CYDEV_FLSHID_MFG_CFG_CMP1_TR0, 0x490001ae
.set CYDEV_FLSHID_MFG_CFG_CMP2_TR0, 0x490001b0
.set CYDEV_FLSHID_MFG_CFG_CMP3_TR0, 0x490001b2
.set CYDEV_FLSHID_MFG_CFG_CMP0_TR1, 0x490001b4
.set CYDEV_FLSHID_MFG_CFG_CMP1_TR1, 0x490001b6
.set CYDEV_FLSHID_MFG_CFG_CMP2_TR1, 0x490001b8
.set CYDEV_FLSHID_MFG_CFG_CMP3_TR1, 0x490001ba
.set CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM, 0x490001ce
.set CYDEV_EXTMEM_BASE, 0x60000000
.set CYDEV_EXTMEM_SIZE, 0x00800000
.set CYDEV_EXTMEM_DATA_MBASE, 0x60000000
.set CYDEV_EXTMEM_DATA_MSIZE, 0x00800000
.set CYDEV_ITM_BASE, 0xe0000000
.set CYDEV_ITM_SIZE, 0x00001000
.set CYDEV_ITM_TRACE_EN, 0xe0000e00
.set CYDEV_ITM_TRACE_PRIVILEGE, 0xe0000e40
.set CYDEV_ITM_TRACE_CTRL, 0xe0000e80
.set CYDEV_ITM_LOCK_ACCESS, 0xe0000fb0
.set CYDEV_ITM_LOCK_STATUS, 0xe0000fb4
.set CYDEV_ITM_PID4, 0xe0000fd0
.set CYDEV_ITM_PID5, 0xe0000fd4
.set CYDEV_ITM_PID6, 0xe0000fd8
.set CYDEV_ITM_PID7, 0xe0000fdc
.set CYDEV_ITM_PID0, 0xe0000fe0
.set CYDEV_ITM_PID1, 0xe0000fe4
.set CYDEV_ITM_PID2, 0xe0000fe8
.set CYDEV_ITM_PID3, 0xe0000fec
.set CYDEV_ITM_CID0, 0xe0000ff0
.set CYDEV_ITM_CID1, 0xe0000ff4
.set CYDEV_ITM_CID2, 0xe0000ff8
.set CYDEV_ITM_CID3, 0xe0000ffc
.set CYDEV_DWT_BASE, 0xe0001000
.set CYDEV_DWT_SIZE, 0x0000005c
.set CYDEV_DWT_CTRL, 0xe0001000
.set CYDEV_DWT_CYCLE_COUNT, 0xe0001004
.set CYDEV_DWT_CPI_COUNT, 0xe0001008
.set CYDEV_DWT_EXC_OVHD_COUNT, 0xe000100c
.set CYDEV_DWT_SLEEP_COUNT, 0xe0001010
.set CYDEV_DWT_LSU_COUNT, 0xe0001014
.set CYDEV_DWT_FOLD_COUNT, 0xe0001018
.set CYDEV_DWT_PC_SAMPLE, 0xe000101c
.set CYDEV_DWT_COMP_0, 0xe0001020
.set CYDEV_DWT_MASK_0, 0xe0001024
.set CYDEV_DWT_FUNCTION_0, 0xe0001028
.set CYDEV_DWT_COMP_1, 0xe0001030
.set CYDEV_DWT_MASK_1, 0xe0001034
.set CYDEV_DWT_FUNCTION_1, 0xe0001038
.set CYDEV_DWT_COMP_2, 0xe0001040
.set CYDEV_DWT_MASK_2, 0xe0001044
.set CYDEV_DWT_FUNCTION_2, 0xe0001048
.set CYDEV_DWT_COMP_3, 0xe0001050
.set CYDEV_DWT_MASK_3, 0xe0001054
.set CYDEV_DWT_FUNCTION_3, 0xe0001058
.set CYDEV_FPB_BASE, 0xe0002000
.set CYDEV_FPB_SIZE, 0x00001000
.set CYDEV_FPB_CTRL, 0xe0002000
.set CYDEV_FPB_REMAP, 0xe0002004
.set CYDEV_FPB_FP_COMP_0, 0xe0002008
.set CYDEV_FPB_FP_COMP_1, 0xe000200c
.set CYDEV_FPB_FP_COMP_2, 0xe0002010
.set CYDEV_FPB_FP_COMP_3, 0xe0002014
.set CYDEV_FPB_FP_COMP_4, 0xe0002018
.set CYDEV_FPB_FP_COMP_5, 0xe000201c
.set CYDEV_FPB_FP_COMP_6, 0xe0002020
.set CYDEV_FPB_FP_COMP_7, 0xe0002024
.set CYDEV_FPB_PID4, 0xe0002fd0
.set CYDEV_FPB_PID5, 0xe0002fd4
.set CYDEV_FPB_PID6, 0xe0002fd8
.set CYDEV_FPB_PID7, 0xe0002fdc
.set CYDEV_FPB_PID0, 0xe0002fe0
.set CYDEV_FPB_PID1, 0xe0002fe4
.set CYDEV_FPB_PID2, 0xe0002fe8
.set CYDEV_FPB_PID3, 0xe0002fec
.set CYDEV_FPB_CID0, 0xe0002ff0
.set CYDEV_FPB_CID1, 0xe0002ff4
.set CYDEV_FPB_CID2, 0xe0002ff8
.set CYDEV_FPB_CID3, 0xe0002ffc
.set CYDEV_NVIC_BASE, 0xe000e000
.set CYDEV_NVIC_SIZE, 0x00000d3c
.set CYDEV_NVIC_INT_CTL_TYPE, 0xe000e004
.set CYDEV_NVIC_SYSTICK_CTL, 0xe000e010
.set CYDEV_NVIC_SYSTICK_RELOAD, 0xe000e014
.set CYDEV_NVIC_SYSTICK_CURRENT, 0xe000e018
.set CYDEV_NVIC_SYSTICK_CAL, 0xe000e01c
.set CYDEV_NVIC_SETENA0, 0xe000e100
.set CYDEV_NVIC_CLRENA0, 0xe000e180
.set CYDEV_NVIC_SETPEND0, 0xe000e200
.set CYDEV_NVIC_CLRPEND0, 0xe000e280
.set CYDEV_NVIC_ACTIVE0, 0xe000e300
.set CYDEV_NVIC_PRI_0, 0xe000e400
.set CYDEV_NVIC_PRI_1, 0xe000e401
.set CYDEV_NVIC_PRI_2, 0xe000e402
.set CYDEV_NVIC_PRI_3, 0xe000e403
.set CYDEV_NVIC_PRI_4, 0xe000e404
.set CYDEV_NVIC_PRI_5, 0xe000e405
.set CYDEV_NVIC_PRI_6, 0xe000e406
.set CYDEV_NVIC_PRI_7, 0xe000e407
.set CYDEV_NVIC_PRI_8, 0xe000e408
.set CYDEV_NVIC_PRI_9, 0xe000e409
.set CYDEV_NVIC_PRI_10, 0xe000e40a
.set CYDEV_NVIC_PRI_11, 0xe000e40b
.set CYDEV_NVIC_PRI_12, 0xe000e40c
.set CYDEV_NVIC_PRI_13, 0xe000e40d
.set CYDEV_NVIC_PRI_14, 0xe000e40e
.set CYDEV_NVIC_PRI_15, 0xe000e40f
.set CYDEV_NVIC_PRI_16, 0xe000e410
.set CYDEV_NVIC_PRI_17, 0xe000e411
.set CYDEV_NVIC_PRI_18, 0xe000e412
.set CYDEV_NVIC_PRI_19, 0xe000e413
.set CYDEV_NVIC_PRI_20, 0xe000e414
.set CYDEV_NVIC_PRI_21, 0xe000e415
.set CYDEV_NVIC_PRI_22, 0xe000e416
.set CYDEV_NVIC_PRI_23, 0xe000e417
.set CYDEV_NVIC_PRI_24, 0xe000e418
.set CYDEV_NVIC_PRI_25, 0xe000e419
.set CYDEV_NVIC_PRI_26, 0xe000e41a
.set CYDEV_NVIC_PRI_27, 0xe000e41b
.set CYDEV_NVIC_PRI_28, 0xe000e41c
.set CYDEV_NVIC_PRI_29, 0xe000e41d
.set CYDEV_NVIC_PRI_30, 0xe000e41e
.set CYDEV_NVIC_PRI_31, 0xe000e41f
.set CYDEV_NVIC_CPUID_BASE, 0xe000ed00
.set CYDEV_NVIC_INTR_CTRL_STATE, 0xe000ed04
.set CYDEV_NVIC_VECT_OFFSET, 0xe000ed08
.set CYDEV_NVIC_APPLN_INTR, 0xe000ed0c
.set CYDEV_NVIC_SYSTEM_CONTROL, 0xe000ed10
.set CYDEV_NVIC_CFG_CONTROL, 0xe000ed14
.set CYDEV_NVIC_SYS_PRIO_HANDLER_4_7, 0xe000ed18
.set CYDEV_NVIC_SYS_PRIO_HANDLER_8_11, 0xe000ed1c
.set CYDEV_NVIC_SYS_PRIO_HANDLER_12_15, 0xe000ed20
.set CYDEV_NVIC_SYS_HANDLER_CSR, 0xe000ed24
.set CYDEV_NVIC_MEMMAN_FAULT_STATUS, 0xe000ed28
.set CYDEV_NVIC_BUS_FAULT_STATUS, 0xe000ed29
.set CYDEV_NVIC_USAGE_FAULT_STATUS, 0xe000ed2a
.set CYDEV_NVIC_HARD_FAULT_STATUS, 0xe000ed2c
.set CYDEV_NVIC_DEBUG_FAULT_STATUS, 0xe000ed30
.set CYDEV_NVIC_MEMMAN_FAULT_ADD, 0xe000ed34
.set CYDEV_NVIC_BUS_FAULT_ADD, 0xe000ed38
.set CYDEV_CORE_DBG_BASE, 0xe000edf0
.set CYDEV_CORE_DBG_SIZE, 0x00000010
.set CYDEV_CORE_DBG_DBG_HLT_CS, 0xe000edf0
.set CYDEV_CORE_DBG_DBG_REG_SEL, 0xe000edf4
.set CYDEV_CORE_DBG_DBG_REG_DATA, 0xe000edf8
.set CYDEV_CORE_DBG_EXC_MON_CTL, 0xe000edfc
.set CYDEV_TPIU_BASE, 0xe0040000
.set CYDEV_TPIU_SIZE, 0x00001000
.set CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ, 0xe0040000
.set CYDEV_TPIU_CURRENT_SYNC_PRT_SZ, 0xe0040004
.set CYDEV_TPIU_ASYNC_CLK_PRESCALER, 0xe0040010
.set CYDEV_TPIU_PROTOCOL, 0xe00400f0
.set CYDEV_TPIU_FORM_FLUSH_STAT, 0xe0040300
.set CYDEV_TPIU_FORM_FLUSH_CTRL, 0xe0040304
.set CYDEV_TPIU_TRIGGER, 0xe0040ee8
.set CYDEV_TPIU_ITETMDATA, 0xe0040eec
.set CYDEV_TPIU_ITATBCTR2, 0xe0040ef0
.set CYDEV_TPIU_ITATBCTR0, 0xe0040ef8
.set CYDEV_TPIU_ITITMDATA, 0xe0040efc
.set CYDEV_TPIU_ITCTRL, 0xe0040f00
.set CYDEV_TPIU_DEVID, 0xe0040fc8
.set CYDEV_TPIU_DEVTYPE, 0xe0040fcc
.set CYDEV_TPIU_PID4, 0xe0040fd0
.set CYDEV_TPIU_PID5, 0xe0040fd4
.set CYDEV_TPIU_PID6, 0xe0040fd8
.set CYDEV_TPIU_PID7, 0xe0040fdc
.set CYDEV_TPIU_PID0, 0xe0040fe0
.set CYDEV_TPIU_PID1, 0xe0040fe4
.set CYDEV_TPIU_PID2, 0xe0040fe8
.set CYDEV_TPIU_PID3, 0xe0040fec
.set CYDEV_TPIU_CID0, 0xe0040ff0
.set CYDEV_TPIU_CID1, 0xe0040ff4
.set CYDEV_TPIU_CID2, 0xe0040ff8
.set CYDEV_TPIU_CID3, 0xe0040ffc
.set CYDEV_ETM_BASE, 0xe0041000
.set CYDEV_ETM_SIZE, 0x00001000
.set CYDEV_ETM_CTL, 0xe0041000
.set CYDEV_ETM_CFG_CODE, 0xe0041004
.set CYDEV_ETM_TRIG_EVENT, 0xe0041008
.set CYDEV_ETM_STATUS, 0xe0041010
.set CYDEV_ETM_SYS_CFG, 0xe0041014
.set CYDEV_ETM_TRACE_ENB_EVENT, 0xe0041020
.set CYDEV_ETM_TRACE_EN_CTRL1, 0xe0041024
.set CYDEV_ETM_FIFOFULL_LEVEL, 0xe004102c
.set CYDEV_ETM_SYNC_FREQ, 0xe00411e0
.set CYDEV_ETM_ETM_ID, 0xe00411e4
.set CYDEV_ETM_CFG_CODE_EXT, 0xe00411e8
.set CYDEV_ETM_TR_SS_EMBICE_CTRL, 0xe00411f0
.set CYDEV_ETM_CS_TRACE_ID, 0xe0041200
.set CYDEV_ETM_OS_LOCK_ACCESS, 0xe0041300
.set CYDEV_ETM_OS_LOCK_STATUS, 0xe0041304
.set CYDEV_ETM_PDSR, 0xe0041314
.set CYDEV_ETM_ITMISCIN, 0xe0041ee0
.set CYDEV_ETM_ITTRIGOUT, 0xe0041ee8
.set CYDEV_ETM_ITATBCTR2, 0xe0041ef0
.set CYDEV_ETM_ITATBCTR0, 0xe0041ef8
.set CYDEV_ETM_INT_MODE_CTRL, 0xe0041f00
.set CYDEV_ETM_CLM_TAG_SET, 0xe0041fa0
.set CYDEV_ETM_CLM_TAG_CLR, 0xe0041fa4
.set CYDEV_ETM_LOCK_ACCESS, 0xe0041fb0
.set CYDEV_ETM_LOCK_STATUS, 0xe0041fb4
.set CYDEV_ETM_AUTH_STATUS, 0xe0041fb8
.set CYDEV_ETM_DEV_TYPE, 0xe0041fcc
.set CYDEV_ETM_PID4, 0xe0041fd0
.set CYDEV_ETM_PID5, 0xe0041fd4
.set CYDEV_ETM_PID6, 0xe0041fd8
.set CYDEV_ETM_PID7, 0xe0041fdc
.set CYDEV_ETM_PID0, 0xe0041fe0
.set CYDEV_ETM_PID1, 0xe0041fe4
.set CYDEV_ETM_PID2, 0xe0041fe8
.set CYDEV_ETM_PID3, 0xe0041fec
.set CYDEV_ETM_CID0, 0xe0041ff0
.set CYDEV_ETM_CID1, 0xe0041ff4
.set CYDEV_ETM_CID2, 0xe0041ff8
.set CYDEV_ETM_CID3, 0xe0041ffc
.set CYDEV_ROM_TABLE_BASE, 0xe00ff000
.set CYDEV_ROM_TABLE_SIZE, 0x00001000
.set CYDEV_ROM_TABLE_NVIC, 0xe00ff000
.set CYDEV_ROM_TABLE_DWT, 0xe00ff004
.set CYDEV_ROM_TABLE_FPB, 0xe00ff008
.set CYDEV_ROM_TABLE_ITM, 0xe00ff00c
.set CYDEV_ROM_TABLE_TPIU, 0xe00ff010
.set CYDEV_ROM_TABLE_ETM, 0xe00ff014
.set CYDEV_ROM_TABLE_END, 0xe00ff018
.set CYDEV_ROM_TABLE_MEMTYPE, 0xe00fffcc
.set CYDEV_ROM_TABLE_PID4, 0xe00fffd0
.set CYDEV_ROM_TABLE_PID5, 0xe00fffd4
.set CYDEV_ROM_TABLE_PID6, 0xe00fffd8
.set CYDEV_ROM_TABLE_PID7, 0xe00fffdc
.set CYDEV_ROM_TABLE_PID0, 0xe00fffe0
.set CYDEV_ROM_TABLE_PID1, 0xe00fffe4
.set CYDEV_ROM_TABLE_PID2, 0xe00fffe8
.set CYDEV_ROM_TABLE_PID3, 0xe00fffec
.set CYDEV_ROM_TABLE_CID0, 0xe00ffff0
.set CYDEV_ROM_TABLE_CID1, 0xe00ffff4
.set CYDEV_ROM_TABLE_CID2, 0xe00ffff8
.set CYDEV_ROM_TABLE_CID3, 0xe00ffffc
.set CYDEV_FLS_SIZE, CYDEV_FLASH_SIZE
.set CYDEV_ECC_BASE, CYDEV_FLSECC_BASE
.set CYDEV_FLS_SECTOR_SIZE, 0x00010000
.set CYDEV_FLS_ROW_SIZE, 0x00000100
.set CYDEV_ECC_SECTOR_SIZE, 0x00002000
.set CYDEV_ECC_ROW_SIZE, 0x00000020
.set CYDEV_EEPROM_SECTOR_SIZE, 0x00000400
.set CYDEV_EEPROM_ROW_SIZE, 0x00000010
.set CYDEV_PERIPH_BASE, CYDEV_CLKDIST_BASE
.set CYCLK_LD_DISABLE, 0x00000004
.set CYCLK_LD_SYNC_EN, 0x00000002
.set CYCLK_LD_LOAD, 0x00000001
.set CYCLK_PIPE, 0x00000080
.set CYCLK_SSS, 0x00000040
.set CYCLK_EARLY, 0x00000020
.set CYCLK_DUTY, 0x00000010
.set CYCLK_SYNC, 0x00000008
.set CYCLK_SRC_SEL_CLK_SYNC_D, 0
.set CYCLK_SRC_SEL_SYNC_DIG, 0
.set CYCLK_SRC_SEL_IMO, 1
.set CYCLK_SRC_SEL_XTAL_MHZ, 2
.set CYCLK_SRC_SEL_XTALM, 2
.set CYCLK_SRC_SEL_ILO, 3
.set CYCLK_SRC_SEL_PLL, 4
.set CYCLK_SRC_SEL_XTAL_KHZ, 5
.set CYCLK_SRC_SEL_XTALK, 5
.set CYCLK_SRC_SEL_DSI_G, 6
.set CYCLK_SRC_SEL_DSI_D, 7
.set CYCLK_SRC_SEL_CLK_SYNC_A, 0
.set CYCLK_SRC_SEL_DSI_A, 7
