Loading plugins phase: Elapsed time ==> 0s.234ms
<CYPRESSTAG name="CyDsfit arguments...">
cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -.fdsreffile=referenced_files.txt -p C:\Software\PSoC Cypress\VCNL4030X01\VCNL4030X01.cydsn\VCNL4030X01.cyprj -d CY8C5888LTI-LP097 -s C:\Software\PSoC Cypress\VCNL4030X01\VCNL4030X01.cydsn\Generated_Source\PSoC5 -- -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE
</CYPRESSTAG>
<CYPRESSTAG name="Design elaboration results...">
</CYPRESSTAG>
Elaboration phase: Elapsed time ==> 2s.923ms
<CYPRESSTAG name="HDL generation results...">
</CYPRESSTAG>
HDL generation phase: Elapsed time ==> 0s.035ms
<CYPRESSTAG name="Synthesis results...">

     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp Verilog Synthesis Compiler: Version 6.3 IR 41
  -|               |-   Copyright (C) 1991-2001 Cypress Semiconductor
   |_______________|
     | | | | | | |

======================================================================
Compiling:  VCNL4030X01.v
Program  :   C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\bin\warp.exe
Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Software\PSoC Cypress\VCNL4030X01\VCNL4030X01.cydsn\VCNL4030X01.cyprj -dcpsoc3 VCNL4030X01.v -verilog
======================================================================

======================================================================
Compiling:  VCNL4030X01.v
Program  :   C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\bin\warp.exe
Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Software\PSoC Cypress\VCNL4030X01\VCNL4030X01.cydsn\VCNL4030X01.cyprj -dcpsoc3 VCNL4030X01.v -verilog
======================================================================

======================================================================
Compiling:  VCNL4030X01.v
Program  :   vlogfe
Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Software\PSoC Cypress\VCNL4030X01\VCNL4030X01.cydsn\VCNL4030X01.cyprj -dcpsoc3 -verilog VCNL4030X01.v
======================================================================

vlogfe V6.3 IR 41:  Verilog parser
Tue Jul 27 22:59:28 2021


======================================================================
Compiling:  VCNL4030X01.v
Program  :   vpp
Options  :    -yv2 -q10 VCNL4030X01.v
======================================================================

vpp V6.3 IR 41:  Verilog Pre-Processor
Tue Jul 27 22:59:28 2021

Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\OneTerminal\OneTerminal.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\or_v1_0\or_v1_0.v'
Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v'

vpp:  No errors.

Library 'work' => directory 'lcpsoc3'
General_symbol_table
General_symbol_table
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Using control file 'VCNL4030X01.ctl'.

vlogfe:  No errors.


======================================================================
Compiling:  VCNL4030X01.v
Program  :   tovif
Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Software\PSoC Cypress\VCNL4030X01\VCNL4030X01.cydsn\VCNL4030X01.cyprj -dcpsoc3 -verilog VCNL4030X01.v
======================================================================

tovif V6.3 IR 41:  High-level synthesis
Tue Jul 27 22:59:29 2021

Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Linking 'C:\Software\PSoC Cypress\VCNL4030X01\VCNL4030X01.cydsn\codegentemp\VCNL4030X01.ctl'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'.
Linking 'C:\Software\PSoC Cypress\VCNL4030X01\VCNL4030X01.cydsn\codegentemp\VCNL4030X01.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\OneTerminal\OneTerminal.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\or_v1_0\or_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v'.

tovif:  No errors.


======================================================================
Compiling:  VCNL4030X01.v
Program  :   topld
Options  :    -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Software\PSoC Cypress\VCNL4030X01\VCNL4030X01.cydsn\VCNL4030X01.cyprj -dcpsoc3 -verilog VCNL4030X01.v
======================================================================

topld V6.3 IR 41:  Synthesis and optimization
Tue Jul 27 22:59:29 2021

Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\cypress.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\work\cypress.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.
Linking 'C:\Software\PSoC Cypress\VCNL4030X01\VCNL4030X01.cydsn\codegentemp\VCNL4030X01.ctl'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'.
Linking 'C:\Software\PSoC Cypress\VCNL4030X01\VCNL4030X01.cydsn\codegentemp\VCNL4030X01.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\OneTerminal\OneTerminal.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\or_v1_0\or_v1_0.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'.

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------
    User names
	\I2C_1:udb_clk\
	Net_5
	\I2C_1:Net_973\
	Net_6
	\I2C_1:Net_974\
	\I2C_1:timeout_clk\
	Net_11
	\I2C_1:Net_975\
	Net_9
	Net_10
	\CDC:dma_complete_0\
	\CDC:Net_1922\
	\CDC:dma_complete_1\
	\CDC:Net_1921\
	\CDC:dma_complete_2\
	\CDC:Net_1920\
	\CDC:dma_complete_3\
	\CDC:Net_1919\
	\CDC:dma_complete_4\
	\CDC:Net_1918\
	\CDC:dma_complete_5\
	\CDC:Net_1917\
	\CDC:dma_complete_6\
	\CDC:Net_1916\
	\CDC:dma_complete_7\
	\CDC:Net_1915\


Deleted 26 User equations/components.
Deleted 0 Synthesized equations/components.

------------------------------------------------------
Alias Detection
------------------------------------------------------
Aliasing \I2C_1:Net_968\ to \I2C_1:Net_969\
Aliasing tmpOE__SCL_1_net_0 to \I2C_1:Net_969\
Aliasing one to \I2C_1:Net_969\
Aliasing tmpOE__SDA_1_net_0 to \I2C_1:Net_969\
Aliasing \CDC:tmpOE__Dm_net_0\ to \I2C_1:Net_969\
Aliasing \CDC:tmpOE__Dp_net_0\ to \I2C_1:Net_969\
Removing Rhs of wire \I2C_1:sda_x_wire\[0] = \I2C_1:Net_643_1\[1]
Removing Rhs of wire \I2C_1:Net_697\[3] = \I2C_1:Net_643_2\[9]
Removing Rhs of wire \I2C_1:Net_1109_0\[6] = \I2C_1:scl_yfb\[19]
Removing Rhs of wire \I2C_1:Net_1109_1\[7] = \I2C_1:sda_yfb\[20]
Removing Lhs of wire \I2C_1:scl_x_wire\[10] = \I2C_1:Net_643_0\[8]
Removing Lhs of wire \I2C_1:Net_968\[12] = \I2C_1:Net_969\[11]
Removing Lhs of wire \I2C_1:tmpOE__Bufoe_scl_net_0\[22] = \I2C_1:Net_969\[11]
Removing Lhs of wire \I2C_1:tmpOE__Bufoe_sda_net_0\[25] = \I2C_1:Net_969\[11]
Removing Rhs of wire tmpOE__SCL_1_net_0[33] = \I2C_1:Net_969\[11]
Removing Lhs of wire one[37] = tmpOE__SCL_1_net_0[33]
Removing Lhs of wire tmpOE__SDA_1_net_0[40] = tmpOE__SCL_1_net_0[33]
Removing Lhs of wire \CDC:tmpOE__Dm_net_0\[47] = tmpOE__SCL_1_net_0[33]
Removing Lhs of wire \CDC:tmpOE__Dp_net_0\[54] = tmpOE__SCL_1_net_0[33]

------------------------------------------------------
Aliased 0 equations, 13 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------

Substituting virtuals - pass 1:


----------------------------------------------------------
Circuit simplification results:

	Expanded 0 signals.
	Turned 0 signals into soft nodes.
	Maximum default expansion cost was set at 3.
----------------------------------------------------------

topld:  No errors.

CYPRESS_DIR    : C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp
Warp Program   : C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\warp\bin\warp.exe
Warp Arguments : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya "-.fftprj=C:\Software\PSoC Cypress\VCNL4030X01\VCNL4030X01.cydsn\VCNL4030X01.cyprj" -dcpsoc3 VCNL4030X01.v -verilog
</CYPRESSTAG>
Warp synthesis phase: Elapsed time ==> 2s.413ms
<CYPRESSTAG name="Fitter results...">
<CYPRESSTAG name="Fitter startup details...">
cyp3fit: V4.3.0.1445, Family: PSoC3, Started at: Tuesday, 27 July 2021 22:59:30
Options: -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Software\PSoC Cypress\VCNL4030X01\VCNL4030X01.cydsn\VCNL4030X01.cyprj -d CY8C5888LTI-LP097 VCNL4030X01.v -verilog
</CYPRESSTAG>
<CYPRESSTAG name="Design parsing">
Design parsing phase: Elapsed time ==> 0s.010ms
</CYPRESSTAG>
<CYPRESSTAG name="Tech Mapping">
<CYPRESSTAG name="Initial Mapping" icon="FILE_RPT_TECHM">
Assigning clock I2C_1_BusClock to clock BUS_CLK because it is a pass-through
<CYPRESSTAG name="Global Clock Selection" icon="FILE_RPT_TECHM">
</CYPRESSTAG>
<CYPRESSTAG name="UDB Clock/Enable Remapping Results">
</CYPRESSTAG>
<CYPRESSTAG name="Duplicate Macrocell detection">
</CYPRESSTAG>
</CYPRESSTAG>
<CYPRESSTAG name="Duplicate Macrocell detection">
</CYPRESSTAG>
<CYPRESSTAG name="Design Equations" icon="FILE_RPT_EQUATION">

------------------------------------------------------------
Design Equations
------------------------------------------------------------
    <CYPRESSTAG name="Pin listing">

    ------------------------------------------------------------
    Pin listing
    ------------------------------------------------------------

    Pin : Name = SCL_1(0)
        Attributes:
            In Group/Port: True
            In Sync Option: SYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: OPEN_DRAIN_LO
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: True
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 1
            IO Voltage: 0
        PORT MAP (
            pa_out => SCL_1(0)__PA ,
            fb => \I2C_1:Net_1109_0\ ,
            pin_input => \I2C_1:Net_643_0\ ,
            pad => SCL_1(0)_PAD );
        Properties:
        {
        }

    Pin : Name = SDA_1(0)
        Attributes:
            In Group/Port: True
            In Sync Option: SYNC
            Out Sync Option: NOSYNC
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: OPEN_DRAIN_LO
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: True
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: False
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: DIGITAL, ROUTABLE
            Initial Value: 1
            IO Voltage: 0
        PORT MAP (
            pa_out => SDA_1(0)__PA ,
            fb => \I2C_1:Net_1109_1\ ,
            pin_input => \I2C_1:sda_x_wire\ ,
            pad => SDA_1(0)_PAD );
        Properties:
        {
        }

    Pin : Name = \CDC:Dm(0)\
        Attributes:
            In Group/Port: True
            In Sync Option: AUTO
            Out Sync Option: AUTO
            Interrupt generated: False
            Interrupt mode: NONE
            Drive mode: HI_Z_ANALOG
            VTrip: EITHER
            Slew: FAST
            Input Sync needed: False
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: True
            Is OE Registered: False
            Uses Analog: True
            Can contain Digital: False
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: USB_D_MINUS
            Initial Value: 0
            IO Voltage: 0
        PORT MAP (
            pa_out => \CDC:Dm(0)\__PA ,
            analog_term => \CDC:Net_597\ ,
            pad => \CDC:Dm(0)_PAD\ );
        Properties:
        {
        }

    Pin : Name = \CDC:Dp(0)\
        Attributes:
            In Group/Port: True
            In Sync Option: SYNC
            Out Sync Option: AUTO
            Interrupt generated: True
            Interrupt mode: FALLING
            Drive mode: HI_Z_ANALOG
            VTrip: CMOS
            Slew: FAST
            Input Sync needed: True
            Output Sync needed: False
            SC shield enabled: False
            POR State: ANY
            LCD Mode: COMMON
            Register Mode: RegComb
            CaSense Mode: NEITHER
            Treat as pin: False
            Is OE Registered: False
            Uses Analog: True
            Can contain Digital: True
            Is SIO: False
            SIO Output Buf: NONREGULATED
            SIO Input Buf: SINGLE_ENDED
            SIO HiFreq: LOW
            SIO Hyst: DISABLED
            SIO Vtrip: MULTIPLIER_0_5
            SIO Multiplier Index: 0
            SIO RefSel: VCC_IO
            Required Capabilities: USB_D_PLUS
            Initial Value: 1
            IO Voltage: 0
        PORT MAP (
            pa_out => \CDC:Dp(0)\__PA ,
            analog_term => \CDC:Net_1000\ ,
            pad => \CDC:Dp(0)_PAD\ );
        Properties:
        {
        }
    </CYPRESSTAG>
    <CYPRESSTAG name="Macrocell listing" icon="FILE_RPT_EQUATION">
    </CYPRESSTAG>
    <CYPRESSTAG name="Datapath listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Status register listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="StatusI register listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Sync listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Control register listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Count7 listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="DRQ listing">
    </CYPRESSTAG>
    <CYPRESSTAG name="Interrupt listing">

    ------------------------------------------------------------
    Interrupt listing
    ------------------------------------------------------------

    interrupt: Name =\I2C_1:I2C_IRQ\
        PORT MAP (
            interrupt => \I2C_1:Net_697\ );
        Properties:
        {
            int_type = "00"
            is_nmi = 0
        }

    interrupt: Name =\CDC:dp_int\
        PORT MAP (
            interrupt => \CDC:Net_1010\ );
        Properties:
        {
            int_type = "10"
            is_nmi = 0
        }

    interrupt: Name =\CDC:ep_3\
        PORT MAP (
            interrupt => \CDC:ep_int_3\ );
        Properties:
        {
            int_type = "10"
            is_nmi = 0
        }

    interrupt: Name =\CDC:ep_2\
        PORT MAP (
            interrupt => \CDC:ep_int_2\ );
        Properties:
        {
            int_type = "10"
            is_nmi = 0
        }

    interrupt: Name =\CDC:ep_1\
        PORT MAP (
            interrupt => \CDC:ep_int_1\ );
        Properties:
        {
            int_type = "10"
            is_nmi = 0
        }

    interrupt: Name =\CDC:ep_0\
        PORT MAP (
            interrupt => \CDC:ep_int_0\ );
        Properties:
        {
            int_type = "10"
            is_nmi = 0
        }

    interrupt: Name =\CDC:bus_reset\
        PORT MAP (
            interrupt => \CDC:Net_1876\ );
        Properties:
        {
            int_type = "10"
            is_nmi = 0
        }

    interrupt: Name =\CDC:arb_int\
        PORT MAP (
            interrupt => \CDC:Net_1889\ );
        Properties:
        {
            int_type = "10"
            is_nmi = 0
        }

    interrupt: Name =\CDC:sof_int\
        PORT MAP (
            interrupt => Net_12 );
        Properties:
        {
            int_type = "10"
            is_nmi = 0
        }
    </CYPRESSTAG>
</CYPRESSTAG>
<CYPRESSTAG name="Technology mapping summary" expanded>

------------------------------------------------------------
Technology mapping summary
------------------------------------------------------------

Resource Type                 : Used : Free :  Max :  % Used
============================================================
Digital Clocks                :    0 :    8 :    8 :  0.00 %
Analog Clocks                 :    0 :    4 :    4 :  0.00 %
CapSense Buffers              :    0 :    2 :    2 :  0.00 %
Digital Filter Block          :    0 :    1 :    1 :  0.00 %
Interrupts                    :    9 :   23 :   32 : 28.13 %
IO                            :    7 :   41 :   48 : 14.58 %
Segment LCD                   :    0 :    1 :    1 :  0.00 %
CAN 2.0b                      :    0 :    1 :    1 :  0.00 %
I2C                           :    1 :    0 :    1 : 100.00 %
USB                           :    1 :    0 :    1 : 100.00 %
DMA Channels                  :    0 :   24 :   24 :  0.00 %
Timer                         :    0 :    4 :    4 :  0.00 %
UDB                           :      :      :      :        
  Macrocells                  :    0 :  192 :  192 :  0.00 %
  Unique P-terms              :    0 :  384 :  384 :  0.00 %
  Total P-terms               :    0 :      :      :        
  Datapath Cells              :    0 :   24 :   24 :  0.00 %
  Status Cells                :    0 :   24 :   24 :  0.00 %
  Control Cells               :    0 :   24 :   24 :  0.00 %
Opamp                         :    0 :    4 :    4 :  0.00 %
Comparator                    :    0 :    4 :    4 :  0.00 %
Delta-Sigma ADC               :    0 :    1 :    1 :  0.00 %
LPF                           :    0 :    2 :    2 :  0.00 %
SAR ADC                       :    0 :    2 :    2 :  0.00 %
Analog (SC/CT) Blocks         :    0 :    4 :    4 :  0.00 %
DAC                           :      :      :      :        
  VIDAC                       :    0 :    4 :    4 :  0.00 %
</CYPRESSTAG>
Technology Mapping: Elapsed time ==> 0s.036ms
Tech Mapping phase: Elapsed time ==> 0s.099ms
</CYPRESSTAG>
<CYPRESSTAG name="Analog Placement">
Initial Analog Placement Results:
IO_0@[IOP=(12)][IoId=(0)] : SCL_1(0) (fixed)
IO_1@[IOP=(12)][IoId=(1)] : SDA_1(0) (fixed)
IO_7@[IOP=(15)][IoId=(7)] : \CDC:Dm(0)\ (fixed)
IO_6@[IOP=(15)][IoId=(6)] : \CDC:Dp(0)\ (fixed)
USB[0]@[FFB(USB,0)] : \CDC:USB\
Analog Placement phase: Elapsed time ==> 0s.018ms
</CYPRESSTAG>
<CYPRESSTAG name="Analog Routing">
Analog Routing phase: Elapsed time ==> 0s.000ms
</CYPRESSTAG>
<CYPRESSTAG name="Analog Code Generation">
============ Analog Final Answer Routes ============
Dump of CyAnalogRoutingResultsDB
Map of net to items {
}
Map of item to net {
}
Mux Info {
}
Dump of CyP35AnalogRoutingResultsDB
IsVddaHalfUsedForComp = False
IsVddaHalfUsedForSar0 = False
IsVddaHalfUsedForSar1 = False
Analog Code Generation phase: Elapsed time ==> 0s.216ms
</CYPRESSTAG>
<CYPRESSTAG name="Digital Placement">
<CYPRESSTAG name="Detailed placement messages">
I2659: No Constrained paths were found. The placer will run in non-timing driven mode.
I2076: Total run-time: 0.5 sec.

</CYPRESSTAG>
<CYPRESSTAG name="PLD Packing">
<CYPRESSTAG name="PLD Packing Summary">
No PLDs were packed.
</CYPRESSTAG>
PLD Packing: Elapsed time ==> 0s.000ms
</CYPRESSTAG>
<CYPRESSTAG name="Partitioning">
<CYPRESSTAG name="Initial Partitioning Summary">
Initial Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>
<CYPRESSTAG name="Final Partitioning Summary">
Final Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>
Partitioning: Elapsed time ==> 0s.019ms
</CYPRESSTAG>
<CYPRESSTAG name="Final Placement Summary">

------------------------------------------------------------
Final Placement Summary
------------------------------------------------------------

       Resource Type :      Count : Avg Inputs : Avg Outputs
    ========================================================
                 UDB :          0 :       0.00 :       0.00
<CYPRESSTAG name="Final Placement Details">
<CYPRESSTAG name="Component Details">

------------------------------------------------------------
Component Placement Details
------------------------------------------------------------
UDB [UDB=(0,0)] is empty.
UDB [UDB=(0,1)] is empty.
UDB [UDB=(0,2)] is empty.
UDB [UDB=(0,3)] is empty.
UDB [UDB=(0,4)] is empty.
UDB [UDB=(0,5)] is empty.
UDB [UDB=(1,0)] is empty.
UDB [UDB=(1,1)] is empty.
UDB [UDB=(1,2)] is empty.
UDB [UDB=(1,3)] is empty.
UDB [UDB=(1,4)] is empty.
UDB [UDB=(1,5)] is empty.
UDB [UDB=(2,0)] is empty.
UDB [UDB=(2,1)] is empty.
UDB [UDB=(2,2)] is empty.
UDB [UDB=(2,3)] is empty.
UDB [UDB=(2,4)] is empty.
UDB [UDB=(2,5)] is empty.
UDB [UDB=(3,0)] is empty.
UDB [UDB=(3,1)] is empty.
UDB [UDB=(3,2)] is empty.
UDB [UDB=(3,3)] is empty.
UDB [UDB=(3,4)] is empty.
UDB [UDB=(3,5)] is empty.
Intr container @ [IntrContainer=(0)]: 
  Intr@ [IntrContainer=(0)][IntrId=(0)] 
    interrupt: Name =\CDC:ep_1\
        PORT MAP (
            interrupt => \CDC:ep_int_1\ );
        Properties:
        {
            int_type = "10"
            is_nmi = 0
        }
  Intr@ [IntrContainer=(0)][IntrId=(1)] 
    interrupt: Name =\CDC:ep_2\
        PORT MAP (
            interrupt => \CDC:ep_int_2\ );
        Properties:
        {
            int_type = "10"
            is_nmi = 0
        }
  Intr@ [IntrContainer=(0)][IntrId=(2)] 
    interrupt: Name =\CDC:ep_3\
        PORT MAP (
            interrupt => \CDC:ep_int_3\ );
        Properties:
        {
            int_type = "10"
            is_nmi = 0
        }
  Intr@ [IntrContainer=(0)][IntrId=(12)] 
    interrupt: Name =\CDC:dp_int\
        PORT MAP (
            interrupt => \CDC:Net_1010\ );
        Properties:
        {
            int_type = "10"
            is_nmi = 0
        }
  Intr@ [IntrContainer=(0)][IntrId=(15)] 
    interrupt: Name =\I2C_1:I2C_IRQ\
        PORT MAP (
            interrupt => \I2C_1:Net_697\ );
        Properties:
        {
            int_type = "00"
            is_nmi = 0
        }
  Intr@ [IntrContainer=(0)][IntrId=(21)] 
    interrupt: Name =\CDC:sof_int\
        PORT MAP (
            interrupt => Net_12 );
        Properties:
        {
            int_type = "10"
            is_nmi = 0
        }
  Intr@ [IntrContainer=(0)][IntrId=(22)] 
    interrupt: Name =\CDC:arb_int\
        PORT MAP (
            interrupt => \CDC:Net_1889\ );
        Properties:
        {
            int_type = "10"
            is_nmi = 0
        }
  Intr@ [IntrContainer=(0)][IntrId=(23)] 
    interrupt: Name =\CDC:bus_reset\
        PORT MAP (
            interrupt => \CDC:Net_1876\ );
        Properties:
        {
            int_type = "10"
            is_nmi = 0
        }
  Intr@ [IntrContainer=(0)][IntrId=(24)] 
    interrupt: Name =\CDC:ep_0\
        PORT MAP (
            interrupt => \CDC:ep_int_0\ );
        Properties:
        {
            int_type = "10"
            is_nmi = 0
        }
Drq container @ [DrqContainer=(0)]: empty
Port 0 contains the following IO cells:
Port 1 contains the following IO cells:
Port 2 contains the following IO cells:
Port 3 contains the following IO cells:
Port 12 contains the following IO cells:
[IoId=0]: 
Pin : Name = SCL_1(0)
    Attributes:
        In Group/Port: True
        In Sync Option: SYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: OPEN_DRAIN_LO
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: True
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 1
        IO Voltage: 0
    PORT MAP (
        pa_out => SCL_1(0)__PA ,
        fb => \I2C_1:Net_1109_0\ ,
        pin_input => \I2C_1:Net_643_0\ ,
        pad => SCL_1(0)_PAD );
    Properties:
    {
    }

[IoId=1]: 
Pin : Name = SDA_1(0)
    Attributes:
        In Group/Port: True
        In Sync Option: SYNC
        Out Sync Option: NOSYNC
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: OPEN_DRAIN_LO
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: True
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: False
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: DIGITAL, ROUTABLE
        Initial Value: 1
        IO Voltage: 0
    PORT MAP (
        pa_out => SDA_1(0)__PA ,
        fb => \I2C_1:Net_1109_1\ ,
        pin_input => \I2C_1:sda_x_wire\ ,
        pad => SDA_1(0)_PAD );
    Properties:
    {
    }

Port 15 generates interrupt for logical port:
    logicalport: Name =\CDC:Dp\
        PORT MAP (
            in_clock_en => tmpOE__SCL_1_net_0 ,
            in_reset => zero ,
            out_clock_en => tmpOE__SCL_1_net_0 ,
            out_reset => zero ,
            interrupt => \CDC:Net_1010\ ,
            in_clock => ClockBlock_BUS_CLK );
        Properties:
        {
            drive_mode = "000"
            ibuf_enabled = "0"
            id = "beca5e2d-f70f-4900-a4db-7eca1ed3126e/618a72fc-5ddd-4df5-958f-a3d55102db42"
            init_dr_st = "1"
            input_buffer_sel = "00"
            input_clk_en = 0
            input_sync = "1"
            input_sync_mode = "0"
            intr_mode = "10"
            invert_in_clock = 0
            invert_in_clock_en = 0
            invert_in_reset = 0
            invert_out_clock = 0
            invert_out_clock_en = 0
            invert_out_reset = 0
            io_voltage = ""
            layout_mode = "CONTIGUOUS"
            oe_conn = "0"
            oe_reset = 0
            oe_sync = "0"
            output_clk_en = 0
            output_clock_mode = "0"
            output_conn = "0"
            output_mode = "0"
            output_reset = 0
            output_sync = "0"
            ovt_hyst_trim = "0"
            ovt_needed = "0"
            ovt_slew_control = "00"
            pa_in_clock = -1
            pa_in_clock_en = -1
            pa_in_reset = -1
            pa_out_clock = -1
            pa_out_clock_en = -1
            pa_out_reset = -1
            pin_aliases = ""
            pin_mode = "I"
            por_state = 4
            port_alias_group = ""
            port_alias_required = 0
            sio_group_cnt = 0
            sio_hifreq = "00000000"
            sio_hyst = "1"
            sio_ibuf = "00000000"
            sio_info = "00"
            sio_obuf = "00000000"
            sio_refsel = "00000000"
            sio_vohsel = "00000000"
            sio_vtrip = "00000000"
            slew_rate = "0"
            spanning = 0
            sw_only = 0
            use_annotation = "0"
            vtrip = "00"
            width = 1
        }
    and contains the following IO cells:
[IoId=6]: 
Pin : Name = \CDC:Dp(0)\
    Attributes:
        In Group/Port: True
        In Sync Option: SYNC
        Out Sync Option: AUTO
        Interrupt generated: True
        Interrupt mode: FALLING
        Drive mode: HI_Z_ANALOG
        VTrip: CMOS
        Slew: FAST
        Input Sync needed: True
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: False
        Is OE Registered: False
        Uses Analog: True
        Can contain Digital: True
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: USB_D_PLUS
        Initial Value: 1
        IO Voltage: 0
    PORT MAP (
        pa_out => \CDC:Dp(0)\__PA ,
        analog_term => \CDC:Net_1000\ ,
        pad => \CDC:Dp(0)_PAD\ );
    Properties:
    {
    }

[IoId=7]: 
Pin : Name = \CDC:Dm(0)\
    Attributes:
        In Group/Port: True
        In Sync Option: AUTO
        Out Sync Option: AUTO
        Interrupt generated: False
        Interrupt mode: NONE
        Drive mode: HI_Z_ANALOG
        VTrip: EITHER
        Slew: FAST
        Input Sync needed: False
        Output Sync needed: False
        SC shield enabled: False
        POR State: ANY
        LCD Mode: COMMON
        Register Mode: RegComb
        CaSense Mode: NEITHER
        Treat as pin: True
        Is OE Registered: False
        Uses Analog: True
        Can contain Digital: False
        Is SIO: False
        SIO Output Buf: NONREGULATED
        SIO Input Buf: SINGLE_ENDED
        SIO HiFreq: LOW
        SIO Hyst: DISABLED
        SIO Vtrip: MULTIPLIER_0_5
        SIO Multiplier Index: 0
        SIO RefSel: VCC_IO
        Required Capabilities: USB_D_MINUS
        Initial Value: 0
        IO Voltage: 0
    PORT MAP (
        pa_out => \CDC:Dm(0)\__PA ,
        analog_term => \CDC:Net_597\ ,
        pad => \CDC:Dm(0)_PAD\ );
    Properties:
    {
    }

ARM group 0: empty
CAN group 0: empty
Cache group 0: empty
CapSense group 0: empty
Clock group 0: 
    Clock Block @ F(Clock,0): 
    clockblockcell: Name =ClockBlock
        PORT MAP (
            imo => ClockBlock_IMO ,
            pllout => ClockBlock_PLL_OUT ,
            ilo => ClockBlock_ILO ,
            clk_100k => ClockBlock_100k ,
            clk_1k => ClockBlock_1k ,
            clk_32k => ClockBlock_32k ,
            xtal => ClockBlock_XTAL ,
            clk_32k_xtal => ClockBlock_XTAL_32KHZ ,
            clk_sync => ClockBlock_MASTER_CLK ,
            clk_bus_glb => ClockBlock_BUS_CLK ,
            clk_bus => ClockBlock_BUS_CLK_local );
        Properties:
        {
        }
Comparator group 0: empty
DFB group 0: empty
DSM group 0: empty
Decimator group 0: empty
EMIF group 0: empty
I2C group 0: 
    I2C Block @ F(I2C,0): 
    i2ccell: Name =\I2C_1:I2C_FF\
        PORT MAP (
            clock => ClockBlock_BUS_CLK ,
            scl_in => \I2C_1:Net_1109_0\ ,
            sda_in => \I2C_1:Net_1109_1\ ,
            scl_out => \I2C_1:Net_643_0\ ,
            sda_out => \I2C_1:sda_x_wire\ ,
            interrupt => \I2C_1:Net_697\ );
        Properties:
        {
            cy_registers = ""
            use_wakeup = 0
        }
LCD group 0: empty
LVD group 0: empty
PICU group 0: empty
PM group 0: empty
SC group 0: empty
SPC group 0: empty
Timer group 0: empty
USB group 0: 
    USB Block @ F(USB,0): 
    usbcell: Name =\CDC:USB\
        PORT MAP (
            dp => \CDC:Net_1000\ ,
            dm => \CDC:Net_597\ ,
            sof_int => Net_12 ,
            arb_int => \CDC:Net_1889\ ,
            usb_int => \CDC:Net_1876\ ,
            ept_int_8 => \CDC:ep_int_8\ ,
            ept_int_7 => \CDC:ep_int_7\ ,
            ept_int_6 => \CDC:ep_int_6\ ,
            ept_int_5 => \CDC:ep_int_5\ ,
            ept_int_4 => \CDC:ep_int_4\ ,
            ept_int_3 => \CDC:ep_int_3\ ,
            ept_int_2 => \CDC:ep_int_2\ ,
            ept_int_1 => \CDC:ep_int_1\ ,
            ept_int_0 => \CDC:ep_int_0\ ,
            ord_int => \CDC:Net_95\ ,
            dma_req_7 => \CDC:dma_request_7\ ,
            dma_req_6 => \CDC:dma_request_6\ ,
            dma_req_5 => \CDC:dma_request_5\ ,
            dma_req_4 => \CDC:dma_request_4\ ,
            dma_req_3 => \CDC:dma_request_3\ ,
            dma_req_2 => \CDC:dma_request_2\ ,
            dma_req_1 => \CDC:dma_request_1\ ,
            dma_req_0 => \CDC:dma_request_0\ ,
            dma_termin => \CDC:dma_terminate\ );
        Properties:
        {
            cy_registers = ""
        }
VIDAC group 0: empty
OpAmp group 0: empty
CsAbuf group 0: empty
Vref group 0: empty
LPF group 0: empty
SAR group 0: empty
ANAIF group 0: empty
PHUB group 0: empty
</CYPRESSTAG>
<CYPRESSTAG name="Port Configuration Details">

------------------------------------------------------------
Port Configuration report
------------------------------------------------------------
     |     |       | Interrupt |                  |             | 
Port | Pin | Fixed |      Type |       Drive Mode |        Name | Connections
-----+-----+-------+-----------+------------------+-------------+-----------------------------------------------
  12 |   0 |     * |      NONE |    OPEN_DRAIN_LO |    SCL_1(0) | FB(\I2C_1:Net_1109_0\), In(\I2C_1:Net_643_0\)
     |   1 |     * |      NONE |    OPEN_DRAIN_LO |    SDA_1(0) | FB(\I2C_1:Net_1109_1\), In(\I2C_1:sda_x_wire\)
-----+-----+-------+-----------+------------------+-------------+-----------------------------------------------
  15 |   6 |     * |   FALLING |      HI_Z_ANALOG | \CDC:Dp(0)\ | Analog(\CDC:Net_1000\)
     |   7 |     * |      NONE |      HI_Z_ANALOG | \CDC:Dm(0)\ | Analog(\CDC:Net_597\)
----------------------------------------------------------------------------------------------------------------
</CYPRESSTAG>
</CYPRESSTAG>
</CYPRESSTAG>
Digital component placer commit/Report: Elapsed time ==> 0s.011ms
Digital Placement phase: Elapsed time ==> 0s.915ms
</CYPRESSTAG>
<CYPRESSTAG name="Digital Routing">
"C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\bin/sjrouter.exe" --xml-path "C:\Program Files (x86)\Cypress\PSoC Creator\4.3\PSoC Creator\dev\psoc5/psoc5lp/route_arch-rrg.cydata" --vh2-path "VCNL4030X01_r.vh2" --pcf-path "VCNL4030X01.pco" --des-name "VCNL4030X01" --dsf-path "VCNL4030X01.dsf" --sdc-path "VCNL4030X01.sdc" --lib-path "VCNL4030X01_r.lib"
Routing successful.
Digital Routing phase: Elapsed time ==> 1s.206ms
</CYPRESSTAG>
<CYPRESSTAG name="Bitstream Generation">
Bitstream Generation phase: Elapsed time ==> 0s.165ms
</CYPRESSTAG>
<CYPRESSTAG name="Bitstream Verification">
Bitstream Verification phase: Elapsed time ==> 0s.032ms
</CYPRESSTAG>
<CYPRESSTAG name="Static timing analysis">
Timing report is in VCNL4030X01_timing.html.
Static timing analysis phase: Elapsed time ==> 0s.332ms
</CYPRESSTAG>
<CYPRESSTAG name="Data reporting">
Data reporting phase: Elapsed time ==> 0s.000ms
</CYPRESSTAG>
<CYPRESSTAG name="Database update...">
Design database save phase: Elapsed time ==> 0s.146ms
</CYPRESSTAG>
cydsfit: Elapsed time ==> 3s.159ms
</CYPRESSTAG>
Fitter phase: Elapsed time ==> 3s.162ms
API generation phase: Elapsed time ==> 1s.504ms
Dependency generation phase: Elapsed time ==> 0s.011ms
Cleanup phase: Elapsed time ==> 0s.001ms
