-- Project:   C:\Software\PSoC Cypress\VCNL4030X01\VCNL4030X01.cydsn\VCNL4030X01.cyprj
-- Generated: 07/27/2021 22:59:32
-- PSoC Creator  4.3

ENTITY VCNL4030X01 IS
    PORT(
        SCL_1(0)_PAD : INOUT std_ulogic;
        SDA_1(0)_PAD : INOUT std_ulogic);
    ATTRIBUTE voltage_VDDABUF OF __DEFAULT__ : ENTITY IS 5e0;
    ATTRIBUTE voltage_VDDA OF __DEFAULT__ : ENTITY IS 5e0;
    ATTRIBUTE voltage_VUSB OF __DEFAULT__ : ENTITY IS 5e0;
    ATTRIBUTE voltage_VDDD OF __DEFAULT__ : ENTITY IS 5e0;
    ATTRIBUTE voltage_VDDIO0 OF __DEFAULT__ : ENTITY IS 5e0;
    ATTRIBUTE voltage_VDDIO1 OF __DEFAULT__ : ENTITY IS 5e0;
    ATTRIBUTE voltage_VDDIO2 OF __DEFAULT__ : ENTITY IS 5e0;
    ATTRIBUTE voltage_VDDIO3 OF __DEFAULT__ : ENTITY IS 5e0;
END VCNL4030X01;

ARCHITECTURE __DEFAULT__ OF VCNL4030X01 IS
    SIGNAL ClockBlock_100k : bit;
    SIGNAL ClockBlock_1k : bit;
    SIGNAL ClockBlock_32k : bit;
    SIGNAL ClockBlock_BUS_CLK : bit;
    ATTRIBUTE global_signal OF ClockBlock_BUS_CLK : SIGNAL IS true;
    SIGNAL ClockBlock_BUS_CLK_local : bit;
    SIGNAL ClockBlock_ILO : bit;
    SIGNAL ClockBlock_IMO : bit;
    SIGNAL ClockBlock_MASTER_CLK : bit;
    SIGNAL ClockBlock_PLL_OUT : bit;
    SIGNAL ClockBlock_XTAL : bit;
    SIGNAL ClockBlock_XTAL_32KHZ : bit;
    SIGNAL Net_12 : bit;
    SIGNAL SCL_1(0)__PA : bit;
    SIGNAL SDA_1(0)__PA : bit;
    SIGNAL \\\CDC:Dm(0)\\__PA\ : bit;
    SIGNAL \\\CDC:Dp(0)\\__PA\ : bit;
    SIGNAL \CDC:Net_1010\ : bit;
    SIGNAL \CDC:Net_1876\ : bit;
    SIGNAL \CDC:Net_1889\ : bit;
    SIGNAL \CDC:Net_95\ : bit;
    SIGNAL \CDC:dma_request_0\ : bit;
    SIGNAL \CDC:dma_request_1\ : bit;
    SIGNAL \CDC:dma_request_2\ : bit;
    SIGNAL \CDC:dma_request_3\ : bit;
    SIGNAL \CDC:dma_request_4\ : bit;
    SIGNAL \CDC:dma_request_5\ : bit;
    SIGNAL \CDC:dma_request_6\ : bit;
    SIGNAL \CDC:dma_request_7\ : bit;
    SIGNAL \CDC:dma_terminate\ : bit;
    SIGNAL \CDC:ep_int_0\ : bit;
    SIGNAL \CDC:ep_int_1\ : bit;
    SIGNAL \CDC:ep_int_2\ : bit;
    SIGNAL \CDC:ep_int_3\ : bit;
    SIGNAL \CDC:ep_int_4\ : bit;
    SIGNAL \CDC:ep_int_5\ : bit;
    SIGNAL \CDC:ep_int_6\ : bit;
    SIGNAL \CDC:ep_int_7\ : bit;
    SIGNAL \CDC:ep_int_8\ : bit;
    SIGNAL \I2C_1:Net_1109_0\ : bit;
    SIGNAL \I2C_1:Net_1109_1\ : bit;
    SIGNAL \I2C_1:Net_643_0\ : bit;
    SIGNAL \I2C_1:Net_697\ : bit;
    SIGNAL \I2C_1:sda_x_wire\ : bit;
    SIGNAL __ONE__ : bit;
    ATTRIBUTE POWER OF __ONE__ : SIGNAL IS true;
    SIGNAL __ZERO__ : bit;
    ATTRIBUTE GROUND OF __ZERO__ : SIGNAL IS true;
    SIGNAL tmpOE__SCL_1_net_0 : bit;
    ATTRIBUTE POWER OF tmpOE__SCL_1_net_0 : SIGNAL IS true;
    SIGNAL zero : bit;
    ATTRIBUTE GROUND OF zero : SIGNAL IS true;
    SIGNAL \ClockBlock.clk_bus_glb_ff__sig\ : bit;
    ATTRIBUTE Location OF ClockBlock : LABEL IS "F(Clock,0)";
    ATTRIBUTE lib_model OF SCL_1(0) : LABEL IS "iocell1";
    ATTRIBUTE Location OF SCL_1(0) : LABEL IS "P12[0]";
    ATTRIBUTE lib_model OF SDA_1(0) : LABEL IS "iocell2";
    ATTRIBUTE Location OF SDA_1(0) : LABEL IS "P12[1]";
    ATTRIBUTE lib_model OF \CDC:Dm(0)\ : LABEL IS "iocell3";
    ATTRIBUTE Location OF \CDC:Dm(0)\ : LABEL IS "P15[7]";
    ATTRIBUTE Location OF \CDC:Dp\ : LABEL IS "F(PICU,8)";
    ATTRIBUTE lib_model OF \CDC:Dp(0)\ : LABEL IS "iocell4";
    ATTRIBUTE Location OF \CDC:Dp(0)\ : LABEL IS "P15[6]";
    ATTRIBUTE Location OF \I2C_1:I2C_IRQ\ : LABEL IS "[IntrContainer=(0)][IntrId=(15)]";
    ATTRIBUTE Location OF \I2C_1:I2C_FF\ : LABEL IS "F(I2C,0)";
    ATTRIBUTE Location OF \CDC:dp_int\ : LABEL IS "[IntrContainer=(0)][IntrId=(12)]";
    ATTRIBUTE Location OF \CDC:USB\ : LABEL IS "F(USB,0)";
    ATTRIBUTE Location OF \CDC:ep_3\ : LABEL IS "[IntrContainer=(0)][IntrId=(2)]";
    ATTRIBUTE Location OF \CDC:ep_2\ : LABEL IS "[IntrContainer=(0)][IntrId=(1)]";
    ATTRIBUTE Location OF \CDC:ep_1\ : LABEL IS "[IntrContainer=(0)][IntrId=(0)]";
    ATTRIBUTE Location OF \CDC:ep_0\ : LABEL IS "[IntrContainer=(0)][IntrId=(24)]";
    ATTRIBUTE Location OF \CDC:bus_reset\ : LABEL IS "[IntrContainer=(0)][IntrId=(23)]";
    ATTRIBUTE Location OF \CDC:arb_int\ : LABEL IS "[IntrContainer=(0)][IntrId=(22)]";
    ATTRIBUTE Location OF \CDC:sof_int\ : LABEL IS "[IntrContainer=(0)][IntrId=(21)]";
    COMPONENT clockblockcell
        PORT (
            dclk_0 : OUT std_ulogic;
            dclk_1 : OUT std_ulogic;
            dclk_2 : OUT std_ulogic;
            dclk_3 : OUT std_ulogic;
            dclk_4 : OUT std_ulogic;
            dclk_5 : OUT std_ulogic;
            dclk_6 : OUT std_ulogic;
            dclk_7 : OUT std_ulogic;
            dclk_glb_0 : OUT std_ulogic;
            dclk_glb_1 : OUT std_ulogic;
            dclk_glb_2 : OUT std_ulogic;
            dclk_glb_3 : OUT std_ulogic;
            dclk_glb_4 : OUT std_ulogic;
            dclk_glb_5 : OUT std_ulogic;
            dclk_glb_6 : OUT std_ulogic;
            dclk_glb_7 : OUT std_ulogic;
            aclk_0 : OUT std_ulogic;
            aclk_1 : OUT std_ulogic;
            aclk_2 : OUT std_ulogic;
            aclk_3 : OUT std_ulogic;
            aclk_glb_0 : OUT std_ulogic;
            aclk_glb_1 : OUT std_ulogic;
            aclk_glb_2 : OUT std_ulogic;
            aclk_glb_3 : OUT std_ulogic;
            clk_a_dig_0 : OUT std_ulogic;
            clk_a_dig_1 : OUT std_ulogic;
            clk_a_dig_2 : OUT std_ulogic;
            clk_a_dig_3 : OUT std_ulogic;
            clk_a_dig_glb_0 : OUT std_ulogic;
            clk_a_dig_glb_1 : OUT std_ulogic;
            clk_a_dig_glb_2 : OUT std_ulogic;
            clk_a_dig_glb_3 : OUT std_ulogic;
            clk_bus : OUT std_ulogic;
            clk_bus_glb : OUT std_ulogic;
            clk_sync : OUT std_ulogic;
            clk_32k_xtal : OUT std_ulogic;
            clk_100k : OUT std_ulogic;
            clk_32k : OUT std_ulogic;
            clk_1k : OUT std_ulogic;
            clk_usb : OUT std_ulogic;
            xmhz_xerr : OUT std_ulogic;
            pll_lock_out : OUT std_ulogic;
            dsi_dig_div_0 : IN std_ulogic;
            dsi_dig_div_1 : IN std_ulogic;
            dsi_dig_div_2 : IN std_ulogic;
            dsi_dig_div_3 : IN std_ulogic;
            dsi_dig_div_4 : IN std_ulogic;
            dsi_dig_div_5 : IN std_ulogic;
            dsi_dig_div_6 : IN std_ulogic;
            dsi_dig_div_7 : IN std_ulogic;
            dsi_ana_div_0 : IN std_ulogic;
            dsi_ana_div_1 : IN std_ulogic;
            dsi_ana_div_2 : IN std_ulogic;
            dsi_ana_div_3 : IN std_ulogic;
            dsi_glb_div : IN std_ulogic;
            dsi_clkin_div : IN std_ulogic;
            imo : OUT std_ulogic;
            ilo : OUT std_ulogic;
            xtal : OUT std_ulogic;
            pllout : OUT std_ulogic;
            clk_bus_glb_ff : OUT std_ulogic;
            aclk_glb_ff_0 : OUT std_ulogic;
            clk_a_dig_glb_ff_0 : OUT std_ulogic;
            aclk_glb_ff_1 : OUT std_ulogic;
            clk_a_dig_glb_ff_1 : OUT std_ulogic;
            aclk_glb_ff_2 : OUT std_ulogic;
            clk_a_dig_glb_ff_2 : OUT std_ulogic;
            aclk_glb_ff_3 : OUT std_ulogic;
            clk_a_dig_glb_ff_3 : OUT std_ulogic;
            dclk_glb_ff_0 : OUT std_ulogic;
            dclk_glb_ff_1 : OUT std_ulogic;
            dclk_glb_ff_2 : OUT std_ulogic;
            dclk_glb_ff_3 : OUT std_ulogic;
            dclk_glb_ff_4 : OUT std_ulogic;
            dclk_glb_ff_5 : OUT std_ulogic;
            dclk_glb_ff_6 : OUT std_ulogic;
            dclk_glb_ff_7 : OUT std_ulogic);
    END COMPONENT;
    COMPONENT i2ccell
        PORT (
            clock : IN std_ulogic;
            scl_in : IN std_ulogic;
            sda_in : IN std_ulogic;
            scl_out : OUT std_ulogic;
            sda_out : OUT std_ulogic;
            interrupt : OUT std_ulogic);
    END COMPONENT;
    COMPONENT interrupt
        PORT (
            interrupt : IN std_ulogic;
            clock : IN std_ulogic);
    END COMPONENT;
    COMPONENT iocell
        PORT (
            oe : IN std_ulogic;
            fb : OUT std_ulogic;
            pa_out : OUT std_ulogic;
            pin_input : IN std_ulogic;
            pad_in : IN std_ulogic;
            pad_out : OUT std_ulogic;
            oe_reg : OUT std_ulogic;
            oe_internal : IN std_ulogic;
            in_clock : IN std_ulogic;
            in_clock_en : IN std_ulogic;
            in_reset : IN std_ulogic;
            out_clock : IN std_ulogic;
            out_clock_en : IN std_ulogic;
            out_reset : IN std_ulogic);
    END COMPONENT;
    COMPONENT logicalport
        PORT (
            interrupt : OUT std_ulogic;
            precharge : IN std_ulogic;
            in_clock : IN std_ulogic;
            in_clock_en : IN std_ulogic;
            in_reset : IN std_ulogic;
            out_clock : IN std_ulogic;
            out_clock_en : IN std_ulogic;
            out_reset : IN std_ulogic);
    END COMPONENT;
    COMPONENT usbcell
        PORT (
            sof_int : OUT std_ulogic;
            arb_int : OUT std_ulogic;
            usb_int : OUT std_ulogic;
            ord_int : OUT std_ulogic;
            ept_int_0 : OUT std_ulogic;
            ept_int_1 : OUT std_ulogic;
            ept_int_2 : OUT std_ulogic;
            ept_int_3 : OUT std_ulogic;
            ept_int_4 : OUT std_ulogic;
            ept_int_5 : OUT std_ulogic;
            ept_int_6 : OUT std_ulogic;
            ept_int_7 : OUT std_ulogic;
            ept_int_8 : OUT std_ulogic;
            dma_req_0 : OUT std_ulogic;
            dma_req_1 : OUT std_ulogic;
            dma_req_2 : OUT std_ulogic;
            dma_req_3 : OUT std_ulogic;
            dma_req_4 : OUT std_ulogic;
            dma_req_5 : OUT std_ulogic;
            dma_req_6 : OUT std_ulogic;
            dma_req_7 : OUT std_ulogic;
            dma_termin : OUT std_ulogic);
    END COMPONENT;
BEGIN

    ClockBlock:clockblockcell
        PORT MAP(
            imo => ClockBlock_IMO,
            pllout => ClockBlock_PLL_OUT,
            ilo => ClockBlock_ILO,
            clk_100k => ClockBlock_100k,
            clk_1k => ClockBlock_1k,
            clk_32k => ClockBlock_32k,
            xtal => ClockBlock_XTAL,
            clk_32k_xtal => ClockBlock_XTAL_32KHZ,
            clk_sync => ClockBlock_MASTER_CLK,
            clk_bus_glb => ClockBlock_BUS_CLK,
            clk_bus => ClockBlock_BUS_CLK_local,
            dsi_clkin_div => open,
            dsi_glb_div => open,
            clk_bus_glb_ff => \ClockBlock.clk_bus_glb_ff__sig\);

    SCL_1:logicalport
        GENERIC MAP(
            drive_mode => "100",
            ibuf_enabled => "1",
            id => "02f2cf2c-2c7a-49df-9246-7a3435c21be3",
            init_dr_st => "1",
            input_buffer_sel => "00",
            input_clk_en => 0,
            input_sync => "1",
            input_sync_mode => "0",
            intr_mode => "00",
            invert_in_clock => 0,
            invert_in_clock_en => 0,
            invert_in_reset => 0,
            invert_out_clock => 0,
            invert_out_clock_en => 0,
            invert_out_reset => 0,
            io_voltage => "",
            layout_mode => "CONTIGUOUS",
            oe_conn => "0",
            oe_reset => 0,
            oe_sync => "0",
            output_clk_en => 0,
            output_clock_mode => "0",
            output_conn => "0",
            output_mode => "0",
            output_reset => 0,
            output_sync => "0",
            ovt_hyst_trim => "0",
            ovt_needed => "0",
            ovt_slew_control => "00",
            pa_in_clock => -1,
            pa_in_clock_en => -1,
            pa_in_reset => -1,
            pa_out_clock => -1,
            pa_out_clock_en => -1,
            pa_out_reset => -1,
            pin_aliases => "",
            pin_mode => "B",
            por_state => 4,
            port_alias_group => "",
            port_alias_required => 0,
            sio_group_cnt => 0,
            sio_hifreq => "00000000",
            sio_hyst => "1",
            sio_ibuf => "00000000",
            sio_info => "00",
            sio_obuf => "00000000",
            sio_refsel => "00000000",
            sio_vohsel => "00000000",
            sio_vtrip => "00000000",
            slew_rate => "0",
            spanning => 0,
            sw_only => 0,
            use_annotation => "0",
            vtrip => "00",
            width => 1,
            in_clk_inv => 0,
            in_clken_inv => 0,
            in_clken_mode => 1,
            in_rst_inv => 0,
            out_clk_inv => 0,
            out_clken_inv => 0,
            out_clken_mode => 1,
            out_rst_inv => 0)
        PORT MAP(
            in_clock_en => open,
            in_reset => open,
            out_clock_en => open,
            out_reset => open,
            in_clock => open);

    SCL_1(0):iocell
        GENERIC MAP(
            in_sync_mode => 2,
            out_sync_mode => 0,
            oe_sync_mode => 0,
            logicalport => "SCL_1",
            logicalport_pin_id => 0,
            io_capabilities => "0000000000000000000000000000000000000000000000000000000000000101")
        PORT MAP(
            pa_out => SCL_1(0)__PA,
            oe => open,
            fb => \I2C_1:Net_1109_0\,
            pin_input => \I2C_1:Net_643_0\,
            pad_out => SCL_1(0)_PAD,
            pad_in => SCL_1(0)_PAD,
            in_clock => ClockBlock_BUS_CLK,
            in_clock_en => '1',
            in_reset => '0',
            out_clock => open,
            out_clock_en => '1',
            out_reset => '0');

    SDA_1:logicalport
        GENERIC MAP(
            drive_mode => "100",
            ibuf_enabled => "1",
            id => "22863ebe-a37b-476f-b252-6e49a8c00b12",
            init_dr_st => "1",
            input_buffer_sel => "00",
            input_clk_en => 0,
            input_sync => "1",
            input_sync_mode => "0",
            intr_mode => "00",
            invert_in_clock => 0,
            invert_in_clock_en => 0,
            invert_in_reset => 0,
            invert_out_clock => 0,
            invert_out_clock_en => 0,
            invert_out_reset => 0,
            io_voltage => "",
            layout_mode => "CONTIGUOUS",
            oe_conn => "0",
            oe_reset => 0,
            oe_sync => "0",
            output_clk_en => 0,
            output_clock_mode => "0",
            output_conn => "0",
            output_mode => "0",
            output_reset => 0,
            output_sync => "0",
            ovt_hyst_trim => "0",
            ovt_needed => "0",
            ovt_slew_control => "00",
            pa_in_clock => -1,
            pa_in_clock_en => -1,
            pa_in_reset => -1,
            pa_out_clock => -1,
            pa_out_clock_en => -1,
            pa_out_reset => -1,
            pin_aliases => "",
            pin_mode => "B",
            por_state => 4,
            port_alias_group => "",
            port_alias_required => 0,
            sio_group_cnt => 0,
            sio_hifreq => "00000000",
            sio_hyst => "1",
            sio_ibuf => "00000000",
            sio_info => "00",
            sio_obuf => "00000000",
            sio_refsel => "00000000",
            sio_vohsel => "00000000",
            sio_vtrip => "00000000",
            slew_rate => "0",
            spanning => 0,
            sw_only => 0,
            use_annotation => "0",
            vtrip => "00",
            width => 1,
            in_clk_inv => 0,
            in_clken_inv => 0,
            in_clken_mode => 1,
            in_rst_inv => 0,
            out_clk_inv => 0,
            out_clken_inv => 0,
            out_clken_mode => 1,
            out_rst_inv => 0)
        PORT MAP(
            in_clock_en => open,
            in_reset => open,
            out_clock_en => open,
            out_reset => open,
            in_clock => open);

    SDA_1(0):iocell
        GENERIC MAP(
            in_sync_mode => 2,
            out_sync_mode => 0,
            oe_sync_mode => 0,
            logicalport => "SDA_1",
            logicalport_pin_id => 0,
            io_capabilities => "0000000000000000000000000000000000000000000000000000000000000101")
        PORT MAP(
            pa_out => SDA_1(0)__PA,
            oe => open,
            fb => \I2C_1:Net_1109_1\,
            pin_input => \I2C_1:sda_x_wire\,
            pad_out => SDA_1(0)_PAD,
            pad_in => SDA_1(0)_PAD,
            in_clock => ClockBlock_BUS_CLK,
            in_clock_en => '1',
            in_reset => '0',
            out_clock => open,
            out_clock_en => '1',
            out_reset => '0');

    \CDC:Dm\:logicalport
        GENERIC MAP(
            drive_mode => "000",
            ibuf_enabled => "0",
            id => "beca5e2d-f70f-4900-a4db-7eca1ed3126e/8b77a6c4-10a0-4390-971c-672353e2a49c",
            init_dr_st => "0",
            input_buffer_sel => "00",
            input_clk_en => 0,
            input_sync => "1",
            input_sync_mode => "0",
            intr_mode => "00",
            invert_in_clock => 0,
            invert_in_clock_en => 0,
            invert_in_reset => 0,
            invert_out_clock => 0,
            invert_out_clock_en => 0,
            invert_out_reset => 0,
            io_voltage => "",
            layout_mode => "NONCONTIGUOUS",
            oe_conn => "0",
            oe_reset => 0,
            oe_sync => "0",
            output_clk_en => 0,
            output_clock_mode => "0",
            output_conn => "0",
            output_mode => "0",
            output_reset => 0,
            output_sync => "0",
            ovt_hyst_trim => "0",
            ovt_needed => "0",
            ovt_slew_control => "00",
            pa_in_clock => -1,
            pa_in_clock_en => -1,
            pa_in_reset => -1,
            pa_out_clock => -1,
            pa_out_clock_en => -1,
            pa_out_reset => -1,
            pin_aliases => "",
            pin_mode => "A",
            por_state => 4,
            port_alias_group => "",
            port_alias_required => 0,
            sio_group_cnt => 0,
            sio_hifreq => "00000000",
            sio_hyst => "1",
            sio_ibuf => "00000000",
            sio_info => "00",
            sio_obuf => "00000000",
            sio_refsel => "00000000",
            sio_vohsel => "00000000",
            sio_vtrip => "00000000",
            slew_rate => "0",
            spanning => 1,
            sw_only => 0,
            use_annotation => "0",
            vtrip => "10",
            width => 1,
            in_clk_inv => 0,
            in_clken_inv => 0,
            in_clken_mode => 1,
            in_rst_inv => 0,
            out_clk_inv => 0,
            out_clken_inv => 0,
            out_clken_mode => 1,
            out_rst_inv => 0)
        PORT MAP(
            in_clock_en => open,
            in_reset => open,
            out_clock_en => open,
            out_reset => open);

    \CDC:Dm(0)\:iocell
        GENERIC MAP(
            in_sync_mode => 0,
            out_sync_mode => 0,
            oe_sync_mode => 0,
            logicalport => "\CDC:Dm\",
            logicalport_pin_id => 0,
            io_capabilities => "0000000000000000000000000000000000000000100000000000000000000000")
        PORT MAP(
            pa_out => \\\CDC:Dm(0)\\__PA\,
            oe => open,
            in_clock => open,
            in_clock_en => '1',
            in_reset => '0',
            out_clock => open,
            out_clock_en => '1',
            out_reset => '0');

    \CDC:Dp\:logicalport
        GENERIC MAP(
            drive_mode => "000",
            ibuf_enabled => "0",
            id => "beca5e2d-f70f-4900-a4db-7eca1ed3126e/618a72fc-5ddd-4df5-958f-a3d55102db42",
            init_dr_st => "1",
            input_buffer_sel => "00",
            input_clk_en => 0,
            input_sync => "1",
            input_sync_mode => "0",
            intr_mode => "10",
            invert_in_clock => 0,
            invert_in_clock_en => 0,
            invert_in_reset => 0,
            invert_out_clock => 0,
            invert_out_clock_en => 0,
            invert_out_reset => 0,
            io_voltage => "",
            layout_mode => "CONTIGUOUS",
            oe_conn => "0",
            oe_reset => 0,
            oe_sync => "0",
            output_clk_en => 0,
            output_clock_mode => "0",
            output_conn => "0",
            output_mode => "0",
            output_reset => 0,
            output_sync => "0",
            ovt_hyst_trim => "0",
            ovt_needed => "0",
            ovt_slew_control => "00",
            pa_in_clock => -1,
            pa_in_clock_en => -1,
            pa_in_reset => -1,
            pa_out_clock => -1,
            pa_out_clock_en => -1,
            pa_out_reset => -1,
            pin_aliases => "",
            pin_mode => "I",
            por_state => 4,
            port_alias_group => "",
            port_alias_required => 0,
            sio_group_cnt => 0,
            sio_hifreq => "00000000",
            sio_hyst => "1",
            sio_ibuf => "00000000",
            sio_info => "00",
            sio_obuf => "00000000",
            sio_refsel => "00000000",
            sio_vohsel => "00000000",
            sio_vtrip => "00000000",
            slew_rate => "0",
            spanning => 0,
            sw_only => 0,
            use_annotation => "0",
            vtrip => "00",
            width => 1,
            in_clk_inv => 0,
            in_clken_inv => 0,
            in_clken_mode => 1,
            in_rst_inv => 0,
            out_clk_inv => 0,
            out_clken_inv => 0,
            out_clken_mode => 1,
            out_rst_inv => 0)
        PORT MAP(
            in_clock_en => open,
            in_reset => open,
            out_clock_en => open,
            out_reset => open,
            interrupt => \CDC:Net_1010\,
            in_clock => open);

    \CDC:Dp(0)\:iocell
        GENERIC MAP(
            in_sync_mode => 2,
            out_sync_mode => 0,
            oe_sync_mode => 0,
            logicalport => "\CDC:Dp\",
            logicalport_pin_id => 0,
            io_capabilities => "0000000000000000000000000000000000000000010000000000000000000000")
        PORT MAP(
            pa_out => \\\CDC:Dp(0)\\__PA\,
            oe => open,
            in_clock => ClockBlock_BUS_CLK,
            in_clock_en => '1',
            in_reset => '0',
            out_clock => open,
            out_clock_en => '1',
            out_reset => '0');

    \I2C_1:I2C_IRQ\:interrupt
        GENERIC MAP(
            int_type => "00",
            is_nmi => 0)
        PORT MAP(
            interrupt => \I2C_1:Net_697\,
            clock => ClockBlock_BUS_CLK);

    \I2C_1:I2C_FF\:i2ccell
        GENERIC MAP(
            cy_registers => "",
            use_wakeup => 0)
        PORT MAP(
            clock => \ClockBlock.clk_bus_glb_ff__sig\,
            scl_in => \I2C_1:Net_1109_0\,
            sda_in => \I2C_1:Net_1109_1\,
            scl_out => \I2C_1:Net_643_0\,
            sda_out => \I2C_1:sda_x_wire\,
            interrupt => \I2C_1:Net_697\);

    \CDC:dp_int\:interrupt
        GENERIC MAP(
            int_type => "10",
            is_nmi => 0)
        PORT MAP(
            interrupt => \CDC:Net_1010\,
            clock => ClockBlock_BUS_CLK);

    \CDC:USB\:usbcell
        GENERIC MAP(
            cy_registers => "")
        PORT MAP(
            sof_int => Net_12,
            arb_int => \CDC:Net_1889\,
            usb_int => \CDC:Net_1876\,
            ept_int_8 => \CDC:ep_int_8\,
            ept_int_7 => \CDC:ep_int_7\,
            ept_int_6 => \CDC:ep_int_6\,
            ept_int_5 => \CDC:ep_int_5\,
            ept_int_4 => \CDC:ep_int_4\,
            ept_int_3 => \CDC:ep_int_3\,
            ept_int_2 => \CDC:ep_int_2\,
            ept_int_1 => \CDC:ep_int_1\,
            ept_int_0 => \CDC:ep_int_0\,
            ord_int => \CDC:Net_95\,
            dma_req_7 => \CDC:dma_request_7\,
            dma_req_6 => \CDC:dma_request_6\,
            dma_req_5 => \CDC:dma_request_5\,
            dma_req_4 => \CDC:dma_request_4\,
            dma_req_3 => \CDC:dma_request_3\,
            dma_req_2 => \CDC:dma_request_2\,
            dma_req_1 => \CDC:dma_request_1\,
            dma_req_0 => \CDC:dma_request_0\,
            dma_termin => \CDC:dma_terminate\);

    \CDC:ep_3\:interrupt
        GENERIC MAP(
            int_type => "10",
            is_nmi => 0)
        PORT MAP(
            interrupt => \CDC:ep_int_3\,
            clock => ClockBlock_BUS_CLK);

    \CDC:ep_2\:interrupt
        GENERIC MAP(
            int_type => "10",
            is_nmi => 0)
        PORT MAP(
            interrupt => \CDC:ep_int_2\,
            clock => ClockBlock_BUS_CLK);

    \CDC:ep_1\:interrupt
        GENERIC MAP(
            int_type => "10",
            is_nmi => 0)
        PORT MAP(
            interrupt => \CDC:ep_int_1\,
            clock => ClockBlock_BUS_CLK);

    \CDC:ep_0\:interrupt
        GENERIC MAP(
            int_type => "10",
            is_nmi => 0)
        PORT MAP(
            interrupt => \CDC:ep_int_0\,
            clock => ClockBlock_BUS_CLK);

    \CDC:bus_reset\:interrupt
        GENERIC MAP(
            int_type => "10",
            is_nmi => 0)
        PORT MAP(
            interrupt => \CDC:Net_1876\,
            clock => ClockBlock_BUS_CLK);

    \CDC:arb_int\:interrupt
        GENERIC MAP(
            int_type => "10",
            is_nmi => 0)
        PORT MAP(
            interrupt => \CDC:Net_1889\,
            clock => ClockBlock_BUS_CLK);

    \CDC:sof_int\:interrupt
        GENERIC MAP(
            int_type => "10",
            is_nmi => 0)
        PORT MAP(
            interrupt => Net_12,
            clock => ClockBlock_BUS_CLK);

END __DEFAULT__;
