--
--	Conversion of VCNL4030X01.v to vh2:
--
--	Cypress Semiconductor - WARP Version 6.3 IR 41
--	Tue Jul 27 22:59:30 2021
--

USE cypress.cypress.all;
USE cypress.rtlpkg.all;
ENTITY top_RTL IS
ATTRIBUTE part_name of top_RTL:TYPE IS "cpsoc3";
END top_RTL;
--------------------------------------------------------
ARCHITECTURE R_T_L OF top_RTL IS
SIGNAL \I2C_1:sda_x_wire\ : bit;
SIGNAL \I2C_1:Net_643_1\ : bit;
SIGNAL \I2C_1:Net_697\ : bit;
SIGNAL \I2C_1:bus_clk\ : bit;
SIGNAL \I2C_1:Net_1109_0\ : bit;
SIGNAL \I2C_1:Net_1109_1\ : bit;
SIGNAL \I2C_1:Net_643_0\ : bit;
SIGNAL \I2C_1:Net_643_2\ : bit;
SIGNAL \I2C_1:scl_x_wire\ : bit;
SIGNAL \I2C_1:Net_969\ : bit;
SIGNAL \I2C_1:Net_968\ : bit;
SIGNAL \I2C_1:udb_clk\ : bit;
SIGNAL Net_5 : bit;
SIGNAL \I2C_1:Net_973\ : bit;
SIGNAL Net_6 : bit;
SIGNAL \I2C_1:Net_974\ : bit;
SIGNAL \I2C_1:scl_yfb\ : bit;
SIGNAL \I2C_1:sda_yfb\ : bit;
SIGNAL \I2C_1:tmpOE__Bufoe_scl_net_0\ : bit;
SIGNAL Net_2 : bit;
SIGNAL \I2C_1:tmpOE__Bufoe_sda_net_0\ : bit;
SIGNAL Net_1 : bit;
SIGNAL \I2C_1:timeout_clk\ : bit;
SIGNAL Net_11 : bit;
SIGNAL \I2C_1:Net_975\ : bit;
SIGNAL Net_9 : bit;
SIGNAL Net_10 : bit;
SIGNAL tmpOE__SCL_1_net_0 : bit;
SIGNAL zero : bit;
SIGNAL tmpFB_0__SCL_1_net_0 : bit;
TERMINAL tmpSIOVREF__SCL_1_net_0 : bit;
SIGNAL one : bit;
SIGNAL tmpINTERRUPT_0__SCL_1_net_0 : bit;
SIGNAL tmpOE__SDA_1_net_0 : bit;
SIGNAL tmpFB_0__SDA_1_net_0 : bit;
TERMINAL tmpSIOVREF__SDA_1_net_0 : bit;
SIGNAL tmpINTERRUPT_0__SDA_1_net_0 : bit;
SIGNAL \CDC:Net_1010\ : bit;
SIGNAL \CDC:tmpOE__Dm_net_0\ : bit;
SIGNAL \CDC:tmpFB_0__Dm_net_0\ : bit;
TERMINAL \CDC:Net_597\ : bit;
SIGNAL \CDC:tmpIO_0__Dm_net_0\ : bit;
TERMINAL \CDC:tmpSIOVREF__Dm_net_0\ : bit;
SIGNAL \CDC:tmpINTERRUPT_0__Dm_net_0\ : bit;
SIGNAL \CDC:tmpOE__Dp_net_0\ : bit;
SIGNAL \CDC:tmpFB_0__Dp_net_0\ : bit;
TERMINAL \CDC:Net_1000\ : bit;
SIGNAL \CDC:tmpIO_0__Dp_net_0\ : bit;
TERMINAL \CDC:tmpSIOVREF__Dp_net_0\ : bit;
SIGNAL Net_12 : bit;
SIGNAL \CDC:Net_1889\ : bit;
SIGNAL \CDC:Net_1876\ : bit;
SIGNAL \CDC:ep_int_8\ : bit;
SIGNAL \CDC:ep_int_7\ : bit;
SIGNAL \CDC:ep_int_6\ : bit;
SIGNAL \CDC:ep_int_5\ : bit;
SIGNAL \CDC:ep_int_4\ : bit;
SIGNAL \CDC:ep_int_3\ : bit;
SIGNAL \CDC:ep_int_2\ : bit;
SIGNAL \CDC:ep_int_1\ : bit;
SIGNAL \CDC:ep_int_0\ : bit;
SIGNAL \CDC:Net_95\ : bit;
SIGNAL \CDC:dma_request_7\ : bit;
SIGNAL \CDC:dma_request_6\ : bit;
SIGNAL \CDC:dma_request_5\ : bit;
SIGNAL \CDC:dma_request_4\ : bit;
SIGNAL \CDC:dma_request_3\ : bit;
SIGNAL \CDC:dma_request_2\ : bit;
SIGNAL \CDC:dma_request_1\ : bit;
SIGNAL \CDC:dma_request_0\ : bit;
SIGNAL \CDC:dma_terminate\ : bit;
SIGNAL \CDC:dma_complete_0\ : bit;
SIGNAL \CDC:Net_1922\ : bit;
SIGNAL \CDC:dma_complete_1\ : bit;
SIGNAL \CDC:Net_1921\ : bit;
SIGNAL \CDC:dma_complete_2\ : bit;
SIGNAL \CDC:Net_1920\ : bit;
SIGNAL \CDC:dma_complete_3\ : bit;
SIGNAL \CDC:Net_1919\ : bit;
SIGNAL \CDC:dma_complete_4\ : bit;
SIGNAL \CDC:Net_1918\ : bit;
SIGNAL \CDC:dma_complete_5\ : bit;
SIGNAL \CDC:Net_1917\ : bit;
SIGNAL \CDC:dma_complete_6\ : bit;
SIGNAL \CDC:Net_1916\ : bit;
SIGNAL \CDC:dma_complete_7\ : bit;
SIGNAL \CDC:Net_1915\ : bit;
BEGIN

zero <=  ('0') ;

tmpOE__SCL_1_net_0 <=  ('1') ;

\I2C_1:I2C_IRQ\:cy_isr_v1_0
	GENERIC MAP(int_type=>"00",
		is_nmi=>'0')
	PORT MAP(int_signal=>\I2C_1:Net_697\);
\I2C_1:I2C_FF\:cy_psoc3_i2c_v1_0
	GENERIC MAP(cy_registers=>"",
		use_wakeup=>'0')
	PORT MAP(clock=>\I2C_1:bus_clk\,
		scl_in=>\I2C_1:Net_1109_0\,
		sda_in=>\I2C_1:Net_1109_1\,
		scl_out=>\I2C_1:Net_643_0\,
		sda_out=>\I2C_1:sda_x_wire\,
		interrupt=>\I2C_1:Net_697\);
\I2C_1:BusClock\:cy_clock_v1_0
	GENERIC MAP(cy_registers=>"",
		id=>"6f2d57bd-b6d0-4115-93da-ded3485bf4ed/5ece924d-20ba-480e-9102-bc082dcdd926",
		source_clock_id=>"75C2148C-3656-4d8a-846D-0CAE99AB6FF7",
		divisor=>0,
		period=>"0",
		is_direct=>'1',
		is_digital=>'1')
	PORT MAP(clock_out=>\I2C_1:bus_clk\,
		dig_domain_out=>open);
\I2C_1:Bufoe_scl\:cy_bufoe
	PORT MAP(x=>\I2C_1:Net_643_0\,
		oe=>tmpOE__SCL_1_net_0,
		y=>Net_2,
		yfb=>\I2C_1:Net_1109_0\);
\I2C_1:Bufoe_sda\:cy_bufoe
	PORT MAP(x=>\I2C_1:sda_x_wire\,
		oe=>tmpOE__SCL_1_net_0,
		y=>Net_1,
		yfb=>\I2C_1:Net_1109_1\);
SCL_1:cy_psoc3_pins_v1_10
	GENERIC MAP(id=>"02f2cf2c-2c7a-49df-9246-7a3435c21be3",
		drive_mode=>"100",
		ibuf_enabled=>"1",
		init_dr_st=>"1",
		input_sync=>"1",
		input_clk_en=>'0',
		input_sync_mode=>"0",
		intr_mode=>"00",
		invert_in_clock=>'0',
		invert_in_clock_en=>'0',
		invert_in_reset=>'0',
		invert_out_clock=>'0',
		invert_out_clock_en=>'0',
		invert_out_reset=>'0',
		io_voltage=>"",
		layout_mode=>"CONTIGUOUS",
		output_conn=>"0",
		output_sync=>"0",
		output_clk_en=>'0',
		output_mode=>"0",
		output_reset=>'0',
		output_clock_mode=>"0",
		oe_sync=>"0",
		oe_conn=>"0",
		oe_reset=>'0',
		pin_aliases=>"",
		pin_mode=>"B",
		por_state=>4,
		sio_group_cnt=>0,
		sio_hifreq=>"00000000",
		sio_hyst=>"1",
		sio_ibuf=>"00000000",
		sio_info=>"00",
		sio_obuf=>"00000000",
		sio_refsel=>"00000000",
		sio_vtrip=>"00000000",
		sio_vohsel=>"00000000",
		slew_rate=>"0",
		spanning=>'0',
		sw_only=>'0',
		vtrip=>"00",
		width=>1,
		port_alias_required=>'0',
		port_alias_group=>"",
		use_annotation=>"0",
		pa_in_clock=>-1,
		pa_in_clock_en=>-1,
		pa_in_reset=>-1,
		pa_out_clock=>-1,
		pa_out_clock_en=>-1,
		pa_out_reset=>-1,
		ovt_needed=>"0",
		ovt_slew_control=>"00",
		ovt_hyst_trim=>"0",
		input_buffer_sel=>"00")
	PORT MAP(oe=>(tmpOE__SCL_1_net_0),
		y=>(zero),
		fb=>(tmpFB_0__SCL_1_net_0),
		analog=>(open),
		io=>Net_2,
		siovref=>(tmpSIOVREF__SCL_1_net_0),
		annotation=>(open),
		in_clock=>zero,
		in_clock_en=>tmpOE__SCL_1_net_0,
		in_reset=>zero,
		out_clock=>zero,
		out_clock_en=>tmpOE__SCL_1_net_0,
		out_reset=>zero,
		interrupt=>tmpINTERRUPT_0__SCL_1_net_0);
SDA_1:cy_psoc3_pins_v1_10
	GENERIC MAP(id=>"22863ebe-a37b-476f-b252-6e49a8c00b12",
		drive_mode=>"100",
		ibuf_enabled=>"1",
		init_dr_st=>"1",
		input_sync=>"1",
		input_clk_en=>'0',
		input_sync_mode=>"0",
		intr_mode=>"00",
		invert_in_clock=>'0',
		invert_in_clock_en=>'0',
		invert_in_reset=>'0',
		invert_out_clock=>'0',
		invert_out_clock_en=>'0',
		invert_out_reset=>'0',
		io_voltage=>"",
		layout_mode=>"CONTIGUOUS",
		output_conn=>"0",
		output_sync=>"0",
		output_clk_en=>'0',
		output_mode=>"0",
		output_reset=>'0',
		output_clock_mode=>"0",
		oe_sync=>"0",
		oe_conn=>"0",
		oe_reset=>'0',
		pin_aliases=>"",
		pin_mode=>"B",
		por_state=>4,
		sio_group_cnt=>0,
		sio_hifreq=>"00000000",
		sio_hyst=>"1",
		sio_ibuf=>"00000000",
		sio_info=>"00",
		sio_obuf=>"00000000",
		sio_refsel=>"00000000",
		sio_vtrip=>"00000000",
		sio_vohsel=>"00000000",
		slew_rate=>"0",
		spanning=>'0',
		sw_only=>'0',
		vtrip=>"00",
		width=>1,
		port_alias_required=>'0',
		port_alias_group=>"",
		use_annotation=>"0",
		pa_in_clock=>-1,
		pa_in_clock_en=>-1,
		pa_in_reset=>-1,
		pa_out_clock=>-1,
		pa_out_clock_en=>-1,
		pa_out_reset=>-1,
		ovt_needed=>"0",
		ovt_slew_control=>"00",
		ovt_hyst_trim=>"0",
		input_buffer_sel=>"00")
	PORT MAP(oe=>(tmpOE__SCL_1_net_0),
		y=>(zero),
		fb=>(tmpFB_0__SDA_1_net_0),
		analog=>(open),
		io=>Net_1,
		siovref=>(tmpSIOVREF__SDA_1_net_0),
		annotation=>(open),
		in_clock=>zero,
		in_clock_en=>tmpOE__SCL_1_net_0,
		in_reset=>zero,
		out_clock=>zero,
		out_clock_en=>tmpOE__SCL_1_net_0,
		out_reset=>zero,
		interrupt=>tmpINTERRUPT_0__SDA_1_net_0);
\CDC:dp_int\:cy_isr_v1_0
	GENERIC MAP(int_type=>"10",
		is_nmi=>'0')
	PORT MAP(int_signal=>\CDC:Net_1010\);
\CDC:Dm\:cy_psoc3_pins_v1_10
	GENERIC MAP(id=>"beca5e2d-f70f-4900-a4db-7eca1ed3126e/8b77a6c4-10a0-4390-971c-672353e2a49c",
		drive_mode=>"000",
		ibuf_enabled=>"0",
		init_dr_st=>"0",
		input_sync=>"1",
		input_clk_en=>'0',
		input_sync_mode=>"0",
		intr_mode=>"00",
		invert_in_clock=>'0',
		invert_in_clock_en=>'0',
		invert_in_reset=>'0',
		invert_out_clock=>'0',
		invert_out_clock_en=>'0',
		invert_out_reset=>'0',
		io_voltage=>"",
		layout_mode=>"NONCONTIGUOUS",
		output_conn=>"0",
		output_sync=>"0",
		output_clk_en=>'0',
		output_mode=>"0",
		output_reset=>'0',
		output_clock_mode=>"0",
		oe_sync=>"0",
		oe_conn=>"0",
		oe_reset=>'0',
		pin_aliases=>"",
		pin_mode=>"A",
		por_state=>4,
		sio_group_cnt=>0,
		sio_hifreq=>"00000000",
		sio_hyst=>"1",
		sio_ibuf=>"00000000",
		sio_info=>"00",
		sio_obuf=>"00000000",
		sio_refsel=>"00000000",
		sio_vtrip=>"00000000",
		sio_vohsel=>"00000000",
		slew_rate=>"0",
		spanning=>'1',
		sw_only=>'0',
		vtrip=>"10",
		width=>1,
		port_alias_required=>'0',
		port_alias_group=>"",
		use_annotation=>"0",
		pa_in_clock=>-1,
		pa_in_clock_en=>-1,
		pa_in_reset=>-1,
		pa_out_clock=>-1,
		pa_out_clock_en=>-1,
		pa_out_reset=>-1,
		ovt_needed=>"0",
		ovt_slew_control=>"00",
		ovt_hyst_trim=>"0",
		input_buffer_sel=>"00")
	PORT MAP(oe=>(tmpOE__SCL_1_net_0),
		y=>(zero),
		fb=>(\CDC:tmpFB_0__Dm_net_0\),
		analog=>\CDC:Net_597\,
		io=>(\CDC:tmpIO_0__Dm_net_0\),
		siovref=>(\CDC:tmpSIOVREF__Dm_net_0\),
		annotation=>(open),
		in_clock=>zero,
		in_clock_en=>tmpOE__SCL_1_net_0,
		in_reset=>zero,
		out_clock=>zero,
		out_clock_en=>tmpOE__SCL_1_net_0,
		out_reset=>zero,
		interrupt=>\CDC:tmpINTERRUPT_0__Dm_net_0\);
\CDC:Dp\:cy_psoc3_pins_v1_10
	GENERIC MAP(id=>"beca5e2d-f70f-4900-a4db-7eca1ed3126e/618a72fc-5ddd-4df5-958f-a3d55102db42",
		drive_mode=>"000",
		ibuf_enabled=>"0",
		init_dr_st=>"1",
		input_sync=>"1",
		input_clk_en=>'0',
		input_sync_mode=>"0",
		intr_mode=>"10",
		invert_in_clock=>'0',
		invert_in_clock_en=>'0',
		invert_in_reset=>'0',
		invert_out_clock=>'0',
		invert_out_clock_en=>'0',
		invert_out_reset=>'0',
		io_voltage=>"",
		layout_mode=>"CONTIGUOUS",
		output_conn=>"0",
		output_sync=>"0",
		output_clk_en=>'0',
		output_mode=>"0",
		output_reset=>'0',
		output_clock_mode=>"0",
		oe_sync=>"0",
		oe_conn=>"0",
		oe_reset=>'0',
		pin_aliases=>"",
		pin_mode=>"I",
		por_state=>4,
		sio_group_cnt=>0,
		sio_hifreq=>"00000000",
		sio_hyst=>"1",
		sio_ibuf=>"00000000",
		sio_info=>"00",
		sio_obuf=>"00000000",
		sio_refsel=>"00000000",
		sio_vtrip=>"00000000",
		sio_vohsel=>"00000000",
		slew_rate=>"0",
		spanning=>'0',
		sw_only=>'0',
		vtrip=>"00",
		width=>1,
		port_alias_required=>'0',
		port_alias_group=>"",
		use_annotation=>"0",
		pa_in_clock=>-1,
		pa_in_clock_en=>-1,
		pa_in_reset=>-1,
		pa_out_clock=>-1,
		pa_out_clock_en=>-1,
		pa_out_reset=>-1,
		ovt_needed=>"0",
		ovt_slew_control=>"00",
		ovt_hyst_trim=>"0",
		input_buffer_sel=>"00")
	PORT MAP(oe=>(tmpOE__SCL_1_net_0),
		y=>(zero),
		fb=>(\CDC:tmpFB_0__Dp_net_0\),
		analog=>\CDC:Net_1000\,
		io=>(\CDC:tmpIO_0__Dp_net_0\),
		siovref=>(\CDC:tmpSIOVREF__Dp_net_0\),
		annotation=>(open),
		in_clock=>zero,
		in_clock_en=>tmpOE__SCL_1_net_0,
		in_reset=>zero,
		out_clock=>zero,
		out_clock_en=>tmpOE__SCL_1_net_0,
		out_reset=>zero,
		interrupt=>\CDC:Net_1010\);
\CDC:USB\:cy_psoc3_usb_v1_0
	GENERIC MAP(cy_registers=>"")
	PORT MAP(dp=>\CDC:Net_1000\,
		dm=>\CDC:Net_597\,
		sof_int=>Net_12,
		arb_int=>\CDC:Net_1889\,
		usb_int=>\CDC:Net_1876\,
		ept_int=>(\CDC:ep_int_8\, \CDC:ep_int_7\, \CDC:ep_int_6\, \CDC:ep_int_5\,
			\CDC:ep_int_4\, \CDC:ep_int_3\, \CDC:ep_int_2\, \CDC:ep_int_1\,
			\CDC:ep_int_0\),
		ord_int=>\CDC:Net_95\,
		dma_req=>(\CDC:dma_request_7\, \CDC:dma_request_6\, \CDC:dma_request_5\, \CDC:dma_request_4\,
			\CDC:dma_request_3\, \CDC:dma_request_2\, \CDC:dma_request_1\, \CDC:dma_request_0\),
		dma_termin=>\CDC:dma_terminate\);
\CDC:ep_3\:cy_isr_v1_0
	GENERIC MAP(int_type=>"10",
		is_nmi=>'0')
	PORT MAP(int_signal=>\CDC:ep_int_3\);
\CDC:ep_2\:cy_isr_v1_0
	GENERIC MAP(int_type=>"10",
		is_nmi=>'0')
	PORT MAP(int_signal=>\CDC:ep_int_2\);
\CDC:ep_1\:cy_isr_v1_0
	GENERIC MAP(int_type=>"10",
		is_nmi=>'0')
	PORT MAP(int_signal=>\CDC:ep_int_1\);
\CDC:ep_0\:cy_isr_v1_0
	GENERIC MAP(int_type=>"10",
		is_nmi=>'0')
	PORT MAP(int_signal=>\CDC:ep_int_0\);
\CDC:bus_reset\:cy_isr_v1_0
	GENERIC MAP(int_type=>"10",
		is_nmi=>'0')
	PORT MAP(int_signal=>\CDC:Net_1876\);
\CDC:arb_int\:cy_isr_v1_0
	GENERIC MAP(int_type=>"10",
		is_nmi=>'0')
	PORT MAP(int_signal=>\CDC:Net_1889\);
\CDC:sof_int\:cy_isr_v1_0
	GENERIC MAP(int_type=>"10",
		is_nmi=>'0')
	PORT MAP(int_signal=>Net_12);

END R_T_L;
