ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 1


   1              		.syntax unified
   2              		.cpu cortex-m3
   3              		.fpu softvfp
   4              		.eabi_attribute 20, 1
   5              		.eabi_attribute 21, 1
   6              		.eabi_attribute 23, 3
   7              		.eabi_attribute 24, 1
   8              		.eabi_attribute 25, 1
   9              		.eabi_attribute 26, 1
  10              		.eabi_attribute 30, 1
  11              		.eabi_attribute 34, 1
  12              		.eabi_attribute 18, 4
  13              		.thumb
  14              		.syntax unified
  15              		.file	"I2C_1_INT.c"
  16              		.text
  17              	.Ltext0:
  18              		.cfi_sections	.debug_frame
  19              		.section	.text.I2C_1_ISR,"ax",%progbits
  20              		.align	2
  21              		.global	I2C_1_ISR
  22              		.thumb
  23              		.thumb_func
  24              		.type	I2C_1_ISR, %function
  25              	I2C_1_ISR:
  26              	.LFB0:
  27              		.file 1 "Generated_Source\\PSoC5\\I2C_1_INT.c"
   1:Generated_Source\PSoC5/I2C_1_INT.c **** /*******************************************************************************
   2:Generated_Source\PSoC5/I2C_1_INT.c **** * File Name: I2C_1_INT.c
   3:Generated_Source\PSoC5/I2C_1_INT.c **** * Version 3.50
   4:Generated_Source\PSoC5/I2C_1_INT.c **** *
   5:Generated_Source\PSoC5/I2C_1_INT.c **** * Description:
   6:Generated_Source\PSoC5/I2C_1_INT.c **** *  This file provides the source code of Interrupt Service Routine (ISR)
   7:Generated_Source\PSoC5/I2C_1_INT.c **** *  for the I2C component.
   8:Generated_Source\PSoC5/I2C_1_INT.c **** *
   9:Generated_Source\PSoC5/I2C_1_INT.c **** ********************************************************************************
  10:Generated_Source\PSoC5/I2C_1_INT.c **** * Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
  11:Generated_Source\PSoC5/I2C_1_INT.c **** * You may use this file only in accordance with the license, terms, conditions,
  12:Generated_Source\PSoC5/I2C_1_INT.c **** * disclaimers, and limitations in the end user license agreement accompanying
  13:Generated_Source\PSoC5/I2C_1_INT.c **** * the software package with which this file was provided.
  14:Generated_Source\PSoC5/I2C_1_INT.c **** *******************************************************************************/
  15:Generated_Source\PSoC5/I2C_1_INT.c **** 
  16:Generated_Source\PSoC5/I2C_1_INT.c **** #include "I2C_1_PVT.h"
  17:Generated_Source\PSoC5/I2C_1_INT.c **** #include "cyapicallbacks.h"
  18:Generated_Source\PSoC5/I2C_1_INT.c **** 
  19:Generated_Source\PSoC5/I2C_1_INT.c **** 
  20:Generated_Source\PSoC5/I2C_1_INT.c **** /*******************************************************************************
  21:Generated_Source\PSoC5/I2C_1_INT.c **** *  Place your includes, defines and code here.
  22:Generated_Source\PSoC5/I2C_1_INT.c **** ********************************************************************************/
  23:Generated_Source\PSoC5/I2C_1_INT.c **** /* `#START I2C_1_ISR_intc` */
  24:Generated_Source\PSoC5/I2C_1_INT.c **** 
  25:Generated_Source\PSoC5/I2C_1_INT.c **** /* `#END` */
  26:Generated_Source\PSoC5/I2C_1_INT.c **** 
  27:Generated_Source\PSoC5/I2C_1_INT.c **** 
  28:Generated_Source\PSoC5/I2C_1_INT.c **** /*******************************************************************************
  29:Generated_Source\PSoC5/I2C_1_INT.c **** * Function Name: I2C_1_ISR
  30:Generated_Source\PSoC5/I2C_1_INT.c **** ********************************************************************************
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 2


  31:Generated_Source\PSoC5/I2C_1_INT.c **** *
  32:Generated_Source\PSoC5/I2C_1_INT.c **** * Summary:
  33:Generated_Source\PSoC5/I2C_1_INT.c **** *  The handler for the I2C interrupt. The slave and master operations are
  34:Generated_Source\PSoC5/I2C_1_INT.c **** *  handled here.
  35:Generated_Source\PSoC5/I2C_1_INT.c **** *
  36:Generated_Source\PSoC5/I2C_1_INT.c **** * Parameters:
  37:Generated_Source\PSoC5/I2C_1_INT.c **** *  None.
  38:Generated_Source\PSoC5/I2C_1_INT.c **** *
  39:Generated_Source\PSoC5/I2C_1_INT.c **** * Return:
  40:Generated_Source\PSoC5/I2C_1_INT.c **** *  None.
  41:Generated_Source\PSoC5/I2C_1_INT.c **** *
  42:Generated_Source\PSoC5/I2C_1_INT.c **** * Reentrant:
  43:Generated_Source\PSoC5/I2C_1_INT.c **** *  No.
  44:Generated_Source\PSoC5/I2C_1_INT.c **** *
  45:Generated_Source\PSoC5/I2C_1_INT.c **** *******************************************************************************/
  46:Generated_Source\PSoC5/I2C_1_INT.c **** CY_ISR(I2C_1_ISR)
  47:Generated_Source\PSoC5/I2C_1_INT.c **** {
  28              		.loc 1 47 0
  29              		.cfi_startproc
  30              		@ args = 0, pretend = 0, frame = 0
  31              		@ frame_needed = 0, uses_anonymous_args = 0
  32 0000 38B5     		push	{r3, r4, r5, lr}
  33              		.cfi_def_cfa_offset 16
  34              		.cfi_offset 3, -16
  35              		.cfi_offset 4, -12
  36              		.cfi_offset 5, -8
  37              		.cfi_offset 14, -4
  48:Generated_Source\PSoC5/I2C_1_INT.c **** #if (I2C_1_MODE_SLAVE_ENABLED)
  49:Generated_Source\PSoC5/I2C_1_INT.c ****    uint8  tmp8;
  50:Generated_Source\PSoC5/I2C_1_INT.c **** #endif  /* (I2C_1_MODE_SLAVE_ENABLED) */
  51:Generated_Source\PSoC5/I2C_1_INT.c **** 
  52:Generated_Source\PSoC5/I2C_1_INT.c ****     uint8  tmpCsr;
  53:Generated_Source\PSoC5/I2C_1_INT.c ****     
  54:Generated_Source\PSoC5/I2C_1_INT.c **** #ifdef I2C_1_ISR_ENTRY_CALLBACK
  55:Generated_Source\PSoC5/I2C_1_INT.c ****     I2C_1_ISR_EntryCallback();
  56:Generated_Source\PSoC5/I2C_1_INT.c **** #endif /* I2C_1_ISR_ENTRY_CALLBACK */
  57:Generated_Source\PSoC5/I2C_1_INT.c ****     
  58:Generated_Source\PSoC5/I2C_1_INT.c **** 
  59:Generated_Source\PSoC5/I2C_1_INT.c **** #if(I2C_1_TIMEOUT_FF_ENABLED)
  60:Generated_Source\PSoC5/I2C_1_INT.c ****     if(0u != I2C_1_TimeoutGetStatus())
  61:Generated_Source\PSoC5/I2C_1_INT.c ****     {
  62:Generated_Source\PSoC5/I2C_1_INT.c ****         I2C_1_TimeoutReset();
  63:Generated_Source\PSoC5/I2C_1_INT.c ****         I2C_1_state = I2C_1_SM_EXIT_IDLE;
  64:Generated_Source\PSoC5/I2C_1_INT.c ****         /* I2C_1_CSR_REG should be cleared after reset */
  65:Generated_Source\PSoC5/I2C_1_INT.c ****     }
  66:Generated_Source\PSoC5/I2C_1_INT.c **** #endif /* (I2C_1_TIMEOUT_FF_ENABLED) */
  67:Generated_Source\PSoC5/I2C_1_INT.c **** 
  68:Generated_Source\PSoC5/I2C_1_INT.c **** 
  69:Generated_Source\PSoC5/I2C_1_INT.c ****     tmpCsr = I2C_1_CSR_REG;      /* Make copy as interrupts clear */
  38              		.loc 1 69 0
  39 0002 A54B     		ldr	r3, .L27
  40 0004 1C78     		ldrb	r4, [r3]	@ zero_extendqisi2
  41              	.LVL0:
  70:Generated_Source\PSoC5/I2C_1_INT.c **** 
  71:Generated_Source\PSoC5/I2C_1_INT.c **** #if(I2C_1_MODE_MULTI_MASTER_SLAVE_ENABLED)
  72:Generated_Source\PSoC5/I2C_1_INT.c ****     if(I2C_1_CHECK_START_GEN(I2C_1_MCSR_REG))
  73:Generated_Source\PSoC5/I2C_1_INT.c ****     {
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 3


  74:Generated_Source\PSoC5/I2C_1_INT.c ****         I2C_1_CLEAR_START_GEN;
  75:Generated_Source\PSoC5/I2C_1_INT.c **** 
  76:Generated_Source\PSoC5/I2C_1_INT.c ****         /* Set transfer complete and error flags */
  77:Generated_Source\PSoC5/I2C_1_INT.c ****         I2C_1_mstrStatus |= (I2C_1_MSTAT_ERR_XFER |
  78:Generated_Source\PSoC5/I2C_1_INT.c ****                                         I2C_1_GET_MSTAT_CMPLT);
  79:Generated_Source\PSoC5/I2C_1_INT.c **** 
  80:Generated_Source\PSoC5/I2C_1_INT.c ****         /* Slave was addressed */
  81:Generated_Source\PSoC5/I2C_1_INT.c ****         I2C_1_state = I2C_1_SM_SLAVE;
  82:Generated_Source\PSoC5/I2C_1_INT.c ****     }
  83:Generated_Source\PSoC5/I2C_1_INT.c **** #endif /* (I2C_1_MODE_MULTI_MASTER_SLAVE_ENABLED) */
  84:Generated_Source\PSoC5/I2C_1_INT.c **** 
  85:Generated_Source\PSoC5/I2C_1_INT.c **** 
  86:Generated_Source\PSoC5/I2C_1_INT.c **** #if(I2C_1_MODE_MULTI_MASTER_ENABLED)
  87:Generated_Source\PSoC5/I2C_1_INT.c ****     if(I2C_1_CHECK_LOST_ARB(tmpCsr))
  88:Generated_Source\PSoC5/I2C_1_INT.c ****     {
  89:Generated_Source\PSoC5/I2C_1_INT.c ****         /* Set errors */
  90:Generated_Source\PSoC5/I2C_1_INT.c ****         I2C_1_mstrStatus |= (I2C_1_MSTAT_ERR_XFER     |
  91:Generated_Source\PSoC5/I2C_1_INT.c ****                                         I2C_1_MSTAT_ERR_ARB_LOST |
  92:Generated_Source\PSoC5/I2C_1_INT.c ****                                         I2C_1_GET_MSTAT_CMPLT);
  93:Generated_Source\PSoC5/I2C_1_INT.c **** 
  94:Generated_Source\PSoC5/I2C_1_INT.c ****         I2C_1_DISABLE_INT_ON_STOP; /* Interrupt on Stop is enabled by write */
  95:Generated_Source\PSoC5/I2C_1_INT.c **** 
  96:Generated_Source\PSoC5/I2C_1_INT.c ****         #if(I2C_1_MODE_MULTI_MASTER_SLAVE_ENABLED)
  97:Generated_Source\PSoC5/I2C_1_INT.c ****             if(I2C_1_CHECK_ADDRESS_STS(tmpCsr))
  98:Generated_Source\PSoC5/I2C_1_INT.c ****             {
  99:Generated_Source\PSoC5/I2C_1_INT.c ****                 /* Slave was addressed */
 100:Generated_Source\PSoC5/I2C_1_INT.c ****                 I2C_1_state = I2C_1_SM_SLAVE;
 101:Generated_Source\PSoC5/I2C_1_INT.c ****             }
 102:Generated_Source\PSoC5/I2C_1_INT.c ****             else
 103:Generated_Source\PSoC5/I2C_1_INT.c ****             {
 104:Generated_Source\PSoC5/I2C_1_INT.c ****                 I2C_1_BUS_RELEASE;
 105:Generated_Source\PSoC5/I2C_1_INT.c **** 
 106:Generated_Source\PSoC5/I2C_1_INT.c ****                 I2C_1_state = I2C_1_SM_EXIT_IDLE;
 107:Generated_Source\PSoC5/I2C_1_INT.c ****             }
 108:Generated_Source\PSoC5/I2C_1_INT.c ****         #else
 109:Generated_Source\PSoC5/I2C_1_INT.c ****             I2C_1_BUS_RELEASE;
 110:Generated_Source\PSoC5/I2C_1_INT.c **** 
 111:Generated_Source\PSoC5/I2C_1_INT.c ****             I2C_1_state = I2C_1_SM_EXIT_IDLE;
 112:Generated_Source\PSoC5/I2C_1_INT.c **** 
 113:Generated_Source\PSoC5/I2C_1_INT.c ****         #endif /* (I2C_1_MODE_MULTI_MASTER_SLAVE_ENABLED) */
 114:Generated_Source\PSoC5/I2C_1_INT.c ****     }
 115:Generated_Source\PSoC5/I2C_1_INT.c **** #endif /* (I2C_1_MODE_MULTI_MASTER_ENABLED) */
 116:Generated_Source\PSoC5/I2C_1_INT.c **** 
 117:Generated_Source\PSoC5/I2C_1_INT.c ****     /* Check for master operation mode */
 118:Generated_Source\PSoC5/I2C_1_INT.c ****     if(I2C_1_CHECK_SM_MASTER)
  42              		.loc 1 118 0
  43 0006 A54B     		ldr	r3, .L27+4
  44 0008 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
  45 000a 13F0400F 		tst	r3, #64
  46 000e 00F03A81 		beq	.L2
  47 0012 E4B2     		uxtb	r4, r4
 119:Generated_Source\PSoC5/I2C_1_INT.c ****     {
 120:Generated_Source\PSoC5/I2C_1_INT.c ****     #if(I2C_1_MODE_MASTER_ENABLED)
 121:Generated_Source\PSoC5/I2C_1_INT.c ****         if(I2C_1_CHECK_BYTE_COMPLETE(tmpCsr))
  48              		.loc 1 121 0
  49 0014 14F0010F 		tst	r4, #1
  50 0018 00F01D81 		beq	.L3
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 4


 122:Generated_Source\PSoC5/I2C_1_INT.c ****         {
 123:Generated_Source\PSoC5/I2C_1_INT.c ****             switch (I2C_1_state)
  51              		.loc 1 123 0
  52 001c 9F4B     		ldr	r3, .L27+4
  53 001e 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
  54 0020 453B     		subs	r3, r3, #69
  55 0022 052B     		cmp	r3, #5
  56 0024 00F21481 		bhi	.L4
  57 0028 DFE813F0 		tbh	[pc, r3, lsl #1]
  58              	.L6:
  59 002c 0600     		.2byte	(.L5-.L6)/2
  60 002e 8200     		.2byte	(.L7-.L6)/2
  61 0030 1201     		.2byte	(.L4-.L6)/2
  62 0032 1201     		.2byte	(.L4-.L6)/2
  63 0034 0600     		.2byte	(.L5-.L6)/2
  64 0036 DF00     		.2byte	(.L8-.L6)/2
  65              		.p2align 1
  66              	.L5:
 124:Generated_Source\PSoC5/I2C_1_INT.c ****             {
 125:Generated_Source\PSoC5/I2C_1_INT.c ****             case I2C_1_SM_MSTR_WR_ADDR:  /* After address is sent, write data */
 126:Generated_Source\PSoC5/I2C_1_INT.c ****             case I2C_1_SM_MSTR_RD_ADDR:  /* After address is sent, read data */
 127:Generated_Source\PSoC5/I2C_1_INT.c **** 
 128:Generated_Source\PSoC5/I2C_1_INT.c ****                 tmpCsr &= ((uint8) ~I2C_1_CSR_STOP_STATUS); /* Clear Stop bit history on address ph
  67              		.loc 1 128 0
  68 0038 04F0DF05 		and	r5, r4, #223
  69              	.LVL1:
 129:Generated_Source\PSoC5/I2C_1_INT.c **** 
 130:Generated_Source\PSoC5/I2C_1_INT.c ****                 if(I2C_1_CHECK_ADDR_ACK(tmpCsr))
  70              		.loc 1 130 0
  71 003c 04F00A04 		and	r4, r4, #10
  72 0040 082C     		cmp	r4, #8
  73 0042 42D1     		bne	.L9
 131:Generated_Source\PSoC5/I2C_1_INT.c ****                 {
 132:Generated_Source\PSoC5/I2C_1_INT.c ****                     /* Setup for transmit or receive of data */
 133:Generated_Source\PSoC5/I2C_1_INT.c ****                     if(I2C_1_state == I2C_1_SM_MSTR_WR_ADDR)   /* TRANSMIT data */
  74              		.loc 1 133 0
  75 0044 954B     		ldr	r3, .L27+4
  76 0046 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
  77 0048 DBB2     		uxtb	r3, r3
  78 004a 452B     		cmp	r3, #69
  79 004c 35D1     		bne	.L10
 134:Generated_Source\PSoC5/I2C_1_INT.c ****                     {
 135:Generated_Source\PSoC5/I2C_1_INT.c ****                         /* Check if at least one byte to transfer */
 136:Generated_Source\PSoC5/I2C_1_INT.c ****                         if(I2C_1_mstrWrBufSize > 0u)
  80              		.loc 1 136 0
  81 004e 944B     		ldr	r3, .L27+8
  82 0050 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
  83 0052 13F0FF0F 		tst	r3, #255
  84 0056 10D0     		beq	.L11
 137:Generated_Source\PSoC5/I2C_1_INT.c ****                         {
 138:Generated_Source\PSoC5/I2C_1_INT.c ****                             /* Load the 1st data byte */
 139:Generated_Source\PSoC5/I2C_1_INT.c ****                             I2C_1_DATA_REG = I2C_1_mstrWrBufPtr[0u];
  85              		.loc 1 139 0
  86 0058 924B     		ldr	r3, .L27+12
  87 005a 1B68     		ldr	r3, [r3]
  88 005c 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
  89 005e DBB2     		uxtb	r3, r3
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 5


  90 0060 914A     		ldr	r2, .L27+16
  91 0062 1370     		strb	r3, [r2]
 140:Generated_Source\PSoC5/I2C_1_INT.c ****                             I2C_1_TRANSMIT_DATA;
  92              		.loc 1 140 0
  93 0064 0422     		movs	r2, #4
  94 0066 8C4B     		ldr	r3, .L27
  95 0068 1A70     		strb	r2, [r3]
 141:Generated_Source\PSoC5/I2C_1_INT.c ****                             I2C_1_mstrWrBufIndex = 1u;   /* Set index to 2nd element */
  96              		.loc 1 141 0
  97 006a 0122     		movs	r2, #1
  98 006c 8F4B     		ldr	r3, .L27+20
  99 006e 1A70     		strb	r2, [r3]
 142:Generated_Source\PSoC5/I2C_1_INT.c **** 
 143:Generated_Source\PSoC5/I2C_1_INT.c ****                             /* Set transmit state until done */
 144:Generated_Source\PSoC5/I2C_1_INT.c ****                             I2C_1_state = I2C_1_SM_MSTR_WR_DATA;
 100              		.loc 1 144 0
 101 0070 4622     		movs	r2, #70
 102 0072 8A4B     		ldr	r3, .L27+4
 103 0074 1A70     		strb	r2, [r3]
 128:Generated_Source\PSoC5/I2C_1_INT.c **** 
 104              		.loc 1 128 0
 105 0076 2C46     		mov	r4, r5
 106 0078 EDE0     		b	.L3
 107              	.L11:
 145:Generated_Source\PSoC5/I2C_1_INT.c ****                         }
 146:Generated_Source\PSoC5/I2C_1_INT.c ****                         /* End of buffer: complete writing */
 147:Generated_Source\PSoC5/I2C_1_INT.c ****                         else if(I2C_1_CHECK_NO_STOP(I2C_1_mstrControl))
 108              		.loc 1 147 0
 109 007a 8D4B     		ldr	r3, .L27+24
 110 007c 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
 111 007e 13F0020F 		tst	r3, #2
 112 0082 0DD0     		beq	.L12
 148:Generated_Source\PSoC5/I2C_1_INT.c ****                         {
 149:Generated_Source\PSoC5/I2C_1_INT.c ****                             /* Set write complete and master halted */
 150:Generated_Source\PSoC5/I2C_1_INT.c ****                             I2C_1_mstrStatus |= (I2C_1_MSTAT_XFER_HALT |
 113              		.loc 1 150 0
 114 0084 8B4A     		ldr	r2, .L27+28
 115 0086 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
 116 0088 43F00A03 		orr	r3, r3, #10
 117 008c 1370     		strb	r3, [r2]
 151:Generated_Source\PSoC5/I2C_1_INT.c ****                                                             I2C_1_MSTAT_WR_CMPLT);
 152:Generated_Source\PSoC5/I2C_1_INT.c **** 
 153:Generated_Source\PSoC5/I2C_1_INT.c ****                             I2C_1_state = I2C_1_SM_MSTR_HALT; /* Expect ReStart */
 118              		.loc 1 153 0
 119 008e 6022     		movs	r2, #96
 120 0090 824B     		ldr	r3, .L27+4
 121 0092 1A70     		strb	r2, [r3]
 154:Generated_Source\PSoC5/I2C_1_INT.c ****                             I2C_1_DisableInt();
 122              		.loc 1 154 0
 123 0094 4FF40042 		mov	r2, #32768
 124 0098 874B     		ldr	r3, .L27+32
 125 009a 1A60     		str	r2, [r3]
 128:Generated_Source\PSoC5/I2C_1_INT.c **** 
 126              		.loc 1 128 0
 127 009c 2C46     		mov	r4, r5
 128 009e DAE0     		b	.L3
 129              	.L12:
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 6


 155:Generated_Source\PSoC5/I2C_1_INT.c ****                         }
 156:Generated_Source\PSoC5/I2C_1_INT.c ****                         else
 157:Generated_Source\PSoC5/I2C_1_INT.c ****                         {
 158:Generated_Source\PSoC5/I2C_1_INT.c ****                             I2C_1_ENABLE_INT_ON_STOP; /* Enable interrupt on Stop, to catch it */
 130              		.loc 1 158 0
 131 00a0 864A     		ldr	r2, .L27+36
 132 00a2 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
 133 00a4 43F01003 		orr	r3, r3, #16
 134 00a8 1370     		strb	r3, [r2]
 159:Generated_Source\PSoC5/I2C_1_INT.c ****                             I2C_1_GENERATE_STOP;
 135              		.loc 1 159 0
 136 00aa 1022     		movs	r2, #16
 137 00ac 844B     		ldr	r3, .L27+40
 138 00ae 1A70     		strb	r2, [r3]
 139 00b0 0422     		movs	r2, #4
 140 00b2 023B     		subs	r3, r3, #2
 141 00b4 1A70     		strb	r2, [r3]
 128:Generated_Source\PSoC5/I2C_1_INT.c **** 
 142              		.loc 1 128 0
 143 00b6 2C46     		mov	r4, r5
 144 00b8 CDE0     		b	.L3
 145              	.L10:
 160:Generated_Source\PSoC5/I2C_1_INT.c ****                         }
 161:Generated_Source\PSoC5/I2C_1_INT.c ****                     }
 162:Generated_Source\PSoC5/I2C_1_INT.c ****                     else  /* Master receive data */
 163:Generated_Source\PSoC5/I2C_1_INT.c ****                     {
 164:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_READY_TO_READ; /* Release bus to read data */
 146              		.loc 1 164 0
 147 00ba 0022     		movs	r2, #0
 148 00bc 764B     		ldr	r3, .L27
 149 00be 1A70     		strb	r2, [r3]
 165:Generated_Source\PSoC5/I2C_1_INT.c **** 
 166:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_state  = I2C_1_SM_MSTR_RD_DATA;
 150              		.loc 1 166 0
 151 00c0 4A22     		movs	r2, #74
 152 00c2 764B     		ldr	r3, .L27+4
 153 00c4 1A70     		strb	r2, [r3]
 128:Generated_Source\PSoC5/I2C_1_INT.c **** 
 154              		.loc 1 128 0
 155 00c6 2C46     		mov	r4, r5
 156 00c8 C5E0     		b	.L3
 157              	.L9:
 167:Generated_Source\PSoC5/I2C_1_INT.c ****                     }
 168:Generated_Source\PSoC5/I2C_1_INT.c ****                 }
 169:Generated_Source\PSoC5/I2C_1_INT.c ****                 /* Address is NACKed */
 170:Generated_Source\PSoC5/I2C_1_INT.c ****                 else if(I2C_1_CHECK_ADDR_NAK(tmpCsr))
 158              		.loc 1 170 0
 159 00ca 0A2C     		cmp	r4, #10
 160 00cc 2BD1     		bne	.L13
 171:Generated_Source\PSoC5/I2C_1_INT.c ****                 {
 172:Generated_Source\PSoC5/I2C_1_INT.c ****                     /* Set Address NAK error */
 173:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_mstrStatus |= (I2C_1_MSTAT_ERR_XFER |
 161              		.loc 1 173 0
 162 00ce 794A     		ldr	r2, .L27+28
 163 00d0 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
 164 00d2 43F0A003 		orr	r3, r3, #160
 165 00d6 1370     		strb	r3, [r2]
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 7


 174:Generated_Source\PSoC5/I2C_1_INT.c ****                                                     I2C_1_MSTAT_ERR_ADDR_NAK);
 175:Generated_Source\PSoC5/I2C_1_INT.c **** 
 176:Generated_Source\PSoC5/I2C_1_INT.c ****                     if(I2C_1_CHECK_NO_STOP(I2C_1_mstrControl))
 166              		.loc 1 176 0
 167 00d8 754B     		ldr	r3, .L27+24
 168 00da 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
 169 00dc 13F0020F 		tst	r3, #2
 170 00e0 14D0     		beq	.L14
 177:Generated_Source\PSoC5/I2C_1_INT.c ****                     {
 178:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_mstrStatus |= (I2C_1_MSTAT_XFER_HALT |
 179:Generated_Source\PSoC5/I2C_1_INT.c ****                                                         I2C_1_GET_MSTAT_CMPLT);
 171              		.loc 1 179 0
 172 00e2 6E4B     		ldr	r3, .L27+4
 173 00e4 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
 178:Generated_Source\PSoC5/I2C_1_INT.c ****                                                         I2C_1_GET_MSTAT_CMPLT);
 174              		.loc 1 178 0
 175 00e6 13F0080F 		tst	r3, #8
 176 00ea 01D0     		beq	.L24
 177 00ec 0923     		movs	r3, #9
 178 00ee 00E0     		b	.L15
 179              	.L24:
 180 00f0 0A23     		movs	r3, #10
 181              	.L15:
 178:Generated_Source\PSoC5/I2C_1_INT.c ****                                                         I2C_1_GET_MSTAT_CMPLT);
 182              		.loc 1 178 0 is_stmt 0 discriminator 4
 183 00f2 704A     		ldr	r2, .L27+28
 184 00f4 1178     		ldrb	r1, [r2]	@ zero_extendqisi2
 185 00f6 0B43     		orrs	r3, r3, r1
 186 00f8 1370     		strb	r3, [r2]
 180:Generated_Source\PSoC5/I2C_1_INT.c **** 
 181:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_state = I2C_1_SM_MSTR_HALT; /* Expect RESTART */
 187              		.loc 1 181 0 is_stmt 1 discriminator 4
 188 00fa 6022     		movs	r2, #96
 189 00fc 674B     		ldr	r3, .L27+4
 190 00fe 1A70     		strb	r2, [r3]
 182:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_DisableInt();
 191              		.loc 1 182 0 discriminator 4
 192 0100 4FF40042 		mov	r2, #32768
 193 0104 6C4B     		ldr	r3, .L27+32
 194 0106 1A60     		str	r2, [r3]
 128:Generated_Source\PSoC5/I2C_1_INT.c **** 
 195              		.loc 1 128 0 discriminator 4
 196 0108 2C46     		mov	r4, r5
 197 010a A4E0     		b	.L3
 198              	.L14:
 183:Generated_Source\PSoC5/I2C_1_INT.c ****                     }
 184:Generated_Source\PSoC5/I2C_1_INT.c ****                     else  /* Do normal Stop */
 185:Generated_Source\PSoC5/I2C_1_INT.c ****                     {
 186:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_ENABLE_INT_ON_STOP; /* Enable interrupt on Stop, to catch it */
 199              		.loc 1 186 0
 200 010c 6B4A     		ldr	r2, .L27+36
 201 010e 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
 202 0110 43F01003 		orr	r3, r3, #16
 203 0114 1370     		strb	r3, [r2]
 187:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_GENERATE_STOP;
 204              		.loc 1 187 0
 205 0116 1022     		movs	r2, #16
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 8


 206 0118 694B     		ldr	r3, .L27+40
 207 011a 1A70     		strb	r2, [r3]
 208 011c 0422     		movs	r2, #4
 209 011e 023B     		subs	r3, r3, #2
 210 0120 1A70     		strb	r2, [r3]
 128:Generated_Source\PSoC5/I2C_1_INT.c **** 
 211              		.loc 1 128 0
 212 0122 2C46     		mov	r4, r5
 213 0124 97E0     		b	.L3
 214              	.L13:
 188:Generated_Source\PSoC5/I2C_1_INT.c ****                     }
 189:Generated_Source\PSoC5/I2C_1_INT.c ****                 }
 190:Generated_Source\PSoC5/I2C_1_INT.c ****                 else
 191:Generated_Source\PSoC5/I2C_1_INT.c ****                 {
 192:Generated_Source\PSoC5/I2C_1_INT.c ****                     /* Address phase is not set for some reason: error */
 193:Generated_Source\PSoC5/I2C_1_INT.c ****                     #if(I2C_1_TIMEOUT_ENABLED)
 194:Generated_Source\PSoC5/I2C_1_INT.c ****                         /* Exit interrupt to take chance for timeout timer to handle this case */
 195:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_DisableInt();
 196:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_ClearPendingInt();
 197:Generated_Source\PSoC5/I2C_1_INT.c ****                     #else
 198:Generated_Source\PSoC5/I2C_1_INT.c ****                         /* Block execution flow: unexpected condition */
 199:Generated_Source\PSoC5/I2C_1_INT.c ****                         CYASSERT(0u != 0u);
 215              		.loc 1 199 0 discriminator 1
 216 0126 0020     		movs	r0, #0
 217 0128 FFF7FEFF 		bl	CyHalt
 218              	.LVL2:
 128:Generated_Source\PSoC5/I2C_1_INT.c **** 
 219              		.loc 1 128 0 discriminator 1
 220 012c 2C46     		mov	r4, r5
 221 012e 92E0     		b	.L3
 222              	.LVL3:
 223              	.L7:
 200:Generated_Source\PSoC5/I2C_1_INT.c ****                     #endif /* (I2C_1_TIMEOUT_ENABLED) */
 201:Generated_Source\PSoC5/I2C_1_INT.c ****                 }
 202:Generated_Source\PSoC5/I2C_1_INT.c ****                 break;
 203:Generated_Source\PSoC5/I2C_1_INT.c **** 
 204:Generated_Source\PSoC5/I2C_1_INT.c ****             case I2C_1_SM_MSTR_WR_DATA:
 205:Generated_Source\PSoC5/I2C_1_INT.c **** 
 206:Generated_Source\PSoC5/I2C_1_INT.c ****                 if(I2C_1_CHECK_DATA_ACK(tmpCsr))
 224              		.loc 1 206 0
 225 0130 14F0020F 		tst	r4, #2
 226 0134 36D1     		bne	.L16
 207:Generated_Source\PSoC5/I2C_1_INT.c ****                 {
 208:Generated_Source\PSoC5/I2C_1_INT.c ****                     /* Check if end of buffer */
 209:Generated_Source\PSoC5/I2C_1_INT.c ****                     if(I2C_1_mstrWrBufIndex  < I2C_1_mstrWrBufSize)
 227              		.loc 1 209 0
 228 0136 5D4B     		ldr	r3, .L27+20
 229 0138 1A78     		ldrb	r2, [r3]	@ zero_extendqisi2
 230 013a D2B2     		uxtb	r2, r2
 231 013c 584B     		ldr	r3, .L27+8
 232 013e 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
 233 0140 DBB2     		uxtb	r3, r3
 234 0142 9A42     		cmp	r2, r3
 235 0144 10D2     		bcs	.L17
 210:Generated_Source\PSoC5/I2C_1_INT.c ****                     {
 211:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_DATA_REG =
 212:Generated_Source\PSoC5/I2C_1_INT.c ****                                                  I2C_1_mstrWrBufPtr[I2C_1_mstrWrBufIndex];
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 9


 236              		.loc 1 212 0
 237 0146 594A     		ldr	r2, .L27+20
 238 0148 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
 239 014a DBB2     		uxtb	r3, r3
 240 014c 5549     		ldr	r1, .L27+12
 241 014e 0968     		ldr	r1, [r1]
 242 0150 CB5C     		ldrb	r3, [r1, r3]	@ zero_extendqisi2
 243 0152 DBB2     		uxtb	r3, r3
 211:Generated_Source\PSoC5/I2C_1_INT.c ****                                                  I2C_1_mstrWrBufPtr[I2C_1_mstrWrBufIndex];
 244              		.loc 1 211 0
 245 0154 5449     		ldr	r1, .L27+16
 246 0156 0B70     		strb	r3, [r1]
 213:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_TRANSMIT_DATA;
 247              		.loc 1 213 0
 248 0158 0421     		movs	r1, #4
 249 015a 4F4B     		ldr	r3, .L27
 250 015c 1970     		strb	r1, [r3]
 214:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_mstrWrBufIndex++;
 251              		.loc 1 214 0
 252 015e 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
 253 0160 0133     		adds	r3, r3, #1
 254 0162 DBB2     		uxtb	r3, r3
 255 0164 1370     		strb	r3, [r2]
 256 0166 76E0     		b	.L3
 257              	.L17:
 215:Generated_Source\PSoC5/I2C_1_INT.c ****                     }
 216:Generated_Source\PSoC5/I2C_1_INT.c ****                     /* End of buffer: complete writing */
 217:Generated_Source\PSoC5/I2C_1_INT.c ****                     else if(I2C_1_CHECK_NO_STOP(I2C_1_mstrControl))
 258              		.loc 1 217 0
 259 0168 514B     		ldr	r3, .L27+24
 260 016a 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
 261 016c 13F0020F 		tst	r3, #2
 262 0170 0CD0     		beq	.L18
 218:Generated_Source\PSoC5/I2C_1_INT.c ****                     {
 219:Generated_Source\PSoC5/I2C_1_INT.c ****                         /* Set write complete and master halted */
 220:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_mstrStatus |= (I2C_1_MSTAT_XFER_HALT |
 263              		.loc 1 220 0
 264 0172 504A     		ldr	r2, .L27+28
 265 0174 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
 266 0176 43F00A03 		orr	r3, r3, #10
 267 017a 1370     		strb	r3, [r2]
 221:Generated_Source\PSoC5/I2C_1_INT.c ****                                                         I2C_1_MSTAT_WR_CMPLT);
 222:Generated_Source\PSoC5/I2C_1_INT.c **** 
 223:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_state = I2C_1_SM_MSTR_HALT;    /* Expect restart */
 268              		.loc 1 223 0
 269 017c 6022     		movs	r2, #96
 270 017e 474B     		ldr	r3, .L27+4
 271 0180 1A70     		strb	r2, [r3]
 224:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_DisableInt();
 272              		.loc 1 224 0
 273 0182 4FF40042 		mov	r2, #32768
 274 0186 4C4B     		ldr	r3, .L27+32
 275 0188 1A60     		str	r2, [r3]
 276 018a 64E0     		b	.L3
 277              	.L18:
 225:Generated_Source\PSoC5/I2C_1_INT.c ****                     }
 226:Generated_Source\PSoC5/I2C_1_INT.c ****                     else  /* Do normal Stop */
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 10


 227:Generated_Source\PSoC5/I2C_1_INT.c ****                     {
 228:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_ENABLE_INT_ON_STOP;    /* Enable interrupt on Stop, to catch it */
 278              		.loc 1 228 0
 279 018c 4B4A     		ldr	r2, .L27+36
 280 018e 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
 281 0190 43F01003 		orr	r3, r3, #16
 282 0194 1370     		strb	r3, [r2]
 229:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_GENERATE_STOP;
 283              		.loc 1 229 0
 284 0196 1022     		movs	r2, #16
 285 0198 494B     		ldr	r3, .L27+40
 286 019a 1A70     		strb	r2, [r3]
 287 019c 0422     		movs	r2, #4
 288 019e 023B     		subs	r3, r3, #2
 289 01a0 1A70     		strb	r2, [r3]
 290 01a2 58E0     		b	.L3
 291              	.L16:
 230:Generated_Source\PSoC5/I2C_1_INT.c ****                     }
 231:Generated_Source\PSoC5/I2C_1_INT.c ****                 }
 232:Generated_Source\PSoC5/I2C_1_INT.c ****                 /* Last byte NAKed: end writing */
 233:Generated_Source\PSoC5/I2C_1_INT.c ****                 else if(I2C_1_CHECK_NO_STOP(I2C_1_mstrControl))
 292              		.loc 1 233 0
 293 01a4 424B     		ldr	r3, .L27+24
 294 01a6 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
 295 01a8 13F0020F 		tst	r3, #2
 296 01ac 0CD0     		beq	.L19
 234:Generated_Source\PSoC5/I2C_1_INT.c ****                 {
 235:Generated_Source\PSoC5/I2C_1_INT.c ****                     /* Set write complete, short transfer and master halted */
 236:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_mstrStatus |= (I2C_1_MSTAT_ERR_XFER       |
 297              		.loc 1 236 0
 298 01ae 414A     		ldr	r2, .L27+28
 299 01b0 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
 300 01b2 43F09A03 		orr	r3, r3, #154
 301 01b6 1370     		strb	r3, [r2]
 237:Generated_Source\PSoC5/I2C_1_INT.c ****                                                     I2C_1_MSTAT_ERR_SHORT_XFER |
 238:Generated_Source\PSoC5/I2C_1_INT.c ****                                                     I2C_1_MSTAT_XFER_HALT      |
 239:Generated_Source\PSoC5/I2C_1_INT.c ****                                                     I2C_1_MSTAT_WR_CMPLT);
 240:Generated_Source\PSoC5/I2C_1_INT.c **** 
 241:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_state = I2C_1_SM_MSTR_HALT;    /* Expect ReStart */
 302              		.loc 1 241 0
 303 01b8 6022     		movs	r2, #96
 304 01ba 384B     		ldr	r3, .L27+4
 305 01bc 1A70     		strb	r2, [r3]
 242:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_DisableInt();
 306              		.loc 1 242 0
 307 01be 4FF40042 		mov	r2, #32768
 308 01c2 3D4B     		ldr	r3, .L27+32
 309 01c4 1A60     		str	r2, [r3]
 310 01c6 46E0     		b	.L3
 311              	.L19:
 243:Generated_Source\PSoC5/I2C_1_INT.c ****                 }
 244:Generated_Source\PSoC5/I2C_1_INT.c ****                 else  /* Do normal Stop */
 245:Generated_Source\PSoC5/I2C_1_INT.c ****                 {
 246:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_ENABLE_INT_ON_STOP;    /* Enable interrupt on Stop, to catch it */
 312              		.loc 1 246 0
 313 01c8 3C4A     		ldr	r2, .L27+36
 314 01ca 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 11


 315 01cc 43F01003 		orr	r3, r3, #16
 316 01d0 1370     		strb	r3, [r2]
 247:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_GENERATE_STOP;
 317              		.loc 1 247 0
 318 01d2 1022     		movs	r2, #16
 319 01d4 3A4B     		ldr	r3, .L27+40
 320 01d6 1A70     		strb	r2, [r3]
 321 01d8 0422     		movs	r2, #4
 322 01da 023B     		subs	r3, r3, #2
 323 01dc 1A70     		strb	r2, [r3]
 248:Generated_Source\PSoC5/I2C_1_INT.c **** 
 249:Generated_Source\PSoC5/I2C_1_INT.c ****                     /* Set short transfer and error flag */
 250:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_mstrStatus |= (I2C_1_MSTAT_ERR_SHORT_XFER |
 324              		.loc 1 250 0
 325 01de 354A     		ldr	r2, .L27+28
 326 01e0 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
 327 01e2 43F09003 		orr	r3, r3, #144
 328 01e6 1370     		strb	r3, [r2]
 329 01e8 35E0     		b	.L3
 330              	.L8:
 251:Generated_Source\PSoC5/I2C_1_INT.c ****                                                     I2C_1_MSTAT_ERR_XFER);
 252:Generated_Source\PSoC5/I2C_1_INT.c ****                 }
 253:Generated_Source\PSoC5/I2C_1_INT.c **** 
 254:Generated_Source\PSoC5/I2C_1_INT.c ****                 break;
 255:Generated_Source\PSoC5/I2C_1_INT.c **** 
 256:Generated_Source\PSoC5/I2C_1_INT.c ****             case I2C_1_SM_MSTR_RD_DATA:
 257:Generated_Source\PSoC5/I2C_1_INT.c **** 
 258:Generated_Source\PSoC5/I2C_1_INT.c ****                 I2C_1_mstrRdBufPtr[I2C_1_mstrRdBufIndex] = I2C_1_DATA_REG;
 331              		.loc 1 258 0
 332 01ea 364A     		ldr	r2, .L27+44
 333 01ec 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
 334 01ee DBB2     		uxtb	r3, r3
 335 01f0 3549     		ldr	r1, .L27+48
 336 01f2 0868     		ldr	r0, [r1]
 337 01f4 2C49     		ldr	r1, .L27+16
 338 01f6 0978     		ldrb	r1, [r1]	@ zero_extendqisi2
 339 01f8 C9B2     		uxtb	r1, r1
 340 01fa C154     		strb	r1, [r0, r3]
 259:Generated_Source\PSoC5/I2C_1_INT.c ****                 I2C_1_mstrRdBufIndex++;
 341              		.loc 1 259 0
 342 01fc 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
 343 01fe 0133     		adds	r3, r3, #1
 344 0200 DBB2     		uxtb	r3, r3
 345 0202 1370     		strb	r3, [r2]
 260:Generated_Source\PSoC5/I2C_1_INT.c **** 
 261:Generated_Source\PSoC5/I2C_1_INT.c ****                 /* Check if end of buffer */
 262:Generated_Source\PSoC5/I2C_1_INT.c ****                 if(I2C_1_mstrRdBufIndex < I2C_1_mstrRdBufSize)
 346              		.loc 1 262 0
 347 0204 1278     		ldrb	r2, [r2]	@ zero_extendqisi2
 348 0206 D2B2     		uxtb	r2, r2
 349 0208 304B     		ldr	r3, .L27+52
 350 020a 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
 351 020c DBB2     		uxtb	r3, r3
 352 020e 9A42     		cmp	r2, r3
 353 0210 03D2     		bcs	.L20
 263:Generated_Source\PSoC5/I2C_1_INT.c ****                 {
 264:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_ACK_AND_RECEIVE;       /* ACK and receive byte */
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 12


 354              		.loc 1 264 0
 355 0212 1022     		movs	r2, #16
 356 0214 204B     		ldr	r3, .L27
 357 0216 1A70     		strb	r2, [r3]
 358 0218 1DE0     		b	.L3
 359              	.L20:
 265:Generated_Source\PSoC5/I2C_1_INT.c ****                 }
 266:Generated_Source\PSoC5/I2C_1_INT.c ****                 /* End of buffer: complete reading */
 267:Generated_Source\PSoC5/I2C_1_INT.c ****                 else if(I2C_1_CHECK_NO_STOP(I2C_1_mstrControl))
 360              		.loc 1 267 0
 361 021a 254B     		ldr	r3, .L27+24
 362 021c 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
 363 021e 13F0020F 		tst	r3, #2
 364 0222 0CD0     		beq	.L21
 268:Generated_Source\PSoC5/I2C_1_INT.c ****                 {
 269:Generated_Source\PSoC5/I2C_1_INT.c ****                     /* Set read complete and master halted */
 270:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_mstrStatus |= (I2C_1_MSTAT_XFER_HALT |
 365              		.loc 1 270 0
 366 0224 234A     		ldr	r2, .L27+28
 367 0226 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
 368 0228 43F00903 		orr	r3, r3, #9
 369 022c 1370     		strb	r3, [r2]
 271:Generated_Source\PSoC5/I2C_1_INT.c ****                                                     I2C_1_MSTAT_RD_CMPLT);
 272:Generated_Source\PSoC5/I2C_1_INT.c **** 
 273:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_state = I2C_1_SM_MSTR_HALT;    /* Expect ReStart */
 370              		.loc 1 273 0
 371 022e 6022     		movs	r2, #96
 372 0230 1A4B     		ldr	r3, .L27+4
 373 0232 1A70     		strb	r2, [r3]
 274:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_DisableInt();
 374              		.loc 1 274 0
 375 0234 4FF40042 		mov	r2, #32768
 376 0238 1F4B     		ldr	r3, .L27+32
 377 023a 1A60     		str	r2, [r3]
 378 023c 0BE0     		b	.L3
 379              	.L21:
 275:Generated_Source\PSoC5/I2C_1_INT.c ****                 }
 276:Generated_Source\PSoC5/I2C_1_INT.c ****                 else
 277:Generated_Source\PSoC5/I2C_1_INT.c ****                 {
 278:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_ENABLE_INT_ON_STOP;
 380              		.loc 1 278 0
 381 023e 1F4A     		ldr	r2, .L27+36
 382 0240 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
 383 0242 43F01003 		orr	r3, r3, #16
 384 0246 1370     		strb	r3, [r2]
 279:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_NAK_AND_RECEIVE;       /* NACK and TRY to generate Stop */
 385              		.loc 1 279 0
 386 0248 0022     		movs	r2, #0
 387 024a 134B     		ldr	r3, .L27
 388 024c 1A70     		strb	r2, [r3]
 389 024e 02E0     		b	.L3
 390              	.L4:
 280:Generated_Source\PSoC5/I2C_1_INT.c ****                 }
 281:Generated_Source\PSoC5/I2C_1_INT.c ****                 break;
 282:Generated_Source\PSoC5/I2C_1_INT.c **** 
 283:Generated_Source\PSoC5/I2C_1_INT.c ****             default: /* This is an invalid state and should not occur */
 284:Generated_Source\PSoC5/I2C_1_INT.c **** 
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 13


 285:Generated_Source\PSoC5/I2C_1_INT.c ****             #if(I2C_1_TIMEOUT_ENABLED)
 286:Generated_Source\PSoC5/I2C_1_INT.c ****                 /* Exit interrupt to take chance for timeout timer to handles this case */
 287:Generated_Source\PSoC5/I2C_1_INT.c ****                 I2C_1_DisableInt();
 288:Generated_Source\PSoC5/I2C_1_INT.c ****                 I2C_1_ClearPendingInt();
 289:Generated_Source\PSoC5/I2C_1_INT.c ****             #else
 290:Generated_Source\PSoC5/I2C_1_INT.c ****                 /* Block execution flow: unexpected condition */
 291:Generated_Source\PSoC5/I2C_1_INT.c ****                 CYASSERT(0u != 0u);
 391              		.loc 1 291 0 discriminator 1
 392 0250 0020     		movs	r0, #0
 393 0252 FFF7FEFF 		bl	CyHalt
 394              	.LVL4:
 395              	.L3:
 292:Generated_Source\PSoC5/I2C_1_INT.c ****             #endif /* (I2C_1_TIMEOUT_ENABLED) */
 293:Generated_Source\PSoC5/I2C_1_INT.c **** 
 294:Generated_Source\PSoC5/I2C_1_INT.c ****                 break;
 295:Generated_Source\PSoC5/I2C_1_INT.c ****             }
 296:Generated_Source\PSoC5/I2C_1_INT.c ****         }
 297:Generated_Source\PSoC5/I2C_1_INT.c **** 
 298:Generated_Source\PSoC5/I2C_1_INT.c ****         /* Catches Stop: end of transaction */
 299:Generated_Source\PSoC5/I2C_1_INT.c ****         if(I2C_1_CHECK_STOP_STS(tmpCsr))
 396              		.loc 1 299 0
 397 0256 14F0200F 		tst	r4, #32
 398 025a 1CD0     		beq	.L1
 300:Generated_Source\PSoC5/I2C_1_INT.c ****         {
 301:Generated_Source\PSoC5/I2C_1_INT.c ****             I2C_1_mstrStatus |= I2C_1_GET_MSTAT_CMPLT;
 399              		.loc 1 301 0
 400 025c 0F4B     		ldr	r3, .L27+4
 401 025e 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
 402 0260 13F0080F 		tst	r3, #8
 403 0264 01D0     		beq	.L25
 404 0266 0123     		movs	r3, #1
 405 0268 00E0     		b	.L23
 406              	.L25:
 407 026a 0223     		movs	r3, #2
 408              	.L23:
 409              		.loc 1 301 0 is_stmt 0 discriminator 4
 410 026c 114A     		ldr	r2, .L27+28
 411 026e 1178     		ldrb	r1, [r2]	@ zero_extendqisi2
 412 0270 0B43     		orrs	r3, r3, r1
 413 0272 1370     		strb	r3, [r2]
 302:Generated_Source\PSoC5/I2C_1_INT.c **** 
 303:Generated_Source\PSoC5/I2C_1_INT.c ****             I2C_1_DISABLE_INT_ON_STOP;
 414              		.loc 1 303 0 is_stmt 1 discriminator 4
 415 0274 114A     		ldr	r2, .L27+36
 416 0276 1378     		ldrb	r3, [r2]	@ zero_extendqisi2
 417 0278 03F0EF03 		and	r3, r3, #239
 418 027c 1370     		strb	r3, [r2]
 304:Generated_Source\PSoC5/I2C_1_INT.c ****             I2C_1_state = I2C_1_SM_IDLE;
 419              		.loc 1 304 0 discriminator 4
 420 027e 1022     		movs	r2, #16
 421 0280 064B     		ldr	r3, .L27+4
 422 0282 1A70     		strb	r2, [r3]
 423 0284 38BD     		pop	{r3, r4, r5, pc}
 424              	.LVL5:
 425              	.L2:
 305:Generated_Source\PSoC5/I2C_1_INT.c ****         }
 306:Generated_Source\PSoC5/I2C_1_INT.c ****     #endif /* (I2C_1_MODE_MASTER_ENABLED) */
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 14


 307:Generated_Source\PSoC5/I2C_1_INT.c ****     }
 308:Generated_Source\PSoC5/I2C_1_INT.c ****     else if(I2C_1_CHECK_SM_SLAVE)
 426              		.loc 1 308 0
 427 0286 054B     		ldr	r3, .L27+4
 428 0288 1B78     		ldrb	r3, [r3]	@ zero_extendqisi2
 429 028a 13F0100F 		tst	r3, #16
 430 028e 02D1     		bne	.L1
 309:Generated_Source\PSoC5/I2C_1_INT.c ****     {
 310:Generated_Source\PSoC5/I2C_1_INT.c ****     #if(I2C_1_MODE_SLAVE_ENABLED)
 311:Generated_Source\PSoC5/I2C_1_INT.c **** 
 312:Generated_Source\PSoC5/I2C_1_INT.c ****         if((I2C_1_CHECK_STOP_STS(tmpCsr)) || /* Stop || Restart */
 313:Generated_Source\PSoC5/I2C_1_INT.c ****            (I2C_1_CHECK_BYTE_COMPLETE(tmpCsr) && I2C_1_CHECK_ADDRESS_STS(tmpCsr)))
 314:Generated_Source\PSoC5/I2C_1_INT.c ****         {
 315:Generated_Source\PSoC5/I2C_1_INT.c ****             /* Catch end of master write transaction: use interrupt on Stop */
 316:Generated_Source\PSoC5/I2C_1_INT.c ****             /* The Stop bit history on address phase does not have correct state */
 317:Generated_Source\PSoC5/I2C_1_INT.c ****             if(I2C_1_SM_SL_WR_DATA == I2C_1_state)
 318:Generated_Source\PSoC5/I2C_1_INT.c ****             {
 319:Generated_Source\PSoC5/I2C_1_INT.c ****                 I2C_1_DISABLE_INT_ON_STOP;
 320:Generated_Source\PSoC5/I2C_1_INT.c **** 
 321:Generated_Source\PSoC5/I2C_1_INT.c ****                 I2C_1_slStatus &= ((uint8) ~I2C_1_SSTAT_WR_BUSY);
 322:Generated_Source\PSoC5/I2C_1_INT.c ****                 I2C_1_slStatus |= ((uint8)  I2C_1_SSTAT_WR_CMPLT);
 323:Generated_Source\PSoC5/I2C_1_INT.c **** 
 324:Generated_Source\PSoC5/I2C_1_INT.c ****                 I2C_1_state = I2C_1_SM_IDLE;
 325:Generated_Source\PSoC5/I2C_1_INT.c ****             }
 326:Generated_Source\PSoC5/I2C_1_INT.c ****         }
 327:Generated_Source\PSoC5/I2C_1_INT.c **** 
 328:Generated_Source\PSoC5/I2C_1_INT.c ****         if(I2C_1_CHECK_BYTE_COMPLETE(tmpCsr))
 329:Generated_Source\PSoC5/I2C_1_INT.c ****         {
 330:Generated_Source\PSoC5/I2C_1_INT.c ****             /* The address only issued after Start or ReStart: so check the address
 331:Generated_Source\PSoC5/I2C_1_INT.c ****                to catch these events:
 332:Generated_Source\PSoC5/I2C_1_INT.c ****                 FF : sets an address phase with a byte_complete interrupt trigger.
 333:Generated_Source\PSoC5/I2C_1_INT.c ****                 UDB: sets an address phase immediately after Start or ReStart. */
 334:Generated_Source\PSoC5/I2C_1_INT.c ****             if(I2C_1_CHECK_ADDRESS_STS(tmpCsr))
 335:Generated_Source\PSoC5/I2C_1_INT.c ****             {
 336:Generated_Source\PSoC5/I2C_1_INT.c ****             /* Check for software address detection */
 337:Generated_Source\PSoC5/I2C_1_INT.c ****             #if(I2C_1_SW_ADRR_DECODE)
 338:Generated_Source\PSoC5/I2C_1_INT.c ****                 tmp8 = I2C_1_GET_SLAVE_ADDR(I2C_1_DATA_REG);
 339:Generated_Source\PSoC5/I2C_1_INT.c **** 
 340:Generated_Source\PSoC5/I2C_1_INT.c ****                 if(tmp8 == I2C_1_slAddress)   /* Check for address match */
 341:Generated_Source\PSoC5/I2C_1_INT.c ****                 {
 342:Generated_Source\PSoC5/I2C_1_INT.c ****                     if(0u != (I2C_1_DATA_REG & I2C_1_READ_FLAG))
 343:Generated_Source\PSoC5/I2C_1_INT.c ****                     {
 344:Generated_Source\PSoC5/I2C_1_INT.c ****                         /* Place code to prepare read buffer here                  */
 345:Generated_Source\PSoC5/I2C_1_INT.c ****                         /* `#START I2C_1_SW_PREPARE_READ_BUF_interrupt` */
 346:Generated_Source\PSoC5/I2C_1_INT.c **** 
 347:Generated_Source\PSoC5/I2C_1_INT.c ****                         /* `#END` */
 348:Generated_Source\PSoC5/I2C_1_INT.c **** 
 349:Generated_Source\PSoC5/I2C_1_INT.c ****                     #ifdef I2C_1_SW_PREPARE_READ_BUF_CALLBACK
 350:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_SwPrepareReadBuf_Callback();
 351:Generated_Source\PSoC5/I2C_1_INT.c ****                     #endif /* I2C_1_SW_PREPARE_READ_BUF_CALLBACK */
 352:Generated_Source\PSoC5/I2C_1_INT.c ****                         
 353:Generated_Source\PSoC5/I2C_1_INT.c ****                         /* Prepare next operation to read, get data and place in data register */
 354:Generated_Source\PSoC5/I2C_1_INT.c ****                         if(I2C_1_slRdBufIndex < I2C_1_slRdBufSize)
 355:Generated_Source\PSoC5/I2C_1_INT.c ****                         {
 356:Generated_Source\PSoC5/I2C_1_INT.c ****                             /* Load first data byte from array */
 357:Generated_Source\PSoC5/I2C_1_INT.c ****                             I2C_1_DATA_REG = I2C_1_slRdBufPtr[I2C_1_slRdBufIndex];
 358:Generated_Source\PSoC5/I2C_1_INT.c ****                             I2C_1_ACK_AND_TRANSMIT;
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 15


 359:Generated_Source\PSoC5/I2C_1_INT.c ****                             I2C_1_slRdBufIndex++;
 360:Generated_Source\PSoC5/I2C_1_INT.c **** 
 361:Generated_Source\PSoC5/I2C_1_INT.c ****                             I2C_1_slStatus |= I2C_1_SSTAT_RD_BUSY;
 362:Generated_Source\PSoC5/I2C_1_INT.c ****                         }
 363:Generated_Source\PSoC5/I2C_1_INT.c ****                         else    /* Overflow: provide 0xFF on bus */
 364:Generated_Source\PSoC5/I2C_1_INT.c ****                         {
 365:Generated_Source\PSoC5/I2C_1_INT.c ****                             I2C_1_DATA_REG = I2C_1_OVERFLOW_RETURN;
 366:Generated_Source\PSoC5/I2C_1_INT.c ****                             I2C_1_ACK_AND_TRANSMIT;
 367:Generated_Source\PSoC5/I2C_1_INT.c **** 
 368:Generated_Source\PSoC5/I2C_1_INT.c ****                             I2C_1_slStatus  |= (I2C_1_SSTAT_RD_BUSY |
 369:Generated_Source\PSoC5/I2C_1_INT.c ****                                                            I2C_1_SSTAT_RD_ERR_OVFL);
 370:Generated_Source\PSoC5/I2C_1_INT.c ****                         }
 371:Generated_Source\PSoC5/I2C_1_INT.c **** 
 372:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_state = I2C_1_SM_SL_RD_DATA;
 373:Generated_Source\PSoC5/I2C_1_INT.c ****                     }
 374:Generated_Source\PSoC5/I2C_1_INT.c ****                     else  /* Write transaction: receive 1st byte */
 375:Generated_Source\PSoC5/I2C_1_INT.c ****                     {
 376:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_ACK_AND_RECEIVE;
 377:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_state = I2C_1_SM_SL_WR_DATA;
 378:Generated_Source\PSoC5/I2C_1_INT.c **** 
 379:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_slStatus |= I2C_1_SSTAT_WR_BUSY;
 380:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_ENABLE_INT_ON_STOP;
 381:Generated_Source\PSoC5/I2C_1_INT.c ****                     }
 382:Generated_Source\PSoC5/I2C_1_INT.c ****                 }
 383:Generated_Source\PSoC5/I2C_1_INT.c ****                 else
 384:Generated_Source\PSoC5/I2C_1_INT.c ****                 {
 385:Generated_Source\PSoC5/I2C_1_INT.c ****                     /*     Place code to compare for additional address here    */
 386:Generated_Source\PSoC5/I2C_1_INT.c ****                     /* `#START I2C_1_SW_ADDR_COMPARE_interruptStart` */
 387:Generated_Source\PSoC5/I2C_1_INT.c **** 
 388:Generated_Source\PSoC5/I2C_1_INT.c ****                     /* `#END` */
 389:Generated_Source\PSoC5/I2C_1_INT.c **** 
 390:Generated_Source\PSoC5/I2C_1_INT.c ****                 #ifdef I2C_1_SW_ADDR_COMPARE_ENTRY_CALLBACK
 391:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_SwAddrCompare_EntryCallback();
 392:Generated_Source\PSoC5/I2C_1_INT.c ****                 #endif /* I2C_1_SW_ADDR_COMPARE_ENTRY_CALLBACK */
 393:Generated_Source\PSoC5/I2C_1_INT.c ****                     
 394:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_NAK_AND_RECEIVE;   /* NACK address */
 395:Generated_Source\PSoC5/I2C_1_INT.c **** 
 396:Generated_Source\PSoC5/I2C_1_INT.c ****                     /* Place code to end of condition for NACK generation here */
 397:Generated_Source\PSoC5/I2C_1_INT.c ****                     /* `#START I2C_1_SW_ADDR_COMPARE_interruptEnd`  */
 398:Generated_Source\PSoC5/I2C_1_INT.c **** 
 399:Generated_Source\PSoC5/I2C_1_INT.c ****                     /* `#END` */
 400:Generated_Source\PSoC5/I2C_1_INT.c **** 
 401:Generated_Source\PSoC5/I2C_1_INT.c ****                 #ifdef I2C_1_SW_ADDR_COMPARE_EXIT_CALLBACK
 402:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_SwAddrCompare_ExitCallback();
 403:Generated_Source\PSoC5/I2C_1_INT.c ****                 #endif /* I2C_1_SW_ADDR_COMPARE_EXIT_CALLBACK */
 404:Generated_Source\PSoC5/I2C_1_INT.c ****                 }
 405:Generated_Source\PSoC5/I2C_1_INT.c **** 
 406:Generated_Source\PSoC5/I2C_1_INT.c ****             #else /* (I2C_1_HW_ADRR_DECODE) */
 407:Generated_Source\PSoC5/I2C_1_INT.c **** 
 408:Generated_Source\PSoC5/I2C_1_INT.c ****                 if(0u != (I2C_1_DATA_REG & I2C_1_READ_FLAG))
 409:Generated_Source\PSoC5/I2C_1_INT.c ****                 {
 410:Generated_Source\PSoC5/I2C_1_INT.c ****                     /* Place code to prepare read buffer here                  */
 411:Generated_Source\PSoC5/I2C_1_INT.c ****                     /* `#START I2C_1_HW_PREPARE_READ_BUF_interrupt` */
 412:Generated_Source\PSoC5/I2C_1_INT.c **** 
 413:Generated_Source\PSoC5/I2C_1_INT.c ****                     /* `#END` */
 414:Generated_Source\PSoC5/I2C_1_INT.c ****                     
 415:Generated_Source\PSoC5/I2C_1_INT.c ****                 #ifdef I2C_1_HW_PREPARE_READ_BUF_CALLBACK
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 16


 416:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_HwPrepareReadBuf_Callback();
 417:Generated_Source\PSoC5/I2C_1_INT.c ****                 #endif /* I2C_1_HW_PREPARE_READ_BUF_CALLBACK */
 418:Generated_Source\PSoC5/I2C_1_INT.c **** 
 419:Generated_Source\PSoC5/I2C_1_INT.c ****                     /* Prepare next operation to read, get data and place in data register */
 420:Generated_Source\PSoC5/I2C_1_INT.c ****                     if(I2C_1_slRdBufIndex < I2C_1_slRdBufSize)
 421:Generated_Source\PSoC5/I2C_1_INT.c ****                     {
 422:Generated_Source\PSoC5/I2C_1_INT.c ****                         /* Load first data byte from array */
 423:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_DATA_REG = I2C_1_slRdBufPtr[I2C_1_slRdBufIndex];
 424:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_ACK_AND_TRANSMIT;
 425:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_slRdBufIndex++;
 426:Generated_Source\PSoC5/I2C_1_INT.c **** 
 427:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_slStatus |= I2C_1_SSTAT_RD_BUSY;
 428:Generated_Source\PSoC5/I2C_1_INT.c ****                     }
 429:Generated_Source\PSoC5/I2C_1_INT.c ****                     else    /* Overflow: provide 0xFF on bus */
 430:Generated_Source\PSoC5/I2C_1_INT.c ****                     {
 431:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_DATA_REG = I2C_1_OVERFLOW_RETURN;
 432:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_ACK_AND_TRANSMIT;
 433:Generated_Source\PSoC5/I2C_1_INT.c **** 
 434:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_slStatus  |= (I2C_1_SSTAT_RD_BUSY |
 435:Generated_Source\PSoC5/I2C_1_INT.c ****                                                        I2C_1_SSTAT_RD_ERR_OVFL);
 436:Generated_Source\PSoC5/I2C_1_INT.c ****                     }
 437:Generated_Source\PSoC5/I2C_1_INT.c **** 
 438:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_state = I2C_1_SM_SL_RD_DATA;
 439:Generated_Source\PSoC5/I2C_1_INT.c ****                 }
 440:Generated_Source\PSoC5/I2C_1_INT.c ****                 else  /* Write transaction: receive 1st byte */
 441:Generated_Source\PSoC5/I2C_1_INT.c ****                 {
 442:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_ACK_AND_RECEIVE;
 443:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_state = I2C_1_SM_SL_WR_DATA;
 444:Generated_Source\PSoC5/I2C_1_INT.c **** 
 445:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_slStatus |= I2C_1_SSTAT_WR_BUSY;
 446:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_ENABLE_INT_ON_STOP;
 447:Generated_Source\PSoC5/I2C_1_INT.c ****                 }
 448:Generated_Source\PSoC5/I2C_1_INT.c **** 
 449:Generated_Source\PSoC5/I2C_1_INT.c ****             #endif /* (I2C_1_SW_ADRR_DECODE) */
 450:Generated_Source\PSoC5/I2C_1_INT.c ****             }
 451:Generated_Source\PSoC5/I2C_1_INT.c ****             /* Data states */
 452:Generated_Source\PSoC5/I2C_1_INT.c ****             /* Data master writes into slave */
 453:Generated_Source\PSoC5/I2C_1_INT.c ****             else if(I2C_1_state == I2C_1_SM_SL_WR_DATA)
 454:Generated_Source\PSoC5/I2C_1_INT.c ****             {
 455:Generated_Source\PSoC5/I2C_1_INT.c ****                 if(I2C_1_slWrBufIndex < I2C_1_slWrBufSize)
 456:Generated_Source\PSoC5/I2C_1_INT.c ****                 {
 457:Generated_Source\PSoC5/I2C_1_INT.c ****                     tmp8 = I2C_1_DATA_REG;
 458:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_ACK_AND_RECEIVE;
 459:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_slWrBufPtr[I2C_1_slWrBufIndex] = tmp8;
 460:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_slWrBufIndex++;
 461:Generated_Source\PSoC5/I2C_1_INT.c ****                 }
 462:Generated_Source\PSoC5/I2C_1_INT.c ****                 else  /* of array: complete write, send NACK */
 463:Generated_Source\PSoC5/I2C_1_INT.c ****                 {
 464:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_NAK_AND_RECEIVE;
 465:Generated_Source\PSoC5/I2C_1_INT.c **** 
 466:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_slStatus |= I2C_1_SSTAT_WR_ERR_OVFL;
 467:Generated_Source\PSoC5/I2C_1_INT.c ****                 }
 468:Generated_Source\PSoC5/I2C_1_INT.c ****             }
 469:Generated_Source\PSoC5/I2C_1_INT.c ****             /* Data master reads from slave */
 470:Generated_Source\PSoC5/I2C_1_INT.c ****             else if(I2C_1_state == I2C_1_SM_SL_RD_DATA)
 471:Generated_Source\PSoC5/I2C_1_INT.c ****             {
 472:Generated_Source\PSoC5/I2C_1_INT.c ****                 if(I2C_1_CHECK_DATA_ACK(tmpCsr))
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 17


 473:Generated_Source\PSoC5/I2C_1_INT.c ****                 {
 474:Generated_Source\PSoC5/I2C_1_INT.c ****                     if(I2C_1_slRdBufIndex < I2C_1_slRdBufSize)
 475:Generated_Source\PSoC5/I2C_1_INT.c ****                     {
 476:Generated_Source\PSoC5/I2C_1_INT.c ****                          /* Get data from array */
 477:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_DATA_REG = I2C_1_slRdBufPtr[I2C_1_slRdBufIndex];
 478:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_TRANSMIT_DATA;
 479:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_slRdBufIndex++;
 480:Generated_Source\PSoC5/I2C_1_INT.c ****                     }
 481:Generated_Source\PSoC5/I2C_1_INT.c ****                     else   /* Overflow: provide 0xFF on bus */
 482:Generated_Source\PSoC5/I2C_1_INT.c ****                     {
 483:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_DATA_REG = I2C_1_OVERFLOW_RETURN;
 484:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_TRANSMIT_DATA;
 485:Generated_Source\PSoC5/I2C_1_INT.c **** 
 486:Generated_Source\PSoC5/I2C_1_INT.c ****                         I2C_1_slStatus |= I2C_1_SSTAT_RD_ERR_OVFL;
 487:Generated_Source\PSoC5/I2C_1_INT.c ****                     }
 488:Generated_Source\PSoC5/I2C_1_INT.c ****                 }
 489:Generated_Source\PSoC5/I2C_1_INT.c ****                 else  /* Last byte was NACKed: read complete */
 490:Generated_Source\PSoC5/I2C_1_INT.c ****                 {
 491:Generated_Source\PSoC5/I2C_1_INT.c ****                     /* Only NACK appears on bus */
 492:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_DATA_REG = I2C_1_OVERFLOW_RETURN;
 493:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_NAK_AND_TRANSMIT;
 494:Generated_Source\PSoC5/I2C_1_INT.c **** 
 495:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_slStatus &= ((uint8) ~I2C_1_SSTAT_RD_BUSY);
 496:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_slStatus |= ((uint8)  I2C_1_SSTAT_RD_CMPLT);
 497:Generated_Source\PSoC5/I2C_1_INT.c **** 
 498:Generated_Source\PSoC5/I2C_1_INT.c ****                     I2C_1_state = I2C_1_SM_IDLE;
 499:Generated_Source\PSoC5/I2C_1_INT.c ****                 }
 500:Generated_Source\PSoC5/I2C_1_INT.c ****             }
 501:Generated_Source\PSoC5/I2C_1_INT.c ****             else
 502:Generated_Source\PSoC5/I2C_1_INT.c ****             {
 503:Generated_Source\PSoC5/I2C_1_INT.c ****             #if(I2C_1_TIMEOUT_ENABLED)
 504:Generated_Source\PSoC5/I2C_1_INT.c ****                 /* Exit interrupt to take chance for timeout timer to handle this case */
 505:Generated_Source\PSoC5/I2C_1_INT.c ****                 I2C_1_DisableInt();
 506:Generated_Source\PSoC5/I2C_1_INT.c ****                 I2C_1_ClearPendingInt();
 507:Generated_Source\PSoC5/I2C_1_INT.c ****             #else
 508:Generated_Source\PSoC5/I2C_1_INT.c ****                 /* Block execution flow: unexpected condition */
 509:Generated_Source\PSoC5/I2C_1_INT.c ****                 CYASSERT(0u != 0u);
 510:Generated_Source\PSoC5/I2C_1_INT.c ****             #endif /* (I2C_1_TIMEOUT_ENABLED) */
 511:Generated_Source\PSoC5/I2C_1_INT.c ****             }
 512:Generated_Source\PSoC5/I2C_1_INT.c ****         }
 513:Generated_Source\PSoC5/I2C_1_INT.c ****     #endif /* (I2C_1_MODE_SLAVE_ENABLED) */
 514:Generated_Source\PSoC5/I2C_1_INT.c ****     }
 515:Generated_Source\PSoC5/I2C_1_INT.c ****     else
 516:Generated_Source\PSoC5/I2C_1_INT.c ****     {
 517:Generated_Source\PSoC5/I2C_1_INT.c ****         /* The FSM skips master and slave processing: return to IDLE */
 518:Generated_Source\PSoC5/I2C_1_INT.c ****         I2C_1_state = I2C_1_SM_IDLE;
 431              		.loc 1 518 0
 432 0290 1022     		movs	r2, #16
 433 0292 024B     		ldr	r3, .L27+4
 434 0294 1A70     		strb	r2, [r3]
 435              	.LVL6:
 436              	.L1:
 437 0296 38BD     		pop	{r3, r4, r5, pc}
 438              	.L28:
 439              		.align	2
 440              	.L27:
 441 0298 D7490040 		.word	1073760727
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 18


 442 029c 00000000 		.word	I2C_1_state
 443 02a0 00000000 		.word	I2C_1_mstrWrBufSize
 444 02a4 00000000 		.word	I2C_1_mstrWrBufPtr
 445 02a8 D8490040 		.word	1073760728
 446 02ac 00000000 		.word	I2C_1_mstrWrBufIndex
 447 02b0 00000000 		.word	I2C_1_mstrControl
 448 02b4 00000000 		.word	I2C_1_mstrStatus
 449 02b8 80E100E0 		.word	-536813184
 450 02bc D6490040 		.word	1073760726
 451 02c0 D9490040 		.word	1073760729
 452 02c4 00000000 		.word	I2C_1_mstrRdBufIndex
 453 02c8 00000000 		.word	I2C_1_mstrRdBufPtr
 454 02cc 00000000 		.word	I2C_1_mstrRdBufSize
 455              		.cfi_endproc
 456              	.LFE0:
 457              		.size	I2C_1_ISR, .-I2C_1_ISR
 458              		.text
 459              	.Letext0:
 460              		.file 2 "Generated_Source\\PSoC5\\cytypes.h"
 461              		.file 3 "Generated_Source\\PSoC5\\I2C_1_PVT.h"
 462              		.file 4 "Generated_Source\\PSoC5\\CyLib.h"
 463              		.section	.debug_info,"",%progbits
 464              	.Ldebug_info0:
 465 0000 80010000 		.4byte	0x180
 466 0004 0400     		.2byte	0x4
 467 0006 00000000 		.4byte	.Ldebug_abbrev0
 468 000a 04       		.byte	0x4
 469 000b 01       		.uleb128 0x1
 470 000c 70000000 		.4byte	.LASF27
 471 0010 0C       		.byte	0xc
 472 0011 EB010000 		.4byte	.LASF28
 473 0015 03010000 		.4byte	.LASF29
 474 0019 00000000 		.4byte	.Ldebug_ranges0+0
 475 001d 00000000 		.4byte	0
 476 0021 00000000 		.4byte	.Ldebug_line0
 477 0025 02       		.uleb128 0x2
 478 0026 01       		.byte	0x1
 479 0027 06       		.byte	0x6
 480 0028 38020000 		.4byte	.LASF0
 481 002c 02       		.uleb128 0x2
 482 002d 01       		.byte	0x1
 483 002e 08       		.byte	0x8
 484 002f 62000000 		.4byte	.LASF1
 485 0033 02       		.uleb128 0x2
 486 0034 02       		.byte	0x2
 487 0035 05       		.byte	0x5
 488 0036 E1010000 		.4byte	.LASF2
 489 003a 02       		.uleb128 0x2
 490 003b 02       		.byte	0x2
 491 003c 07       		.byte	0x7
 492 003d 35000000 		.4byte	.LASF3
 493 0041 02       		.uleb128 0x2
 494 0042 04       		.byte	0x4
 495 0043 05       		.byte	0x5
 496 0044 23020000 		.4byte	.LASF4
 497 0048 02       		.uleb128 0x2
 498 0049 04       		.byte	0x4
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 19


 499 004a 07       		.byte	0x7
 500 004b 3A010000 		.4byte	.LASF5
 501 004f 02       		.uleb128 0x2
 502 0050 08       		.byte	0x8
 503 0051 05       		.byte	0x5
 504 0052 BB010000 		.4byte	.LASF6
 505 0056 02       		.uleb128 0x2
 506 0057 08       		.byte	0x8
 507 0058 07       		.byte	0x7
 508 0059 83010000 		.4byte	.LASF7
 509 005d 03       		.uleb128 0x3
 510 005e 04       		.byte	0x4
 511 005f 05       		.byte	0x5
 512 0060 696E7400 		.ascii	"int\000"
 513 0064 02       		.uleb128 0x2
 514 0065 04       		.byte	0x4
 515 0066 07       		.byte	0x7
 516 0067 76010000 		.4byte	.LASF8
 517 006b 04       		.uleb128 0x4
 518 006c 4C010000 		.4byte	.LASF9
 519 0070 02       		.byte	0x2
 520 0071 E901     		.2byte	0x1e9
 521 0073 2C000000 		.4byte	0x2c
 522 0077 04       		.uleb128 0x4
 523 0078 63010000 		.4byte	.LASF10
 524 007c 02       		.byte	0x2
 525 007d EB01     		.2byte	0x1eb
 526 007f 48000000 		.4byte	0x48
 527 0083 02       		.uleb128 0x2
 528 0084 04       		.byte	0x4
 529 0085 04       		.byte	0x4
 530 0086 5C000000 		.4byte	.LASF11
 531 008a 02       		.uleb128 0x2
 532 008b 08       		.byte	0x8
 533 008c 04       		.byte	0x4
 534 008d 52010000 		.4byte	.LASF12
 535 0091 02       		.uleb128 0x2
 536 0092 01       		.byte	0x1
 537 0093 08       		.byte	0x8
 538 0094 C9010000 		.4byte	.LASF13
 539 0098 04       		.uleb128 0x4
 540 0099 FE000000 		.4byte	.LASF14
 541 009d 02       		.byte	0x2
 542 009e 9302     		.2byte	0x293
 543 00a0 A4000000 		.4byte	0xa4
 544 00a4 05       		.uleb128 0x5
 545 00a5 6B000000 		.4byte	0x6b
 546 00a9 04       		.uleb128 0x4
 547 00aa 07000000 		.4byte	.LASF15
 548 00ae 02       		.byte	0x2
 549 00af 9502     		.2byte	0x295
 550 00b1 B5000000 		.4byte	0xb5
 551 00b5 05       		.uleb128 0x5
 552 00b6 77000000 		.4byte	0x77
 553 00ba 02       		.uleb128 0x2
 554 00bb 08       		.byte	0x8
 555 00bc 04       		.byte	0x4
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 20


 556 00bd 2C020000 		.4byte	.LASF16
 557 00c1 02       		.uleb128 0x2
 558 00c2 04       		.byte	0x4
 559 00c3 07       		.byte	0x7
 560 00c4 B2010000 		.4byte	.LASF17
 561 00c8 06       		.uleb128 0x6
 562 00c9 59010000 		.4byte	.LASF30
 563 00cd 01       		.byte	0x1
 564 00ce 2E       		.byte	0x2e
 565 00cf 00000000 		.4byte	.LFB0
 566 00d3 D0020000 		.4byte	.LFE0-.LFB0
 567 00d7 01       		.uleb128 0x1
 568 00d8 9C       		.byte	0x9c
 569 00d9 0F010000 		.4byte	0x10f
 570 00dd 07       		.uleb128 0x7
 571 00de 00000000 		.4byte	.LASF31
 572 00e2 01       		.byte	0x1
 573 00e3 34       		.byte	0x34
 574 00e4 6B000000 		.4byte	0x6b
 575 00e8 00000000 		.4byte	.LLST0
 576 00ec 08       		.uleb128 0x8
 577 00ed 2C010000 		.4byte	.LVL2
 578 00f1 78010000 		.4byte	0x178
 579 00f5 FF000000 		.4byte	0xff
 580 00f9 09       		.uleb128 0x9
 581 00fa 01       		.uleb128 0x1
 582 00fb 50       		.byte	0x50
 583 00fc 01       		.uleb128 0x1
 584 00fd 30       		.byte	0x30
 585 00fe 00       		.byte	0
 586 00ff 0A       		.uleb128 0xa
 587 0100 56020000 		.4byte	.LVL4
 588 0104 78010000 		.4byte	0x178
 589 0108 09       		.uleb128 0x9
 590 0109 01       		.uleb128 0x1
 591 010a 50       		.byte	0x50
 592 010b 01       		.uleb128 0x1
 593 010c 30       		.byte	0x30
 594 010d 00       		.byte	0
 595 010e 00       		.byte	0
 596 010f 0B       		.uleb128 0xb
 597 0110 6A010000 		.4byte	.LASF18
 598 0114 03       		.byte	0x3
 599 0115 23       		.byte	0x23
 600 0116 A4000000 		.4byte	0xa4
 601 011a 0B       		.uleb128 0xb
 602 011b 9A010000 		.4byte	.LASF19
 603 011f 03       		.byte	0x3
 604 0120 27       		.byte	0x27
 605 0121 A4000000 		.4byte	0xa4
 606 0125 0B       		.uleb128 0xb
 607 0126 58020000 		.4byte	.LASF20
 608 012a 03       		.byte	0x3
 609 012b 28       		.byte	0x28
 610 012c A4000000 		.4byte	0xa4
 611 0130 0B       		.uleb128 0xb
 612 0131 CE010000 		.4byte	.LASF21
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 21


 613 0135 03       		.byte	0x3
 614 0136 2B       		.byte	0x2b
 615 0137 3B010000 		.4byte	0x13b
 616 013b 0C       		.uleb128 0xc
 617 013c 04       		.byte	0x4
 618 013d A4000000 		.4byte	0xa4
 619 0141 0B       		.uleb128 0xb
 620 0142 44020000 		.4byte	.LASF22
 621 0146 03       		.byte	0x3
 622 0147 2C       		.byte	0x2c
 623 0148 A4000000 		.4byte	0xa4
 624 014c 0B       		.uleb128 0xb
 625 014d 0D000000 		.4byte	.LASF23
 626 0151 03       		.byte	0x3
 627 0152 2D       		.byte	0x2d
 628 0153 A4000000 		.4byte	0xa4
 629 0157 0B       		.uleb128 0xb
 630 0158 22000000 		.4byte	.LASF24
 631 015c 03       		.byte	0x3
 632 015d 30       		.byte	0x30
 633 015e 3B010000 		.4byte	0x13b
 634 0162 0B       		.uleb128 0xb
 635 0163 48000000 		.4byte	.LASF25
 636 0167 03       		.byte	0x3
 637 0168 31       		.byte	0x31
 638 0169 A4000000 		.4byte	0xa4
 639 016d 0B       		.uleb128 0xb
 640 016e 0E020000 		.4byte	.LASF26
 641 0172 03       		.byte	0x3
 642 0173 32       		.byte	0x32
 643 0174 A4000000 		.4byte	0xa4
 644 0178 0D       		.uleb128 0xd
 645 0179 AB010000 		.4byte	.LASF32
 646 017d AB010000 		.4byte	.LASF32
 647 0181 04       		.byte	0x4
 648 0182 7F       		.byte	0x7f
 649 0183 00       		.byte	0
 650              		.section	.debug_abbrev,"",%progbits
 651              	.Ldebug_abbrev0:
 652 0000 01       		.uleb128 0x1
 653 0001 11       		.uleb128 0x11
 654 0002 01       		.byte	0x1
 655 0003 25       		.uleb128 0x25
 656 0004 0E       		.uleb128 0xe
 657 0005 13       		.uleb128 0x13
 658 0006 0B       		.uleb128 0xb
 659 0007 03       		.uleb128 0x3
 660 0008 0E       		.uleb128 0xe
 661 0009 1B       		.uleb128 0x1b
 662 000a 0E       		.uleb128 0xe
 663 000b 55       		.uleb128 0x55
 664 000c 17       		.uleb128 0x17
 665 000d 11       		.uleb128 0x11
 666 000e 01       		.uleb128 0x1
 667 000f 10       		.uleb128 0x10
 668 0010 17       		.uleb128 0x17
 669 0011 00       		.byte	0
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 22


 670 0012 00       		.byte	0
 671 0013 02       		.uleb128 0x2
 672 0014 24       		.uleb128 0x24
 673 0015 00       		.byte	0
 674 0016 0B       		.uleb128 0xb
 675 0017 0B       		.uleb128 0xb
 676 0018 3E       		.uleb128 0x3e
 677 0019 0B       		.uleb128 0xb
 678 001a 03       		.uleb128 0x3
 679 001b 0E       		.uleb128 0xe
 680 001c 00       		.byte	0
 681 001d 00       		.byte	0
 682 001e 03       		.uleb128 0x3
 683 001f 24       		.uleb128 0x24
 684 0020 00       		.byte	0
 685 0021 0B       		.uleb128 0xb
 686 0022 0B       		.uleb128 0xb
 687 0023 3E       		.uleb128 0x3e
 688 0024 0B       		.uleb128 0xb
 689 0025 03       		.uleb128 0x3
 690 0026 08       		.uleb128 0x8
 691 0027 00       		.byte	0
 692 0028 00       		.byte	0
 693 0029 04       		.uleb128 0x4
 694 002a 16       		.uleb128 0x16
 695 002b 00       		.byte	0
 696 002c 03       		.uleb128 0x3
 697 002d 0E       		.uleb128 0xe
 698 002e 3A       		.uleb128 0x3a
 699 002f 0B       		.uleb128 0xb
 700 0030 3B       		.uleb128 0x3b
 701 0031 05       		.uleb128 0x5
 702 0032 49       		.uleb128 0x49
 703 0033 13       		.uleb128 0x13
 704 0034 00       		.byte	0
 705 0035 00       		.byte	0
 706 0036 05       		.uleb128 0x5
 707 0037 35       		.uleb128 0x35
 708 0038 00       		.byte	0
 709 0039 49       		.uleb128 0x49
 710 003a 13       		.uleb128 0x13
 711 003b 00       		.byte	0
 712 003c 00       		.byte	0
 713 003d 06       		.uleb128 0x6
 714 003e 2E       		.uleb128 0x2e
 715 003f 01       		.byte	0x1
 716 0040 3F       		.uleb128 0x3f
 717 0041 19       		.uleb128 0x19
 718 0042 03       		.uleb128 0x3
 719 0043 0E       		.uleb128 0xe
 720 0044 3A       		.uleb128 0x3a
 721 0045 0B       		.uleb128 0xb
 722 0046 3B       		.uleb128 0x3b
 723 0047 0B       		.uleb128 0xb
 724 0048 27       		.uleb128 0x27
 725 0049 19       		.uleb128 0x19
 726 004a 11       		.uleb128 0x11
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 23


 727 004b 01       		.uleb128 0x1
 728 004c 12       		.uleb128 0x12
 729 004d 06       		.uleb128 0x6
 730 004e 40       		.uleb128 0x40
 731 004f 18       		.uleb128 0x18
 732 0050 9742     		.uleb128 0x2117
 733 0052 19       		.uleb128 0x19
 734 0053 01       		.uleb128 0x1
 735 0054 13       		.uleb128 0x13
 736 0055 00       		.byte	0
 737 0056 00       		.byte	0
 738 0057 07       		.uleb128 0x7
 739 0058 34       		.uleb128 0x34
 740 0059 00       		.byte	0
 741 005a 03       		.uleb128 0x3
 742 005b 0E       		.uleb128 0xe
 743 005c 3A       		.uleb128 0x3a
 744 005d 0B       		.uleb128 0xb
 745 005e 3B       		.uleb128 0x3b
 746 005f 0B       		.uleb128 0xb
 747 0060 49       		.uleb128 0x49
 748 0061 13       		.uleb128 0x13
 749 0062 02       		.uleb128 0x2
 750 0063 17       		.uleb128 0x17
 751 0064 00       		.byte	0
 752 0065 00       		.byte	0
 753 0066 08       		.uleb128 0x8
 754 0067 898201   		.uleb128 0x4109
 755 006a 01       		.byte	0x1
 756 006b 11       		.uleb128 0x11
 757 006c 01       		.uleb128 0x1
 758 006d 31       		.uleb128 0x31
 759 006e 13       		.uleb128 0x13
 760 006f 01       		.uleb128 0x1
 761 0070 13       		.uleb128 0x13
 762 0071 00       		.byte	0
 763 0072 00       		.byte	0
 764 0073 09       		.uleb128 0x9
 765 0074 8A8201   		.uleb128 0x410a
 766 0077 00       		.byte	0
 767 0078 02       		.uleb128 0x2
 768 0079 18       		.uleb128 0x18
 769 007a 9142     		.uleb128 0x2111
 770 007c 18       		.uleb128 0x18
 771 007d 00       		.byte	0
 772 007e 00       		.byte	0
 773 007f 0A       		.uleb128 0xa
 774 0080 898201   		.uleb128 0x4109
 775 0083 01       		.byte	0x1
 776 0084 11       		.uleb128 0x11
 777 0085 01       		.uleb128 0x1
 778 0086 31       		.uleb128 0x31
 779 0087 13       		.uleb128 0x13
 780 0088 00       		.byte	0
 781 0089 00       		.byte	0
 782 008a 0B       		.uleb128 0xb
 783 008b 34       		.uleb128 0x34
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 24


 784 008c 00       		.byte	0
 785 008d 03       		.uleb128 0x3
 786 008e 0E       		.uleb128 0xe
 787 008f 3A       		.uleb128 0x3a
 788 0090 0B       		.uleb128 0xb
 789 0091 3B       		.uleb128 0x3b
 790 0092 0B       		.uleb128 0xb
 791 0093 49       		.uleb128 0x49
 792 0094 13       		.uleb128 0x13
 793 0095 3F       		.uleb128 0x3f
 794 0096 19       		.uleb128 0x19
 795 0097 3C       		.uleb128 0x3c
 796 0098 19       		.uleb128 0x19
 797 0099 00       		.byte	0
 798 009a 00       		.byte	0
 799 009b 0C       		.uleb128 0xc
 800 009c 0F       		.uleb128 0xf
 801 009d 00       		.byte	0
 802 009e 0B       		.uleb128 0xb
 803 009f 0B       		.uleb128 0xb
 804 00a0 49       		.uleb128 0x49
 805 00a1 13       		.uleb128 0x13
 806 00a2 00       		.byte	0
 807 00a3 00       		.byte	0
 808 00a4 0D       		.uleb128 0xd
 809 00a5 2E       		.uleb128 0x2e
 810 00a6 00       		.byte	0
 811 00a7 3F       		.uleb128 0x3f
 812 00a8 19       		.uleb128 0x19
 813 00a9 3C       		.uleb128 0x3c
 814 00aa 19       		.uleb128 0x19
 815 00ab 6E       		.uleb128 0x6e
 816 00ac 0E       		.uleb128 0xe
 817 00ad 03       		.uleb128 0x3
 818 00ae 0E       		.uleb128 0xe
 819 00af 3A       		.uleb128 0x3a
 820 00b0 0B       		.uleb128 0xb
 821 00b1 3B       		.uleb128 0x3b
 822 00b2 0B       		.uleb128 0xb
 823 00b3 00       		.byte	0
 824 00b4 00       		.byte	0
 825 00b5 00       		.byte	0
 826              		.section	.debug_loc,"",%progbits
 827              	.Ldebug_loc0:
 828              	.LLST0:
 829 0000 06000000 		.4byte	.LVL0
 830 0004 3C000000 		.4byte	.LVL1
 831 0008 0100     		.2byte	0x1
 832 000a 54       		.byte	0x54
 833 000b 3C000000 		.4byte	.LVL1
 834 000f 30010000 		.4byte	.LVL3
 835 0013 0100     		.2byte	0x1
 836 0015 55       		.byte	0x55
 837 0016 30010000 		.4byte	.LVL3
 838 001a 96020000 		.4byte	.LVL6
 839 001e 0100     		.2byte	0x1
 840 0020 54       		.byte	0x54
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 25


 841 0021 00000000 		.4byte	0
 842 0025 00000000 		.4byte	0
 843              		.section	.debug_aranges,"",%progbits
 844 0000 1C000000 		.4byte	0x1c
 845 0004 0200     		.2byte	0x2
 846 0006 00000000 		.4byte	.Ldebug_info0
 847 000a 04       		.byte	0x4
 848 000b 00       		.byte	0
 849 000c 0000     		.2byte	0
 850 000e 0000     		.2byte	0
 851 0010 00000000 		.4byte	.LFB0
 852 0014 D0020000 		.4byte	.LFE0-.LFB0
 853 0018 00000000 		.4byte	0
 854 001c 00000000 		.4byte	0
 855              		.section	.debug_ranges,"",%progbits
 856              	.Ldebug_ranges0:
 857 0000 00000000 		.4byte	.LFB0
 858 0004 D0020000 		.4byte	.LFE0
 859 0008 00000000 		.4byte	0
 860 000c 00000000 		.4byte	0
 861              		.section	.debug_line,"",%progbits
 862              	.Ldebug_line0:
 863 0000 14010000 		.section	.debug_str,"MS",%progbits,1
 863      02006000 
 863      00000201 
 863      FB0E0D00 
 863      01010101 
 864              	.LASF31:
 865 0000 746D7043 		.ascii	"tmpCsr\000"
 865      737200
 866              	.LASF15:
 867 0007 72656733 		.ascii	"reg32\000"
 867      3200
 868              	.LASF23:
 869 000d 4932435F 		.ascii	"I2C_1_mstrRdBufIndex\000"
 869      315F6D73 
 869      74725264 
 869      42756649 
 869      6E646578 
 870              	.LASF24:
 871 0022 4932435F 		.ascii	"I2C_1_mstrWrBufPtr\000"
 871      315F6D73 
 871      74725772 
 871      42756650 
 871      747200
 872              	.LASF3:
 873 0035 73686F72 		.ascii	"short unsigned int\000"
 873      7420756E 
 873      7369676E 
 873      65642069 
 873      6E7400
 874              	.LASF25:
 875 0048 4932435F 		.ascii	"I2C_1_mstrWrBufSize\000"
 875      315F6D73 
 875      74725772 
 875      42756653 
 875      697A6500 
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 26


 876              	.LASF11:
 877 005c 666C6F61 		.ascii	"float\000"
 877      7400
 878              	.LASF1:
 879 0062 756E7369 		.ascii	"unsigned char\000"
 879      676E6564 
 879      20636861 
 879      7200
 880              	.LASF27:
 881 0070 474E5520 		.ascii	"GNU C11 5.4.1 20160609 (release) [ARM/embedded-5-br"
 881      43313120 
 881      352E342E 
 881      31203230 
 881      31363036 
 882 00a3 616E6368 		.ascii	"anch revision 237715] -mcpu=cortex-m3 -mthumb -g -O"
 882      20726576 
 882      6973696F 
 882      6E203233 
 882      37373135 
 883 00d6 67202D66 		.ascii	"g -ffunction-sections -ffat-lto-objects\000"
 883      66756E63 
 883      74696F6E 
 883      2D736563 
 883      74696F6E 
 884              	.LASF14:
 885 00fe 72656738 		.ascii	"reg8\000"
 885      00
 886              	.LASF29:
 887 0103 433A5C53 		.ascii	"C:\\Software\\PSoC Cypress\\VCNL4030X01\\VCNL4030X0"
 887      6F667477 
 887      6172655C 
 887      50536F43 
 887      20437970 
 888 0132 312E6379 		.ascii	"1.cydsn\000"
 888      64736E00 
 889              	.LASF5:
 890 013a 6C6F6E67 		.ascii	"long unsigned int\000"
 890      20756E73 
 890      69676E65 
 890      6420696E 
 890      7400
 891              	.LASF9:
 892 014c 75696E74 		.ascii	"uint8\000"
 892      3800
 893              	.LASF12:
 894 0152 646F7562 		.ascii	"double\000"
 894      6C6500
 895              	.LASF30:
 896 0159 4932435F 		.ascii	"I2C_1_ISR\000"
 896      315F4953 
 896      5200
 897              	.LASF10:
 898 0163 75696E74 		.ascii	"uint32\000"
 898      333200
 899              	.LASF18:
 900 016a 4932435F 		.ascii	"I2C_1_state\000"
 900      315F7374 
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 27


 900      61746500 
 901              	.LASF8:
 902 0176 756E7369 		.ascii	"unsigned int\000"
 902      676E6564 
 902      20696E74 
 902      00
 903              	.LASF7:
 904 0183 6C6F6E67 		.ascii	"long long unsigned int\000"
 904      206C6F6E 
 904      6720756E 
 904      7369676E 
 904      65642069 
 905              	.LASF19:
 906 019a 4932435F 		.ascii	"I2C_1_mstrStatus\000"
 906      315F6D73 
 906      74725374 
 906      61747573 
 906      00
 907              	.LASF32:
 908 01ab 43794861 		.ascii	"CyHalt\000"
 908      6C7400
 909              	.LASF17:
 910 01b2 73697A65 		.ascii	"sizetype\000"
 910      74797065 
 910      00
 911              	.LASF6:
 912 01bb 6C6F6E67 		.ascii	"long long int\000"
 912      206C6F6E 
 912      6720696E 
 912      7400
 913              	.LASF13:
 914 01c9 63686172 		.ascii	"char\000"
 914      00
 915              	.LASF21:
 916 01ce 4932435F 		.ascii	"I2C_1_mstrRdBufPtr\000"
 916      315F6D73 
 916      74725264 
 916      42756650 
 916      747200
 917              	.LASF2:
 918 01e1 73686F72 		.ascii	"short int\000"
 918      7420696E 
 918      7400
 919              	.LASF28:
 920 01eb 47656E65 		.ascii	"Generated_Source\\PSoC5\\I2C_1_INT.c\000"
 920      72617465 
 920      645F536F 
 920      75726365 
 920      5C50536F 
 921              	.LASF26:
 922 020e 4932435F 		.ascii	"I2C_1_mstrWrBufIndex\000"
 922      315F6D73 
 922      74725772 
 922      42756649 
 922      6E646578 
 923              	.LASF4:
 924 0223 6C6F6E67 		.ascii	"long int\000"
ARM GAS  C:\Users\HWANYU~1\AppData\Local\Temp\ccJUnpbs.s 			page 28


 924      20696E74 
 924      00
 925              	.LASF16:
 926 022c 6C6F6E67 		.ascii	"long double\000"
 926      20646F75 
 926      626C6500 
 927              	.LASF0:
 928 0238 7369676E 		.ascii	"signed char\000"
 928      65642063 
 928      68617200 
 929              	.LASF22:
 930 0244 4932435F 		.ascii	"I2C_1_mstrRdBufSize\000"
 930      315F6D73 
 930      74725264 
 930      42756653 
 930      697A6500 
 931              	.LASF20:
 932 0258 4932435F 		.ascii	"I2C_1_mstrControl\000"
 932      315F6D73 
 932      7472436F 
 932      6E74726F 
 932      6C00
 933              		.ident	"GCC: (GNU Tools for ARM Embedded Processors) 5.4.1 20160609 (release) [ARM/embedded-5-bran
