<?xml version="1.0" encoding="utf-8"?>
<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
  <name>CY8C5888LTI_LP097</name>
  <version>0.1</version>
  <description>CY8C58LP</description>
  <addressUnitBits>8</addressUnitBits>
  <width>32</width>
  <peripherals>
    <peripheral>
      <name>CDC</name>
      <description>USBFS</description>
      <baseAddress>0x0</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x0</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>CR0</name>
          <description>USB Control 0 Register</description>
          <addressOffset>0x40006008</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>DEVICE_ADDRESS</name>
              <description>These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware when assigned during enumeration. It is not set automatically by the hardware.</description>
              <lsb>0</lsb>
              <msb>6</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>USB_ENABLE</name>
              <description>This bit enables the device to respond to USB traffic.</description>
              <lsb>7</lsb>
              <msb>7</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Disabled</name>
                  <description>Block responds to USB traffic.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Enabled</name>
                  <description>Block does not respond to USB traffic.</description>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>CR1</name>
          <description>USB Control 1 Register</description>
          <addressOffset>0x40006009</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>REG_ENABLE</name>
              <description>This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to connect the transceiver directly to the supply.</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Disabled</name>
                  <description>Regulator for 5V is disabled.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Enabled</name>
                  <description>Regulator for 5V is enabled.</description>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ENABLE_LOCK</name>
              <description>This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic.  Unless an external clock is being provided this bit should remain set for proper USB operation.</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>BUS_ACTIVITY</name>
              <description>The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High value until firmware clears it.</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>TRIM_OFFSET_MSB</name>
              <description>This bit enables trim bit[7].</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SIE_EP_INT_EN</name>
          <description>USB SIE Data Endpoints Interrupt Enable Register</description>
          <addressOffset>0x4000600A</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>EP1_INTR_EN</name>
              <description>Enables interrupt for EP1.</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>EP2_INTR_EN</name>
              <description>Enables interrupt for EP2.</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>EP3_INTR_EN</name>
              <description>Enables interrupt for EP3.</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>EP4_INTR_EN</name>
              <description>Enables interrupt for EP4.</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>EP5_INTR_EN</name>
              <description>Enables interrupt for EP5.</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>EP6_INTR_EN</name>
              <description>Enables interrupt for EP6.</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>EP7_INTR_EN</name>
              <description>Enables interrupt for EP7.</description>
              <lsb>6</lsb>
              <msb>6</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>EP8_INTR_EN</name>
              <description>Enables interrupt for EP8.</description>
              <lsb>7</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SIE_EP_INT_SR</name>
          <description>SIE Data Endpoint Interrupt Status Register</description>
          <addressOffset>0x4000600B</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>EP1_INTR</name>
              <description>Interrupt status for EP1.</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>EP2_INTR</name>
              <description>Interrupt status for EP2.</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>EP3_INTR</name>
              <description>Interrupt status for EP3.</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>EP4_INTR</name>
              <description>Interrupt status for EP4.</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>EP5_INTR</name>
              <description>Interrupt status for EP5.</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>EP6_INTR</name>
              <description>Interrupt status for EP6.</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>EP7_INTR</name>
              <description>Interrupt status for EP7.</description>
              <lsb>6</lsb>
              <msb>6</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>EP8_INTR</name>
              <description>Interrupt status for EP8.</description>
              <lsb>7</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SIE_EP1_CNT0</name>
          <description>SIE Endpoint 1 Count0 Register</description>
          <addressOffset>0x4000600C</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>DATA_COUNT_MSB</name>
              <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
              <lsb>0</lsb>
              <msb>2</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA_VALID</name>
              <description>DATA_ERROR - 0, DATA_VALID - 1.</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA_TOGGLE</name>
              <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
              <lsb>7</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SIE_EP1_CNT1</name>
          <description>SIE Endpoint 1 Count1 Register</description>
          <addressOffset>0x4000600D</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>DATA_COUNT</name>
              <description>These bits are the 8 LSb of a 11-bit counter.  The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
              <lsb>0</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SIE_EP1_CR0</name>
          <description>SIE Endpoint 1 Control Register</description>
          <addressOffset>0x4000600E</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
              <lsb>0</lsb>
              <msb>3</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLE</name>
                  <description>Ignore all USB traffic to this endpoint.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NAK_INOUT</name>
                  <description>SETUP: Accept, IN: NAK, OUT: NAK.</description>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STATUS_OUT_ONLY</name>
                  <description>SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others.</description>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STALL_INOUT</name>
                  <description>SETUP: Accept, IN: STALL, OUT: STALL.</description>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ISO_OUT</name>
                  <description>SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token.</description>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STATUS_IN_ONLY</name>
                  <description>SETUP: Accept, IN: Respond with 0B data, OUT:  Stall.</description>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ISO_IN</name>
                  <description>SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore.</description>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NAK_OUT</name>
                  <description>SETUP: Ignore, IN: Ignore, OUT: NAK.</description>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ACK_OUT</name>
                  <description>SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token.</description>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ACK_OUT_STATUS_IN</name>
                  <description>SETUP: Accept, IN: Respond with 0B data, OUT:  Accept data.</description>
                  <value>11</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NAK_IN</name>
                  <description>SETUP: Ignore, IN: NAK, OUT: Ignore.</description>
                  <value>12</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ACK_IN</name>
                  <description>SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore</description>
                  <value>13</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ACK_IN_STATUS_OUT</name>
                  <description>SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others.</description>
                  <value>15</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ACKED_TXN</name>
              <description>ACKED_NO - 0, ACKED_YES - 1.</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>NAK_INT_EN</name>
              <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>ERR_IN_TXN</name>
              <description>The Error in transaction bit is set whenever an error is detected.</description>
              <lsb>6</lsb>
              <msb>6</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>STALL</name>
              <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
              <lsb>7</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>USBIO_CR0</name>
          <description>USBIO Control 0 Register</description>
          <addressOffset>0x40006010</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>RD</name>
              <description>Received Data. This read only bit gives the state of the USB differential receiver.</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-only</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DIFF_LOW</name>
                  <description>D+ less than D- (K state), or D+=D-=0 (SE0).</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>DIFF_HIGH</name>
                  <description>D+ greater than D- (J state).</description>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TD</name>
              <description>Transmit Data. Transmit a USB J or K state on the USB bus. No effect if TEN=0 or TSE0=1.</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DIFF_K</name>
                  <description>Force USB K state (D+ is low D- is high).</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>DIFF_J</name>
                  <description>Force USB J state (D+ is high D- is low).</description>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>TSE0</name>
              <description>Transmit Single-Ended Zero. SE0: both D+ and D- low. No effect if TEN=0.</description>
              <lsb>6</lsb>
              <msb>6</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>TEN</name>
              <description>USB Transmit Enable. This is used to manually transmit on the D+ and D- pins. Normally this bit should be cleared to allow the internal SIE to drive the pins. The most common reason for manually transmitting is to force a resume state on the bus.</description>
              <lsb>7</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>USBIO_CR1</name>
          <description>USBIO Control 1 Register</description>
          <addressOffset>0x40006012</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>DMO</name>
              <description>This read only bit gives the state of the D- pin.</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>DPO</name>
              <description>This read only bit gives the state of the D+ pin.</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>USBPUEN</name>
              <description>This bit enables the connection of the internal 1.5 k pull up resistor on the D+ pin.</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>IOMODE</name>
              <description>This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes. If this bit is set the DMI and DPI bits are used to drive the D- and D+ pins.</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Bit_banged</name>
                  <description>Bit-banged mode for Dm and Dp.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>USB</name>
                  <description>USB block controls Dm and Dp.</description>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>SIE_EP2_CNT0</name>
          <description>SIE Endpoint 1 Count0 Register</description>
          <addressOffset>0x4000601C</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>DATA_COUNT_MSB</name>
              <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
              <lsb>0</lsb>
              <msb>2</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA_VALID</name>
              <description>DATA_ERROR - 0, DATA_VALID - 1.</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA_TOGGLE</name>
              <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
              <lsb>7</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SIE_EP2_CNT1</name>
          <description>SIE Endpoint 1 Count1 Register</description>
          <addressOffset>0x4000601D</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>DATA_COUNT</name>
              <description>These bits are the 8 LSb of a 11-bit counter.  The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
              <lsb>0</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SIE_EP2_CR0</name>
          <description>SIE Endpoint 1 Control Register</description>
          <addressOffset>0x4000601E</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
              <lsb>0</lsb>
              <msb>3</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLE</name>
                  <description>Ignore all USB traffic to this endpoint.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NAK_INOUT</name>
                  <description>SETUP: Accept, IN: NAK, OUT: NAK.</description>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STATUS_OUT_ONLY</name>
                  <description>SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others.</description>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STALL_INOUT</name>
                  <description>SETUP: Accept, IN: STALL, OUT: STALL.</description>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ISO_OUT</name>
                  <description>SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token.</description>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STATUS_IN_ONLY</name>
                  <description>SETUP: Accept, IN: Respond with 0B data, OUT:  Stall.</description>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ISO_IN</name>
                  <description>SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore.</description>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NAK_OUT</name>
                  <description>SETUP: Ignore, IN: Ignore, OUT: NAK.</description>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ACK_OUT</name>
                  <description>SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token.</description>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ACK_OUT_STATUS_IN</name>
                  <description>SETUP: Accept, IN: Respond with 0B data, OUT:  Accept data.</description>
                  <value>11</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NAK_IN</name>
                  <description>SETUP: Ignore, IN: NAK, OUT: Ignore.</description>
                  <value>12</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ACK_IN</name>
                  <description>SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore</description>
                  <value>13</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ACK_IN_STATUS_OUT</name>
                  <description>SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others.</description>
                  <value>15</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ACKED_TXN</name>
              <description>ACKED_NO - 0, ACKED_YES - 1.</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>NAK_INT_EN</name>
              <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>ERR_IN_TXN</name>
              <description>The Error in transaction bit is set whenever an error is detected.</description>
              <lsb>6</lsb>
              <msb>6</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>STALL</name>
              <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
              <lsb>7</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>EP0_CR</name>
          <description>Endpoint0 control Register</description>
          <addressOffset>0x40006028</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
              <lsb>0</lsb>
              <msb>3</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLE</name>
                  <description>Ignore all USB traffic to this endpoint.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NAK_INOUT</name>
                  <description>SETUP: Accept, IN: NAK, OUT: NAK.</description>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STATUS_OUT_ONLY</name>
                  <description>SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others.</description>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STALL_INOUT</name>
                  <description>SETUP: Accept, IN: STALL, OUT: STALL.</description>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ISO_OUT</name>
                  <description>SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token.</description>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STATUS_IN_ONLY</name>
                  <description>SETUP: Accept, IN: Respond with 0B data, OUT:  Stall.</description>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ISO_IN</name>
                  <description>SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore.</description>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NAK_OUT</name>
                  <description>SETUP: Ignore, IN: Ignore, OUT: NAK.</description>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ACK_OUT</name>
                  <description>SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token.</description>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ACK_OUT_STATUS_IN</name>
                  <description>SETUP: Accept, IN: Respond with 0B data, OUT:  Accept data.</description>
                  <value>11</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NAK_IN</name>
                  <description>SETUP: Ignore, IN: NAK, OUT: Ignore.</description>
                  <value>12</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ACK_IN</name>
                  <description>SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore</description>
                  <value>13</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ACK_IN_STATUS_OUT</name>
                  <description>SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others.</description>
                  <value>15</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ACKED_TXN</name>
              <description>ACKED_NO - 0, ACKED_YES - 1.</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>NAK_INT_EN</name>
              <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>ERR_IN_TXN</name>
              <description>The Error in transaction bit is set whenever an error is detected.</description>
              <lsb>6</lsb>
              <msb>6</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>STALL</name>
              <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
              <lsb>7</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>EP0_CNT</name>
          <description>Endpoint0 control Register</description>
          <addressOffset>0x40006029</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>BYTE_COUNT</name>
              <description>These bits indicate the number of data bytes in a transaction. For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8. For OUT or SETUP transactions the count is updated by hardware to the number of data bytes received plus two for the CRC bytes. Valid values are 2 to 10.</description>
              <lsb>0</lsb>
              <msb>3</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA_VALID</name>
              <description>This bit is used for OUT/SETUP transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DATA_ERROR</name>
                  <description>No ACK'd transactions since bit was last cleared.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>DATA_VALID</name>
                  <description>Indicates a transaction ended with an ACK.</description>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>DATA_TOGGLE</name>
              <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SIE_EP3_CNT0</name>
          <description>SIE Endpoint 1 Count0 Register</description>
          <addressOffset>0x4000602C</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>DATA_COUNT_MSB</name>
              <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
              <lsb>0</lsb>
              <msb>2</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA_VALID</name>
              <description>DATA_ERROR - 0, DATA_VALID - 1.</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>DATA_TOGGLE</name>
              <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
              <lsb>7</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SIE_EP3_CNT1</name>
          <description>SIE Endpoint 1 Count1 Register</description>
          <addressOffset>0x4000602D</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>DATA_COUNT</name>
              <description>These bits are the 8 LSb of a 11-bit counter.  The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
              <lsb>0</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>SIE_EP3_CR0</name>
          <description>SIE Endpoint 1 Control Register</description>
          <addressOffset>0x4000602E</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>MODE</name>
              <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
              <lsb>0</lsb>
              <msb>3</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DISABLE</name>
                  <description>Ignore all USB traffic to this endpoint.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NAK_INOUT</name>
                  <description>SETUP: Accept, IN: NAK, OUT: NAK.</description>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STATUS_OUT_ONLY</name>
                  <description>SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others.</description>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STALL_INOUT</name>
                  <description>SETUP: Accept, IN: STALL, OUT: STALL.</description>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ISO_OUT</name>
                  <description>SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token.</description>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>STATUS_IN_ONLY</name>
                  <description>SETUP: Accept, IN: Respond with 0B data, OUT:  Stall.</description>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ISO_IN</name>
                  <description>SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore.</description>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NAK_OUT</name>
                  <description>SETUP: Ignore, IN: Ignore, OUT: NAK.</description>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ACK_OUT</name>
                  <description>SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token.</description>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ACK_OUT_STATUS_IN</name>
                  <description>SETUP: Accept, IN: Respond with 0B data, OUT:  Accept data.</description>
                  <value>11</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>NAK_IN</name>
                  <description>SETUP: Ignore, IN: NAK, OUT: Ignore.</description>
                  <value>12</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ACK_IN</name>
                  <description>SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore</description>
                  <value>13</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>ACK_IN_STATUS_OUT</name>
                  <description>SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others.</description>
                  <value>15</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>ACKED_TXN</name>
              <description>ACKED_NO - 0, ACKED_YES - 1.</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>NAK_INT_EN</name>
              <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>ERR_IN_TXN</name>
              <description>The Error in transaction bit is set whenever an error is detected.</description>
              <lsb>6</lsb>
              <msb>6</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>STALL</name>
              <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
              <lsb>7</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ARB_EP1_CFG</name>
          <description>Arbiter Endpoint 1 Configuration Register</description>
          <addressOffset>0x40006080</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>IN_DATA_RDY</name>
              <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>DMA_REQ</name>
              <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>CRC_BYPASS</name>
              <description>CRC_NORMAL - 0, CRC_BYPASS - 1</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>RESET_PTR</name>
              <description>RESET_KRYPTON - 0, RESET_NORMAL - 1</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ARB_EP1_INT_EN</name>
          <description>Arbiter Endpoint 1 Interrupt Enable Register</description>
          <addressOffset>0x40006081</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>IN_BUF_FULL_EN</name>
              <description>IN Endpoint Local Buffer Full</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>DMA_GNT_EN</name>
              <description>Endpoint DMA Grant</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>BUF_OVER_EN</name>
              <description>Endpoint Buffer Overflow</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>BUF_UNDER_EN</name>
              <description>Endpoint Buffer Underflow</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>ERR_INT_EN</name>
              <description>Endpoint Error in Transaction Interrupt</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>DMA_TERMIN_EN</name>
              <description>Endpoint DMA Terminated Enable</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ARB_EP1_INT_SR</name>
          <description>Arbiter Endpoint 1 Interrupt Status Register</description>
          <addressOffset>0x40006082</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>IN_BUF_FULL_EN</name>
              <description>IN Endpoint Local Buffer Full</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>DMA_GNT_EN</name>
              <description>Endpoint DMA Grant</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>BUF_OVER_EN</name>
              <description>Endpoint Buffer Overflow</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>BUF_UNDER_EN</name>
              <description>Endpoint Buffer Underflow</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>ERR_INT_EN</name>
              <description>Endpoint Error in Transaction Interrupt</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>DMA_TERMIN_EN</name>
              <description>Endpoint DMA Terminated Enable</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ARB_RW1_WA</name>
          <description>Arbiter Endpoint 1 Write Address LSB Register</description>
          <addressOffset>0x40006084</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>WA8</name>
              <description>Write Address for EP.</description>
              <lsb>0</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ARB_RW1_WA_MSB</name>
          <description>Arbiter Endpoint 1 Write Address MSB Register</description>
          <addressOffset>0x40006085</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>WA9</name>
              <description>Write Address for EP MSB.</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ARB_RW1_RA</name>
          <description>Arbiter Endpoint 1 Read Address LSB Register</description>
          <addressOffset>0x40006086</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>RA8</name>
              <description>Read Address for EP MSB.</description>
              <lsb>0</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ARB_RW1_RA_MSB</name>
          <description>Arbiter Endpoint 1 Read Address MSB Register</description>
          <addressOffset>0x40006087</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>RA9</name>
              <description>Read Address for EP MSB.</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ARB_EP2_CFG</name>
          <description>Arbiter Endpoint 1 Configuration Register</description>
          <addressOffset>0x40006090</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>IN_DATA_RDY</name>
              <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>DMA_REQ</name>
              <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>CRC_BYPASS</name>
              <description>CRC_NORMAL - 0, CRC_BYPASS - 1</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>RESET_PTR</name>
              <description>RESET_KRYPTON - 0, RESET_NORMAL - 1</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ARB_EP2_INT_EN</name>
          <description>Arbiter Endpoint 1 Interrupt Enable Register</description>
          <addressOffset>0x40006091</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>IN_BUF_FULL_EN</name>
              <description>IN Endpoint Local Buffer Full</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>DMA_GNT_EN</name>
              <description>Endpoint DMA Grant</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>BUF_OVER_EN</name>
              <description>Endpoint Buffer Overflow</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>BUF_UNDER_EN</name>
              <description>Endpoint Buffer Underflow</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>ERR_INT_EN</name>
              <description>Endpoint Error in Transaction Interrupt</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>DMA_TERMIN_EN</name>
              <description>Endpoint DMA Terminated Enable</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ARB_EP2_INT_SR</name>
          <description>Arbiter Endpoint 1 Interrupt Status Register</description>
          <addressOffset>0x40006092</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>IN_BUF_FULL_EN</name>
              <description>IN Endpoint Local Buffer Full</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>DMA_GNT_EN</name>
              <description>Endpoint DMA Grant</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>BUF_OVER_EN</name>
              <description>Endpoint Buffer Overflow</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>BUF_UNDER_EN</name>
              <description>Endpoint Buffer Underflow</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>ERR_INT_EN</name>
              <description>Endpoint Error in Transaction Interrupt</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>DMA_TERMIN_EN</name>
              <description>Endpoint DMA Terminated Enable</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ARB_RW2_WA</name>
          <description>Arbiter Endpoint 1 Write Address LSB Register</description>
          <addressOffset>0x40006094</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>WA8</name>
              <description>Write Address for EP.</description>
              <lsb>0</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ARB_RW2_WA_MSB</name>
          <description>Arbiter Endpoint 1 Write Address MSB Register</description>
          <addressOffset>0x40006095</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>WA9</name>
              <description>Write Address for EP MSB.</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ARB_RW2_RA</name>
          <description>Arbiter Endpoint 1 Read Address LSB Register</description>
          <addressOffset>0x40006096</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>RA8</name>
              <description>Read Address for EP MSB.</description>
              <lsb>0</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ARB_RW2_RA_MSB</name>
          <description>Arbiter Endpoint 1 Read Address MSB Register</description>
          <addressOffset>0x40006097</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>RA9</name>
              <description>Read Address for EP MSB.</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ARB_CFG</name>
          <description>Arbiter configuration register</description>
          <addressOffset>0x4000609C</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>AUTO_MEM</name>
              <description>Enables Auto Memory Configuration.  Manual memory configuration by default.</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>DMA_CFG</name>
              <description>DMA Access Configuration.</description>
              <lsb>5</lsb>
              <msb>6</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>DMA_NONE</name>
                  <description>No DMA.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>DMA_MANUAL</name>
                  <description>Manual DMA.</description>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>DMA_AUTO</name>
                  <description>Auto DMA.</description>
                  <value>2</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
            <field>
              <name>CFG_CMP</name>
              <description>Register Configuration Complete Indication. Posedge is detected on this bit. Hence a 0 to 1 transition is required.</description>
              <lsb>7</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>USB_CLK_EN</name>
          <description>USB Control 0 Register</description>
          <addressOffset>0x4000609D</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>CSR_CLK_EN</name>
              <description>Clock Enable for Core Logic clocked by AHB bus clock.</description>
              <lsb>7</lsb>
              <msb>7</msb>
              <access>read-write</access>
              <enumeratedValues>
                <enumeratedValue>
                  <name>Disabled</name>
                  <description>Disables clock to UBS block.</description>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>Enabled</name>
                  <description>Enables clock to UBS block.</description>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
            </field>
          </fields>
        </register>
        <register>
          <name>ARB_INT_EN</name>
          <description>Arbiter Interrupt Enable Register</description>
          <addressOffset>0x4000609E</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>EP1_INTR_EN</name>
              <description>Enables interrupt for EP1.</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>EP2_INTR_EN</name>
              <description>Enables interrupt for EP2.</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>EP3_INTR_EN</name>
              <description>Enables interrupt for EP3.</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>EP4_INTR_EN</name>
              <description>Enables interrupt for EP4.</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>EP5_INTR_EN</name>
              <description>Enables interrupt for EP5.</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>EP6_INTR_EN</name>
              <description>Enables interrupt for EP6.</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>EP7_INTR_EN</name>
              <description>Enables interrupt for EP7.</description>
              <lsb>6</lsb>
              <msb>6</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>EP8_INTR_EN</name>
              <description>Enables interrupt for EP8.</description>
              <lsb>7</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ARB_INT_SR</name>
          <description>Arbiter Interrupt Status</description>
          <addressOffset>0x4000609F</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>EP1_INTR</name>
              <description>Interrupt status for EP1.</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>EP2_INTR</name>
              <description>Interrupt status for EP2.</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>EP3_INTR</name>
              <description>Interrupt status for EP3.</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>EP4_INTR</name>
              <description>Interrupt status for EP4.</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>EP5_INTR</name>
              <description>Interrupt status for EP5.</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>EP6_INTR</name>
              <description>Interrupt status for EP6.</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>EP7_INTR</name>
              <description>Interrupt status for EP7.</description>
              <lsb>6</lsb>
              <msb>6</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>EP8_INTR</name>
              <description>Interrupt status for EP8.</description>
              <lsb>7</lsb>
              <msb>7</msb>
              <access>read-only</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ARB_EP3_CFG</name>
          <description>Arbiter Endpoint 1 Configuration Register</description>
          <addressOffset>0x400060A0</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>IN_DATA_RDY</name>
              <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>DMA_REQ</name>
              <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>CRC_BYPASS</name>
              <description>CRC_NORMAL - 0, CRC_BYPASS - 1</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>RESET_PTR</name>
              <description>RESET_KRYPTON - 0, RESET_NORMAL - 1</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ARB_EP3_INT_EN</name>
          <description>Arbiter Endpoint 1 Interrupt Enable Register</description>
          <addressOffset>0x400060A1</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>IN_BUF_FULL_EN</name>
              <description>IN Endpoint Local Buffer Full</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>DMA_GNT_EN</name>
              <description>Endpoint DMA Grant</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>BUF_OVER_EN</name>
              <description>Endpoint Buffer Overflow</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>BUF_UNDER_EN</name>
              <description>Endpoint Buffer Underflow</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>ERR_INT_EN</name>
              <description>Endpoint Error in Transaction Interrupt</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>DMA_TERMIN_EN</name>
              <description>Endpoint DMA Terminated Enable</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ARB_EP3_INT_SR</name>
          <description>Arbiter Endpoint 1 Interrupt Status Register</description>
          <addressOffset>0x400060A2</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>IN_BUF_FULL_EN</name>
              <description>IN Endpoint Local Buffer Full</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>DMA_GNT_EN</name>
              <description>Endpoint DMA Grant</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>BUF_OVER_EN</name>
              <description>Endpoint Buffer Overflow</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>BUF_UNDER_EN</name>
              <description>Endpoint Buffer Underflow</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>ERR_INT_EN</name>
              <description>Endpoint Error in Transaction Interrupt</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>DMA_TERMIN_EN</name>
              <description>Endpoint DMA Terminated Enable</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ARB_RW3_WA</name>
          <description>Arbiter Endpoint 1 Write Address LSB Register</description>
          <addressOffset>0x400060A4</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>WA8</name>
              <description>Write Address for EP.</description>
              <lsb>0</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ARB_RW3_WA_MSB</name>
          <description>Arbiter Endpoint 1 Write Address MSB Register</description>
          <addressOffset>0x400060A5</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>WA9</name>
              <description>Write Address for EP MSB.</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ARB_RW3_RA</name>
          <description>Arbiter Endpoint 1 Read Address LSB Register</description>
          <addressOffset>0x400060A6</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>RA8</name>
              <description>Read Address for EP MSB.</description>
              <lsb>0</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>ARB_RW3_RA_MSB</name>
          <description>Arbiter Endpoint 1 Read Address MSB Register</description>
          <addressOffset>0x400060A7</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>RA9</name>
              <description>Read Address for EP MSB.</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
    <peripheral>
      <name>I2C_1</name>
      <description>No description available</description>
      <baseAddress>0x0</baseAddress>
      <addressBlock>
        <offset>0</offset>
        <size>0x0</size>
        <usage>registers</usage>
      </addressBlock>
      <registers>
        <register>
          <name>I2C_1_FF_XCFG</name>
          <description>I2C Extended Configuration Register</description>
          <addressOffset>0x400049C8</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>csr_clk_en</name>
              <description>This bit is used for gating system clock for the blocks core logic that is not associated with AHB interface. Clock is made available to the core logic only when this bit is set to 1 and the input pin ext_clk_en is also active. If either of them is not active, the blocks core logic does not receive the system clock.</description>
              <lsb>7</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>i2c_on</name>
              <description>This bit should be set by the user during initial block configuration if the user wants to use the I2C block as wake-up source. Only when this bit set along with other bits mentioned in the sleep mode section, the I2C wakes up system from sleep on address match.</description>
              <lsb>6</lsb>
              <msb>6</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>ready_to_sleep</name>
              <description>Once the user sets the force_nack bit, the I2C block sets this bit if I2C is not busy or it waits for ongoing transaction to be completed and then sets this bit. As long as this bit is set, the I2C block is going to nack all the transactions.Clearing force_nack bit automatically clears this bit. HW clears this bit automatically on assertion of PD (Power Down)</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>force_nack</name>
              <description>This bit must be set by the user before putting the device to sleep and wait for ready_to_sleep status bit to be set. This can be cleared by user by writing '0' and the HW clears it automatically on assertion of PD(Power Down)</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>hw_addr_en</name>
              <description>When this bit is set to a '1', hardware address compare is enabled. On an address match, an interrupt is generated, CSR register bit 3 is set, and the clock is stalled until the CPU writes a 0 into the CSR register bit 3. The address is automatically ACKed on a match. On an address mismatch,no interrupt is generated, clock is not stalled, and bit 3 in the CSR register is set. The CPU must write a 0 into the CSR register bit 3 to clear it. The address is automatically NACKed on a mismatch. You must configure the compare address in the ADR register. When this bit is set to a '0', software address compare is enabled. An interrupt is generated, the clock is stalled, and CSR register bit 3 is set when the received address byte is available in the Data register; to enable the CPU to do a firmware address compare. The clock is stalled until the CPU writes a 0 into the CSR register bit 3. The functionality of this bit is independent of the data buffering mode.</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>I2C_1_FF_ADDR</name>
          <description>I2C Slave Adddress Register</description>
          <addressOffset>0x400049CA</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>slave_address</name>
              <description>These seven bits hold the slave's own device address. These bits are held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>0</lsb>
              <msb>6</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>I2C_1_FF_CFG</name>
          <description>I2C Configuration Register</description>
          <addressOffset>0x400049D6</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>sio_select</name>
              <description>I2C Pin Select for SCL/SDA lines from SIO1/SIO2, 0 = SCL and SDA lines get their inputs from SIO1 module.sclk_str1 and sda_ack1 are driven to SIO1 module and they get asserted once device wakes up from sleep. 1 = SCL and SDA lines get their inputs from SIO2 module. sclk_str2 and sda_ack2 are driven to SIO2 module and they get asserted once device wakes up from sleep. This bit is valid only when I2C.CFG[6] is asserted.</description>
              <lsb>7</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>pselect</name>
              <description>I2C Pin Select for SCL/SDA lines from GPIO/SIO, 0 = SCL and SDA lines get their inputs from GPIO module.sclk_str0 and sda_ack0 are driven to GPIO module and they get asserted once device wakes up from sleep. 1 = SCL and SDA lines get their inputs from one of the SIO Blocks that is chosen based on the configuration of bit I2C.CFG[7]</description>
              <lsb>6</lsb>
              <msb>6</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>bus_error_ie</name>
              <description>Bus Error Interrupt Enable 0 disabled 1 enabled. An interrupt is generated on the detection of a Bus error condition.</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>stop_ie</name>
              <description>Stop Interrupt Enable 0 disabled 1 enabled. An interrupt is generated on the detection of a Stop condition.</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>clock_rate</name>
              <description>0 Samples/bit is 16, 1 Samples/bit is 32</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>en_mstr</name>
              <description>Enables master mode for the device</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>en_slave</name>
              <description>Enables Slave mode for the device</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>I2C_1_FF_CSR</name>
          <description>I2C Control and Status Register</description>
          <addressOffset>0x400049D7</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>bus_error</name>
              <description>It must be cleared by firmware by writing a '0' to the bit position. It is never cleared by the hardware. 1 a misplaced Start or Stop condition was detected. This bit is held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>7</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>lost_arb</name>
              <description>This bit is set immediately on lost arbitration; however, it does not cause an interrupt. This status may be checked after the following Byte Complete interrupt. Any Start detect or a write to the Start or Restart generate bits (MCSR register), when operating in Master mode, will also clear the bit. 1 lost Arbitration. This bit is held zero if I2C_CFG.en_mstr is zero.</description>
              <lsb>6</lsb>
              <msb>6</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>stop_status</name>
              <description>It must be cleared by firmware with write of '0' to the bit position. It is never cleared by the hardware. 1 a Stop condition was detected. This bit is held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>5</lsb>
              <msb>5</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>ack</name>
              <description>Acknowledge Out. Bit is automatically cleared by hardware on a Byte Complete event. 0 nack the last received byte. 1 ack the last received byte</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>address</name>
              <description>It must be cleared by firmware with write of '0' to the bit position. 1 the received byte is a slave address. This bit is held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>transmit</name>
              <description>Bit is set by firmware to define the direction of the byte transfer. Any Start detect will clear the bit. 0 receive mode 1 transmit mode. This bit is held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>lrb</name>
              <description>Last Received Bit. The value of the 9th bit in a Transmit sequence, which is the acknowledge bit from the receiver. Any Start detect or a write to the Start or Restart generate bits, when operating in Master mode, will also clear the bit. 0 last transmitted byte was ACK'ed by the receiver. 1 last transmitted byte was NACK'ed by the receiver. This bit is held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>byte_complete</name>
              <description>Transmit/Receive Mode: 0 no completed transmit/receive since last cleared by firmware. Any Start detect or a write to the start or Restart generate bits, when operating in Master mode, will also clear the bit. Transmit mode: 1 eight bits of data have been transmitted and an ACK or NACK has been received. Receive mode: 1 eight bits of data have been received. This bit is held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>I2C_1_FF_DATA</name>
          <description>I2C Data Register</description>
          <addressOffset>0x400049D8</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>data</name>
              <description>Read received data or write data to transmit. These bits are held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>0</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>I2C_1_FF_MCSR</name>
          <description>Master Control and Status Register: I2C_MCSR</description>
          <addressOffset>0x400049D9</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>stop_gen</name>
              <description>This bit is set only for master transmitter and used at the end of byte transfer. After byte complete status is set, if this bit is set followed by the Transmit bit in I2C.CSR register, Stop condition is generated after byte complete. This bit is automatically reset to 0 after the Stop, start or Restart has been generated. During data phase, if Stop Gen bit is set to 0, clearing the Transmit bit in I2C.CSR register will also generate a Stop condition. This bit is held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>bus_busy</name>
              <description>This bit is set to the following. 0 when a Stop condition is detected (from any bus master). 1 when a Start condition is detected (from any bus master). This bit is held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>master_mode</name>
              <description>This bit is set/cleared by hardware when the device is operating as a master. 0 stop condition detected, generated by this device. 1 start condition detected, generated by this device. This bit is held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>restart_gen</name>
              <description>This bit is cleared by hardware when the Restart generation is complete. 0 restart generation complete. 1 generate a Restart condition. This bit is held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>start_gen</name>
              <description>This bit is cleared by hardware when the Start generation is complete. 0 start generation complete. 1 generate a Start condition and send a byte (address) to the I2C bus, if bus is not busy. This bit is held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>I2C_1_FF_CLK_DIV1</name>
          <description>I2C Clock Divide Factor Register-1</description>
          <addressOffset>0x400049DB</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>Div</name>
              <description>The configuration of this register along with that in register CLK_DIV2 defines the factor by which the SYSCLK will be divided in the I2C block. These bits are held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>0</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>I2C_1_FF_CLK_DIV2</name>
          <description>I2C Clock Divide Factor Register-2</description>
          <addressOffset>0x400049DC</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>Div</name>
              <description>The configuration of this register along with that in register CLK_DIV1 defines the factor by whichthe SYSCLK will be divided in the I2C block. These bits are held zero if I2C_CFG.en_mstr and I2C_CFG.en_slave are both zero.</description>
              <lsb>0</lsb>
              <msb>1</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>I2C_1_FF__TMOUT_CSR</name>
          <description>I2C Timerout Control and Status Register</description>
          <addressOffset>0x400049DD</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>sda_pin_status</name>
              <description>SDA Line status.</description>
              <lsb>4</lsb>
              <msb>4</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>scl_pin_status</name>
              <description>SCL Line status.</description>
              <lsb>3</lsb>
              <msb>3</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>i2c_timeout_int_enable</name>
              <description>I2C Timeout interrupt enable.</description>
              <lsb>2</lsb>
              <msb>2</msb>
              <access>read-only</access>
            </field>
            <field>
              <name>i2c_sda_timeout_enable</name>
              <description>I2C SDA Timeout enable.</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>i2c_scl_timeout_enable</name>
              <description>I2C SCL Timeout enable.</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>I2C_1_FF__TMOUT_SR</name>
          <description>I2C Timerout Status Register</description>
          <addressOffset>0x400049DE</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>sda_tmout_status</name>
              <description>SDA Timeout status.</description>
              <lsb>1</lsb>
              <msb>1</msb>
              <access>read-write</access>
            </field>
            <field>
              <name>scl_tmout_status</name>
              <description>SCL Timeout status.</description>
              <lsb>0</lsb>
              <msb>0</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>I2C_1_FF__TMOUT_CFG0</name>
          <description>I2C Timerout Period Configuration Register-0</description>
          <addressOffset>0x400049DF</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>timeout_period_lowbyte</name>
              <description>The configuration of this register along with that in register TMOUT_CFG1 to define the number units before SCL or SDA stuck low timeout triggers the I2C interrupt. The one unit is equal to SYSCLK/1024. The TMOUT_CFG0 defines lower byte of the period.</description>
              <lsb>0</lsb>
              <msb>7</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
        <register>
          <name>I2C_1_FF__TMOUT_CFG1</name>
          <description>Extended Configuration Register: TMOUT_CFG1</description>
          <addressOffset>0x400049E0</addressOffset>
          <size>8</size>
          <access>read-write</access>
          <resetValue>0</resetValue>
          <resetMask>0</resetMask>
          <fields>
            <field>
              <name>timeout_period_highnibble</name>
              <description>The configuration of this register along with that in register TMOUT_CFG1 to define the number units before SCL or SDA stuck low timeout triggers the I2C interrupt. The one unit is equal to SYSCLK/1024. The TMOUT_CFG1 defines higher octet of the period.</description>
              <lsb>0</lsb>
              <msb>3</msb>
              <access>read-write</access>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>
  </peripherals>
</device>