ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 1


   1              	/***************************************************************************//**
   2              	* \file CyBootAsmGnu.s
   3              	* \version 6.10
   4              	*
   5              	*  \brief
   6              	*   Assembly routines for GNU as.
   7              	*
   8              	********************************************************************************
   9              	* \copyright
  10              	* Copyright 2010-2021, Cypress Semiconductor Corporation.  All rights reserved.
  11              	* You may use this file only in accordance with the license, terms, conditions,
  12              	* disclaimers, and limitations in the end user license agreement accompanying
  13              	* the software package with which this file was provided.
  14              	*******************************************************************************/
  15              	
  16              	.include "cyfittergnu.inc"
   1              	/*******************************************************************************
   2              	* File Name: cyfittergnu.inc
   3              	* 
   4              	* PSoC Creator  4.3
   5              	*
   6              	* Description:
   7              	* 
   8              	* This file is automatically generated by PSoC Creator.
   9              	*
  10              	********************************************************************************
  11              	* Copyright (c) 2007-2019 Cypress Semiconductor.  All rights reserved.
  12              	* You may use this file only in accordance with the license, terms, conditions, 
  13              	* disclaimers, and limitations in the end user license agreement accompanying 
  14              	* the software package with which this file was provided.
  15              	********************************************************************************/
  16              	
  17              	.ifndef INCLUDED_CYFITTERGNU_INC
  18              	.set INCLUDED_CYFITTERGNU_INC, 1
  19              	.include "cydevicegnu.inc"
   1              	/*******************************************************************************
   2              	* File Name: cydevicegnu.inc
   3              	* OBSOLETE: Do not use this file. Use the _trm version instead.
   4              	* PSoC Creator  4.3
   5              	*
   6              	* Description:
   7              	* This file provides all of the address values for the entire PSoC device.
   8              	* This file is automatically generated by PSoC Creator.
   9              	*
  10              	********************************************************************************
  11              	* Copyright (c) 2007-2019 Cypress Semiconductor.  All rights reserved.
  12              	* You may use this file only in accordance with the license, terms, conditions, 
  13              	* disclaimers, and limitations in the end user license agreement accompanying 
  14              	* the software package with which this file was provided.
  15              	********************************************************************************/
  16              	
  17              	.set CYDEV_FLASH_BASE, 0x00000000
  18              	.set CYDEV_FLASH_SIZE, 0x00040000
  19              	.set CYDEV_FLASH_DATA_MBASE, 0x00000000
  20              	.set CYDEV_FLASH_DATA_MSIZE, 0x00040000
  21              	.set CYDEV_SRAM_BASE, 0x1fff8000
  22              	.set CYDEV_SRAM_SIZE, 0x00010000
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 2


  23              	.set CYDEV_SRAM_CODE64K_MBASE, 0x1fff8000
  24              	.set CYDEV_SRAM_CODE64K_MSIZE, 0x00004000
  25              	.set CYDEV_SRAM_CODE32K_MBASE, 0x1fffc000
  26              	.set CYDEV_SRAM_CODE32K_MSIZE, 0x00002000
  27              	.set CYDEV_SRAM_CODE16K_MBASE, 0x1fffe000
  28              	.set CYDEV_SRAM_CODE16K_MSIZE, 0x00001000
  29              	.set CYDEV_SRAM_CODE_MBASE, 0x1fff8000
  30              	.set CYDEV_SRAM_CODE_MSIZE, 0x00008000
  31              	.set CYDEV_SRAM_DATA_MBASE, 0x20000000
  32              	.set CYDEV_SRAM_DATA_MSIZE, 0x00008000
  33              	.set CYDEV_SRAM_DATA16K_MBASE, 0x20001000
  34              	.set CYDEV_SRAM_DATA16K_MSIZE, 0x00001000
  35              	.set CYDEV_SRAM_DATA32K_MBASE, 0x20002000
  36              	.set CYDEV_SRAM_DATA32K_MSIZE, 0x00002000
  37              	.set CYDEV_SRAM_DATA64K_MBASE, 0x20004000
  38              	.set CYDEV_SRAM_DATA64K_MSIZE, 0x00004000
  39              	.set CYDEV_DMA_BASE, 0x20008000
  40              	.set CYDEV_DMA_SIZE, 0x00008000
  41              	.set CYDEV_DMA_SRAM64K_MBASE, 0x20008000
  42              	.set CYDEV_DMA_SRAM64K_MSIZE, 0x00004000
  43              	.set CYDEV_DMA_SRAM32K_MBASE, 0x2000c000
  44              	.set CYDEV_DMA_SRAM32K_MSIZE, 0x00002000
  45              	.set CYDEV_DMA_SRAM16K_MBASE, 0x2000e000
  46              	.set CYDEV_DMA_SRAM16K_MSIZE, 0x00001000
  47              	.set CYDEV_DMA_SRAM_MBASE, 0x2000f000
  48              	.set CYDEV_DMA_SRAM_MSIZE, 0x00001000
  49              	.set CYDEV_CLKDIST_BASE, 0x40004000
  50              	.set CYDEV_CLKDIST_SIZE, 0x00000110
  51              	.set CYDEV_CLKDIST_CR, 0x40004000
  52              	.set CYDEV_CLKDIST_LD, 0x40004001
  53              	.set CYDEV_CLKDIST_WRK0, 0x40004002
  54              	.set CYDEV_CLKDIST_WRK1, 0x40004003
  55              	.set CYDEV_CLKDIST_MSTR0, 0x40004004
  56              	.set CYDEV_CLKDIST_MSTR1, 0x40004005
  57              	.set CYDEV_CLKDIST_BCFG0, 0x40004006
  58              	.set CYDEV_CLKDIST_BCFG1, 0x40004007
  59              	.set CYDEV_CLKDIST_BCFG2, 0x40004008
  60              	.set CYDEV_CLKDIST_UCFG, 0x40004009
  61              	.set CYDEV_CLKDIST_DLY0, 0x4000400a
  62              	.set CYDEV_CLKDIST_DLY1, 0x4000400b
  63              	.set CYDEV_CLKDIST_DMASK, 0x40004010
  64              	.set CYDEV_CLKDIST_AMASK, 0x40004014
  65              	.set CYDEV_CLKDIST_DCFG0_BASE, 0x40004080
  66              	.set CYDEV_CLKDIST_DCFG0_SIZE, 0x00000003
  67              	.set CYDEV_CLKDIST_DCFG0_CFG0, 0x40004080
  68              	.set CYDEV_CLKDIST_DCFG0_CFG1, 0x40004081
  69              	.set CYDEV_CLKDIST_DCFG0_CFG2, 0x40004082
  70              	.set CYDEV_CLKDIST_DCFG1_BASE, 0x40004084
  71              	.set CYDEV_CLKDIST_DCFG1_SIZE, 0x00000003
  72              	.set CYDEV_CLKDIST_DCFG1_CFG0, 0x40004084
  73              	.set CYDEV_CLKDIST_DCFG1_CFG1, 0x40004085
  74              	.set CYDEV_CLKDIST_DCFG1_CFG2, 0x40004086
  75              	.set CYDEV_CLKDIST_DCFG2_BASE, 0x40004088
  76              	.set CYDEV_CLKDIST_DCFG2_SIZE, 0x00000003
  77              	.set CYDEV_CLKDIST_DCFG2_CFG0, 0x40004088
  78              	.set CYDEV_CLKDIST_DCFG2_CFG1, 0x40004089
  79              	.set CYDEV_CLKDIST_DCFG2_CFG2, 0x4000408a
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 3


  80              	.set CYDEV_CLKDIST_DCFG3_BASE, 0x4000408c
  81              	.set CYDEV_CLKDIST_DCFG3_SIZE, 0x00000003
  82              	.set CYDEV_CLKDIST_DCFG3_CFG0, 0x4000408c
  83              	.set CYDEV_CLKDIST_DCFG3_CFG1, 0x4000408d
  84              	.set CYDEV_CLKDIST_DCFG3_CFG2, 0x4000408e
  85              	.set CYDEV_CLKDIST_DCFG4_BASE, 0x40004090
  86              	.set CYDEV_CLKDIST_DCFG4_SIZE, 0x00000003
  87              	.set CYDEV_CLKDIST_DCFG4_CFG0, 0x40004090
  88              	.set CYDEV_CLKDIST_DCFG4_CFG1, 0x40004091
  89              	.set CYDEV_CLKDIST_DCFG4_CFG2, 0x40004092
  90              	.set CYDEV_CLKDIST_DCFG5_BASE, 0x40004094
  91              	.set CYDEV_CLKDIST_DCFG5_SIZE, 0x00000003
  92              	.set CYDEV_CLKDIST_DCFG5_CFG0, 0x40004094
  93              	.set CYDEV_CLKDIST_DCFG5_CFG1, 0x40004095
  94              	.set CYDEV_CLKDIST_DCFG5_CFG2, 0x40004096
  95              	.set CYDEV_CLKDIST_DCFG6_BASE, 0x40004098
  96              	.set CYDEV_CLKDIST_DCFG6_SIZE, 0x00000003
  97              	.set CYDEV_CLKDIST_DCFG6_CFG0, 0x40004098
  98              	.set CYDEV_CLKDIST_DCFG6_CFG1, 0x40004099
  99              	.set CYDEV_CLKDIST_DCFG6_CFG2, 0x4000409a
 100              	.set CYDEV_CLKDIST_DCFG7_BASE, 0x4000409c
 101              	.set CYDEV_CLKDIST_DCFG7_SIZE, 0x00000003
 102              	.set CYDEV_CLKDIST_DCFG7_CFG0, 0x4000409c
 103              	.set CYDEV_CLKDIST_DCFG7_CFG1, 0x4000409d
 104              	.set CYDEV_CLKDIST_DCFG7_CFG2, 0x4000409e
 105              	.set CYDEV_CLKDIST_ACFG0_BASE, 0x40004100
 106              	.set CYDEV_CLKDIST_ACFG0_SIZE, 0x00000004
 107              	.set CYDEV_CLKDIST_ACFG0_CFG0, 0x40004100
 108              	.set CYDEV_CLKDIST_ACFG0_CFG1, 0x40004101
 109              	.set CYDEV_CLKDIST_ACFG0_CFG2, 0x40004102
 110              	.set CYDEV_CLKDIST_ACFG0_CFG3, 0x40004103
 111              	.set CYDEV_CLKDIST_ACFG1_BASE, 0x40004104
 112              	.set CYDEV_CLKDIST_ACFG1_SIZE, 0x00000004
 113              	.set CYDEV_CLKDIST_ACFG1_CFG0, 0x40004104
 114              	.set CYDEV_CLKDIST_ACFG1_CFG1, 0x40004105
 115              	.set CYDEV_CLKDIST_ACFG1_CFG2, 0x40004106
 116              	.set CYDEV_CLKDIST_ACFG1_CFG3, 0x40004107
 117              	.set CYDEV_CLKDIST_ACFG2_BASE, 0x40004108
 118              	.set CYDEV_CLKDIST_ACFG2_SIZE, 0x00000004
 119              	.set CYDEV_CLKDIST_ACFG2_CFG0, 0x40004108
 120              	.set CYDEV_CLKDIST_ACFG2_CFG1, 0x40004109
 121              	.set CYDEV_CLKDIST_ACFG2_CFG2, 0x4000410a
 122              	.set CYDEV_CLKDIST_ACFG2_CFG3, 0x4000410b
 123              	.set CYDEV_CLKDIST_ACFG3_BASE, 0x4000410c
 124              	.set CYDEV_CLKDIST_ACFG3_SIZE, 0x00000004
 125              	.set CYDEV_CLKDIST_ACFG3_CFG0, 0x4000410c
 126              	.set CYDEV_CLKDIST_ACFG3_CFG1, 0x4000410d
 127              	.set CYDEV_CLKDIST_ACFG3_CFG2, 0x4000410e
 128              	.set CYDEV_CLKDIST_ACFG3_CFG3, 0x4000410f
 129              	.set CYDEV_FASTCLK_BASE, 0x40004200
 130              	.set CYDEV_FASTCLK_SIZE, 0x00000026
 131              	.set CYDEV_FASTCLK_IMO_BASE, 0x40004200
 132              	.set CYDEV_FASTCLK_IMO_SIZE, 0x00000001
 133              	.set CYDEV_FASTCLK_IMO_CR, 0x40004200
 134              	.set CYDEV_FASTCLK_XMHZ_BASE, 0x40004210
 135              	.set CYDEV_FASTCLK_XMHZ_SIZE, 0x00000004
 136              	.set CYDEV_FASTCLK_XMHZ_CSR, 0x40004210
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 4


 137              	.set CYDEV_FASTCLK_XMHZ_CFG0, 0x40004212
 138              	.set CYDEV_FASTCLK_XMHZ_CFG1, 0x40004213
 139              	.set CYDEV_FASTCLK_PLL_BASE, 0x40004220
 140              	.set CYDEV_FASTCLK_PLL_SIZE, 0x00000006
 141              	.set CYDEV_FASTCLK_PLL_CFG0, 0x40004220
 142              	.set CYDEV_FASTCLK_PLL_CFG1, 0x40004221
 143              	.set CYDEV_FASTCLK_PLL_P, 0x40004222
 144              	.set CYDEV_FASTCLK_PLL_Q, 0x40004223
 145              	.set CYDEV_FASTCLK_PLL_SR, 0x40004225
 146              	.set CYDEV_SLOWCLK_BASE, 0x40004300
 147              	.set CYDEV_SLOWCLK_SIZE, 0x0000000b
 148              	.set CYDEV_SLOWCLK_ILO_BASE, 0x40004300
 149              	.set CYDEV_SLOWCLK_ILO_SIZE, 0x00000002
 150              	.set CYDEV_SLOWCLK_ILO_CR0, 0x40004300
 151              	.set CYDEV_SLOWCLK_ILO_CR1, 0x40004301
 152              	.set CYDEV_SLOWCLK_X32_BASE, 0x40004308
 153              	.set CYDEV_SLOWCLK_X32_SIZE, 0x00000003
 154              	.set CYDEV_SLOWCLK_X32_CR, 0x40004308
 155              	.set CYDEV_SLOWCLK_X32_CFG, 0x40004309
 156              	.set CYDEV_SLOWCLK_X32_TST, 0x4000430a
 157              	.set CYDEV_BOOST_BASE, 0x40004320
 158              	.set CYDEV_BOOST_SIZE, 0x00000007
 159              	.set CYDEV_BOOST_CR0, 0x40004320
 160              	.set CYDEV_BOOST_CR1, 0x40004321
 161              	.set CYDEV_BOOST_CR2, 0x40004322
 162              	.set CYDEV_BOOST_CR3, 0x40004323
 163              	.set CYDEV_BOOST_SR, 0x40004324
 164              	.set CYDEV_BOOST_CR4, 0x40004325
 165              	.set CYDEV_BOOST_SR2, 0x40004326
 166              	.set CYDEV_PWRSYS_BASE, 0x40004330
 167              	.set CYDEV_PWRSYS_SIZE, 0x00000002
 168              	.set CYDEV_PWRSYS_CR0, 0x40004330
 169              	.set CYDEV_PWRSYS_CR1, 0x40004331
 170              	.set CYDEV_PM_BASE, 0x40004380
 171              	.set CYDEV_PM_SIZE, 0x00000057
 172              	.set CYDEV_PM_TW_CFG0, 0x40004380
 173              	.set CYDEV_PM_TW_CFG1, 0x40004381
 174              	.set CYDEV_PM_TW_CFG2, 0x40004382
 175              	.set CYDEV_PM_WDT_CFG, 0x40004383
 176              	.set CYDEV_PM_WDT_CR, 0x40004384
 177              	.set CYDEV_PM_INT_SR, 0x40004390
 178              	.set CYDEV_PM_MODE_CFG0, 0x40004391
 179              	.set CYDEV_PM_MODE_CFG1, 0x40004392
 180              	.set CYDEV_PM_MODE_CSR, 0x40004393
 181              	.set CYDEV_PM_USB_CR0, 0x40004394
 182              	.set CYDEV_PM_WAKEUP_CFG0, 0x40004398
 183              	.set CYDEV_PM_WAKEUP_CFG1, 0x40004399
 184              	.set CYDEV_PM_WAKEUP_CFG2, 0x4000439a
 185              	.set CYDEV_PM_ACT_BASE, 0x400043a0
 186              	.set CYDEV_PM_ACT_SIZE, 0x0000000e
 187              	.set CYDEV_PM_ACT_CFG0, 0x400043a0
 188              	.set CYDEV_PM_ACT_CFG1, 0x400043a1
 189              	.set CYDEV_PM_ACT_CFG2, 0x400043a2
 190              	.set CYDEV_PM_ACT_CFG3, 0x400043a3
 191              	.set CYDEV_PM_ACT_CFG4, 0x400043a4
 192              	.set CYDEV_PM_ACT_CFG5, 0x400043a5
 193              	.set CYDEV_PM_ACT_CFG6, 0x400043a6
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 5


 194              	.set CYDEV_PM_ACT_CFG7, 0x400043a7
 195              	.set CYDEV_PM_ACT_CFG8, 0x400043a8
 196              	.set CYDEV_PM_ACT_CFG9, 0x400043a9
 197              	.set CYDEV_PM_ACT_CFG10, 0x400043aa
 198              	.set CYDEV_PM_ACT_CFG11, 0x400043ab
 199              	.set CYDEV_PM_ACT_CFG12, 0x400043ac
 200              	.set CYDEV_PM_ACT_CFG13, 0x400043ad
 201              	.set CYDEV_PM_STBY_BASE, 0x400043b0
 202              	.set CYDEV_PM_STBY_SIZE, 0x0000000e
 203              	.set CYDEV_PM_STBY_CFG0, 0x400043b0
 204              	.set CYDEV_PM_STBY_CFG1, 0x400043b1
 205              	.set CYDEV_PM_STBY_CFG2, 0x400043b2
 206              	.set CYDEV_PM_STBY_CFG3, 0x400043b3
 207              	.set CYDEV_PM_STBY_CFG4, 0x400043b4
 208              	.set CYDEV_PM_STBY_CFG5, 0x400043b5
 209              	.set CYDEV_PM_STBY_CFG6, 0x400043b6
 210              	.set CYDEV_PM_STBY_CFG7, 0x400043b7
 211              	.set CYDEV_PM_STBY_CFG8, 0x400043b8
 212              	.set CYDEV_PM_STBY_CFG9, 0x400043b9
 213              	.set CYDEV_PM_STBY_CFG10, 0x400043ba
 214              	.set CYDEV_PM_STBY_CFG11, 0x400043bb
 215              	.set CYDEV_PM_STBY_CFG12, 0x400043bc
 216              	.set CYDEV_PM_STBY_CFG13, 0x400043bd
 217              	.set CYDEV_PM_AVAIL_BASE, 0x400043c0
 218              	.set CYDEV_PM_AVAIL_SIZE, 0x00000017
 219              	.set CYDEV_PM_AVAIL_CR0, 0x400043c0
 220              	.set CYDEV_PM_AVAIL_CR1, 0x400043c1
 221              	.set CYDEV_PM_AVAIL_CR2, 0x400043c2
 222              	.set CYDEV_PM_AVAIL_CR3, 0x400043c3
 223              	.set CYDEV_PM_AVAIL_CR4, 0x400043c4
 224              	.set CYDEV_PM_AVAIL_CR5, 0x400043c5
 225              	.set CYDEV_PM_AVAIL_CR6, 0x400043c6
 226              	.set CYDEV_PM_AVAIL_SR0, 0x400043d0
 227              	.set CYDEV_PM_AVAIL_SR1, 0x400043d1
 228              	.set CYDEV_PM_AVAIL_SR2, 0x400043d2
 229              	.set CYDEV_PM_AVAIL_SR3, 0x400043d3
 230              	.set CYDEV_PM_AVAIL_SR4, 0x400043d4
 231              	.set CYDEV_PM_AVAIL_SR5, 0x400043d5
 232              	.set CYDEV_PM_AVAIL_SR6, 0x400043d6
 233              	.set CYDEV_PICU_BASE, 0x40004500
 234              	.set CYDEV_PICU_SIZE, 0x000000b0
 235              	.set CYDEV_PICU_INTTYPE_BASE, 0x40004500
 236              	.set CYDEV_PICU_INTTYPE_SIZE, 0x00000080
 237              	.set CYDEV_PICU_INTTYPE_PICU0_BASE, 0x40004500
 238              	.set CYDEV_PICU_INTTYPE_PICU0_SIZE, 0x00000008
 239              	.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE0, 0x40004500
 240              	.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE1, 0x40004501
 241              	.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE2, 0x40004502
 242              	.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE3, 0x40004503
 243              	.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE4, 0x40004504
 244              	.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE5, 0x40004505
 245              	.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE6, 0x40004506
 246              	.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE7, 0x40004507
 247              	.set CYDEV_PICU_INTTYPE_PICU1_BASE, 0x40004508
 248              	.set CYDEV_PICU_INTTYPE_PICU1_SIZE, 0x00000008
 249              	.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE0, 0x40004508
 250              	.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE1, 0x40004509
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 6


 251              	.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE2, 0x4000450a
 252              	.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE3, 0x4000450b
 253              	.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE4, 0x4000450c
 254              	.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE5, 0x4000450d
 255              	.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE6, 0x4000450e
 256              	.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE7, 0x4000450f
 257              	.set CYDEV_PICU_INTTYPE_PICU2_BASE, 0x40004510
 258              	.set CYDEV_PICU_INTTYPE_PICU2_SIZE, 0x00000008
 259              	.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE0, 0x40004510
 260              	.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE1, 0x40004511
 261              	.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE2, 0x40004512
 262              	.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE3, 0x40004513
 263              	.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE4, 0x40004514
 264              	.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE5, 0x40004515
 265              	.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE6, 0x40004516
 266              	.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE7, 0x40004517
 267              	.set CYDEV_PICU_INTTYPE_PICU3_BASE, 0x40004518
 268              	.set CYDEV_PICU_INTTYPE_PICU3_SIZE, 0x00000008
 269              	.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE0, 0x40004518
 270              	.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE1, 0x40004519
 271              	.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE2, 0x4000451a
 272              	.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE3, 0x4000451b
 273              	.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE4, 0x4000451c
 274              	.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE5, 0x4000451d
 275              	.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE6, 0x4000451e
 276              	.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE7, 0x4000451f
 277              	.set CYDEV_PICU_INTTYPE_PICU4_BASE, 0x40004520
 278              	.set CYDEV_PICU_INTTYPE_PICU4_SIZE, 0x00000008
 279              	.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE0, 0x40004520
 280              	.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE1, 0x40004521
 281              	.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE2, 0x40004522
 282              	.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE3, 0x40004523
 283              	.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE4, 0x40004524
 284              	.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE5, 0x40004525
 285              	.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE6, 0x40004526
 286              	.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE7, 0x40004527
 287              	.set CYDEV_PICU_INTTYPE_PICU5_BASE, 0x40004528
 288              	.set CYDEV_PICU_INTTYPE_PICU5_SIZE, 0x00000008
 289              	.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE0, 0x40004528
 290              	.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE1, 0x40004529
 291              	.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE2, 0x4000452a
 292              	.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE3, 0x4000452b
 293              	.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE4, 0x4000452c
 294              	.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE5, 0x4000452d
 295              	.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE6, 0x4000452e
 296              	.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE7, 0x4000452f
 297              	.set CYDEV_PICU_INTTYPE_PICU6_BASE, 0x40004530
 298              	.set CYDEV_PICU_INTTYPE_PICU6_SIZE, 0x00000008
 299              	.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE0, 0x40004530
 300              	.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE1, 0x40004531
 301              	.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE2, 0x40004532
 302              	.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE3, 0x40004533
 303              	.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE4, 0x40004534
 304              	.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE5, 0x40004535
 305              	.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE6, 0x40004536
 306              	.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE7, 0x40004537
 307              	.set CYDEV_PICU_INTTYPE_PICU12_BASE, 0x40004560
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 7


 308              	.set CYDEV_PICU_INTTYPE_PICU12_SIZE, 0x00000008
 309              	.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE0, 0x40004560
 310              	.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE1, 0x40004561
 311              	.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE2, 0x40004562
 312              	.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE3, 0x40004563
 313              	.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE4, 0x40004564
 314              	.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE5, 0x40004565
 315              	.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE6, 0x40004566
 316              	.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE7, 0x40004567
 317              	.set CYDEV_PICU_INTTYPE_PICU15_BASE, 0x40004578
 318              	.set CYDEV_PICU_INTTYPE_PICU15_SIZE, 0x00000008
 319              	.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE0, 0x40004578
 320              	.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE1, 0x40004579
 321              	.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE2, 0x4000457a
 322              	.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE3, 0x4000457b
 323              	.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE4, 0x4000457c
 324              	.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE5, 0x4000457d
 325              	.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE6, 0x4000457e
 326              	.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE7, 0x4000457f
 327              	.set CYDEV_PICU_STAT_BASE, 0x40004580
 328              	.set CYDEV_PICU_STAT_SIZE, 0x00000010
 329              	.set CYDEV_PICU_STAT_PICU0_BASE, 0x40004580
 330              	.set CYDEV_PICU_STAT_PICU0_SIZE, 0x00000001
 331              	.set CYDEV_PICU_STAT_PICU0_INTSTAT, 0x40004580
 332              	.set CYDEV_PICU_STAT_PICU1_BASE, 0x40004581
 333              	.set CYDEV_PICU_STAT_PICU1_SIZE, 0x00000001
 334              	.set CYDEV_PICU_STAT_PICU1_INTSTAT, 0x40004581
 335              	.set CYDEV_PICU_STAT_PICU2_BASE, 0x40004582
 336              	.set CYDEV_PICU_STAT_PICU2_SIZE, 0x00000001
 337              	.set CYDEV_PICU_STAT_PICU2_INTSTAT, 0x40004582
 338              	.set CYDEV_PICU_STAT_PICU3_BASE, 0x40004583
 339              	.set CYDEV_PICU_STAT_PICU3_SIZE, 0x00000001
 340              	.set CYDEV_PICU_STAT_PICU3_INTSTAT, 0x40004583
 341              	.set CYDEV_PICU_STAT_PICU4_BASE, 0x40004584
 342              	.set CYDEV_PICU_STAT_PICU4_SIZE, 0x00000001
 343              	.set CYDEV_PICU_STAT_PICU4_INTSTAT, 0x40004584
 344              	.set CYDEV_PICU_STAT_PICU5_BASE, 0x40004585
 345              	.set CYDEV_PICU_STAT_PICU5_SIZE, 0x00000001
 346              	.set CYDEV_PICU_STAT_PICU5_INTSTAT, 0x40004585
 347              	.set CYDEV_PICU_STAT_PICU6_BASE, 0x40004586
 348              	.set CYDEV_PICU_STAT_PICU6_SIZE, 0x00000001
 349              	.set CYDEV_PICU_STAT_PICU6_INTSTAT, 0x40004586
 350              	.set CYDEV_PICU_STAT_PICU12_BASE, 0x4000458c
 351              	.set CYDEV_PICU_STAT_PICU12_SIZE, 0x00000001
 352              	.set CYDEV_PICU_STAT_PICU12_INTSTAT, 0x4000458c
 353              	.set CYDEV_PICU_STAT_PICU15_BASE, 0x4000458f
 354              	.set CYDEV_PICU_STAT_PICU15_SIZE, 0x00000001
 355              	.set CYDEV_PICU_STAT_PICU15_INTSTAT, 0x4000458f
 356              	.set CYDEV_PICU_SNAP_BASE, 0x40004590
 357              	.set CYDEV_PICU_SNAP_SIZE, 0x00000010
 358              	.set CYDEV_PICU_SNAP_PICU0_BASE, 0x40004590
 359              	.set CYDEV_PICU_SNAP_PICU0_SIZE, 0x00000001
 360              	.set CYDEV_PICU_SNAP_PICU0_SNAP, 0x40004590
 361              	.set CYDEV_PICU_SNAP_PICU1_BASE, 0x40004591
 362              	.set CYDEV_PICU_SNAP_PICU1_SIZE, 0x00000001
 363              	.set CYDEV_PICU_SNAP_PICU1_SNAP, 0x40004591
 364              	.set CYDEV_PICU_SNAP_PICU2_BASE, 0x40004592
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 8


 365              	.set CYDEV_PICU_SNAP_PICU2_SIZE, 0x00000001
 366              	.set CYDEV_PICU_SNAP_PICU2_SNAP, 0x40004592
 367              	.set CYDEV_PICU_SNAP_PICU3_BASE, 0x40004593
 368              	.set CYDEV_PICU_SNAP_PICU3_SIZE, 0x00000001
 369              	.set CYDEV_PICU_SNAP_PICU3_SNAP, 0x40004593
 370              	.set CYDEV_PICU_SNAP_PICU4_BASE, 0x40004594
 371              	.set CYDEV_PICU_SNAP_PICU4_SIZE, 0x00000001
 372              	.set CYDEV_PICU_SNAP_PICU4_SNAP, 0x40004594
 373              	.set CYDEV_PICU_SNAP_PICU5_BASE, 0x40004595
 374              	.set CYDEV_PICU_SNAP_PICU5_SIZE, 0x00000001
 375              	.set CYDEV_PICU_SNAP_PICU5_SNAP, 0x40004595
 376              	.set CYDEV_PICU_SNAP_PICU6_BASE, 0x40004596
 377              	.set CYDEV_PICU_SNAP_PICU6_SIZE, 0x00000001
 378              	.set CYDEV_PICU_SNAP_PICU6_SNAP, 0x40004596
 379              	.set CYDEV_PICU_SNAP_PICU12_BASE, 0x4000459c
 380              	.set CYDEV_PICU_SNAP_PICU12_SIZE, 0x00000001
 381              	.set CYDEV_PICU_SNAP_PICU12_SNAP, 0x4000459c
 382              	.set CYDEV_PICU_SNAP_PICU_15_BASE, 0x4000459f
 383              	.set CYDEV_PICU_SNAP_PICU_15_SIZE, 0x00000001
 384              	.set CYDEV_PICU_SNAP_PICU_15_SNAP_15, 0x4000459f
 385              	.set CYDEV_PICU_DISABLE_COR_BASE, 0x400045a0
 386              	.set CYDEV_PICU_DISABLE_COR_SIZE, 0x00000010
 387              	.set CYDEV_PICU_DISABLE_COR_PICU0_BASE, 0x400045a0
 388              	.set CYDEV_PICU_DISABLE_COR_PICU0_SIZE, 0x00000001
 389              	.set CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR, 0x400045a0
 390              	.set CYDEV_PICU_DISABLE_COR_PICU1_BASE, 0x400045a1
 391              	.set CYDEV_PICU_DISABLE_COR_PICU1_SIZE, 0x00000001
 392              	.set CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR, 0x400045a1
 393              	.set CYDEV_PICU_DISABLE_COR_PICU2_BASE, 0x400045a2
 394              	.set CYDEV_PICU_DISABLE_COR_PICU2_SIZE, 0x00000001
 395              	.set CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR, 0x400045a2
 396              	.set CYDEV_PICU_DISABLE_COR_PICU3_BASE, 0x400045a3
 397              	.set CYDEV_PICU_DISABLE_COR_PICU3_SIZE, 0x00000001
 398              	.set CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR, 0x400045a3
 399              	.set CYDEV_PICU_DISABLE_COR_PICU4_BASE, 0x400045a4
 400              	.set CYDEV_PICU_DISABLE_COR_PICU4_SIZE, 0x00000001
 401              	.set CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR, 0x400045a4
 402              	.set CYDEV_PICU_DISABLE_COR_PICU5_BASE, 0x400045a5
 403              	.set CYDEV_PICU_DISABLE_COR_PICU5_SIZE, 0x00000001
 404              	.set CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR, 0x400045a5
 405              	.set CYDEV_PICU_DISABLE_COR_PICU6_BASE, 0x400045a6
 406              	.set CYDEV_PICU_DISABLE_COR_PICU6_SIZE, 0x00000001
 407              	.set CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR, 0x400045a6
 408              	.set CYDEV_PICU_DISABLE_COR_PICU12_BASE, 0x400045ac
 409              	.set CYDEV_PICU_DISABLE_COR_PICU12_SIZE, 0x00000001
 410              	.set CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR, 0x400045ac
 411              	.set CYDEV_PICU_DISABLE_COR_PICU15_BASE, 0x400045af
 412              	.set CYDEV_PICU_DISABLE_COR_PICU15_SIZE, 0x00000001
 413              	.set CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR, 0x400045af
 414              	.set CYDEV_MFGCFG_BASE, 0x40004600
 415              	.set CYDEV_MFGCFG_SIZE, 0x000000ed
 416              	.set CYDEV_MFGCFG_ANAIF_BASE, 0x40004600
 417              	.set CYDEV_MFGCFG_ANAIF_SIZE, 0x00000038
 418              	.set CYDEV_MFGCFG_ANAIF_DAC0_BASE, 0x40004608
 419              	.set CYDEV_MFGCFG_ANAIF_DAC0_SIZE, 0x00000001
 420              	.set CYDEV_MFGCFG_ANAIF_DAC0_TR, 0x40004608
 421              	.set CYDEV_MFGCFG_ANAIF_DAC1_BASE, 0x40004609
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 9


 422              	.set CYDEV_MFGCFG_ANAIF_DAC1_SIZE, 0x00000001
 423              	.set CYDEV_MFGCFG_ANAIF_DAC1_TR, 0x40004609
 424              	.set CYDEV_MFGCFG_ANAIF_DAC2_BASE, 0x4000460a
 425              	.set CYDEV_MFGCFG_ANAIF_DAC2_SIZE, 0x00000001
 426              	.set CYDEV_MFGCFG_ANAIF_DAC2_TR, 0x4000460a
 427              	.set CYDEV_MFGCFG_ANAIF_DAC3_BASE, 0x4000460b
 428              	.set CYDEV_MFGCFG_ANAIF_DAC3_SIZE, 0x00000001
 429              	.set CYDEV_MFGCFG_ANAIF_DAC3_TR, 0x4000460b
 430              	.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE, 0x40004610
 431              	.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE, 0x00000001
 432              	.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0, 0x40004610
 433              	.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE, 0x40004611
 434              	.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE, 0x00000001
 435              	.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0, 0x40004611
 436              	.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE, 0x40004612
 437              	.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE, 0x00000001
 438              	.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0, 0x40004612
 439              	.set CYDEV_MFGCFG_ANAIF_SAR0_BASE, 0x40004614
 440              	.set CYDEV_MFGCFG_ANAIF_SAR0_SIZE, 0x00000001
 441              	.set CYDEV_MFGCFG_ANAIF_SAR0_TR0, 0x40004614
 442              	.set CYDEV_MFGCFG_ANAIF_SAR1_BASE, 0x40004616
 443              	.set CYDEV_MFGCFG_ANAIF_SAR1_SIZE, 0x00000001
 444              	.set CYDEV_MFGCFG_ANAIF_SAR1_TR0, 0x40004616
 445              	.set CYDEV_MFGCFG_ANAIF_OPAMP0_BASE, 0x40004620
 446              	.set CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE, 0x00000002
 447              	.set CYDEV_MFGCFG_ANAIF_OPAMP0_TR0, 0x40004620
 448              	.set CYDEV_MFGCFG_ANAIF_OPAMP0_TR1, 0x40004621
 449              	.set CYDEV_MFGCFG_ANAIF_OPAMP1_BASE, 0x40004622
 450              	.set CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE, 0x00000002
 451              	.set CYDEV_MFGCFG_ANAIF_OPAMP1_TR0, 0x40004622
 452              	.set CYDEV_MFGCFG_ANAIF_OPAMP1_TR1, 0x40004623
 453              	.set CYDEV_MFGCFG_ANAIF_OPAMP2_BASE, 0x40004624
 454              	.set CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE, 0x00000002
 455              	.set CYDEV_MFGCFG_ANAIF_OPAMP2_TR0, 0x40004624
 456              	.set CYDEV_MFGCFG_ANAIF_OPAMP2_TR1, 0x40004625
 457              	.set CYDEV_MFGCFG_ANAIF_OPAMP3_BASE, 0x40004626
 458              	.set CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE, 0x00000002
 459              	.set CYDEV_MFGCFG_ANAIF_OPAMP3_TR0, 0x40004626
 460              	.set CYDEV_MFGCFG_ANAIF_OPAMP3_TR1, 0x40004627
 461              	.set CYDEV_MFGCFG_ANAIF_CMP0_BASE, 0x40004630
 462              	.set CYDEV_MFGCFG_ANAIF_CMP0_SIZE, 0x00000002
 463              	.set CYDEV_MFGCFG_ANAIF_CMP0_TR0, 0x40004630
 464              	.set CYDEV_MFGCFG_ANAIF_CMP0_TR1, 0x40004631
 465              	.set CYDEV_MFGCFG_ANAIF_CMP1_BASE, 0x40004632
 466              	.set CYDEV_MFGCFG_ANAIF_CMP1_SIZE, 0x00000002
 467              	.set CYDEV_MFGCFG_ANAIF_CMP1_TR0, 0x40004632
 468              	.set CYDEV_MFGCFG_ANAIF_CMP1_TR1, 0x40004633
 469              	.set CYDEV_MFGCFG_ANAIF_CMP2_BASE, 0x40004634
 470              	.set CYDEV_MFGCFG_ANAIF_CMP2_SIZE, 0x00000002
 471              	.set CYDEV_MFGCFG_ANAIF_CMP2_TR0, 0x40004634
 472              	.set CYDEV_MFGCFG_ANAIF_CMP2_TR1, 0x40004635
 473              	.set CYDEV_MFGCFG_ANAIF_CMP3_BASE, 0x40004636
 474              	.set CYDEV_MFGCFG_ANAIF_CMP3_SIZE, 0x00000002
 475              	.set CYDEV_MFGCFG_ANAIF_CMP3_TR0, 0x40004636
 476              	.set CYDEV_MFGCFG_ANAIF_CMP3_TR1, 0x40004637
 477              	.set CYDEV_MFGCFG_PWRSYS_BASE, 0x40004680
 478              	.set CYDEV_MFGCFG_PWRSYS_SIZE, 0x0000000b
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 10


 479              	.set CYDEV_MFGCFG_PWRSYS_HIB_TR0, 0x40004680
 480              	.set CYDEV_MFGCFG_PWRSYS_HIB_TR1, 0x40004681
 481              	.set CYDEV_MFGCFG_PWRSYS_I2C_TR, 0x40004682
 482              	.set CYDEV_MFGCFG_PWRSYS_SLP_TR, 0x40004683
 483              	.set CYDEV_MFGCFG_PWRSYS_BUZZ_TR, 0x40004684
 484              	.set CYDEV_MFGCFG_PWRSYS_WAKE_TR0, 0x40004685
 485              	.set CYDEV_MFGCFG_PWRSYS_WAKE_TR1, 0x40004686
 486              	.set CYDEV_MFGCFG_PWRSYS_BREF_TR, 0x40004687
 487              	.set CYDEV_MFGCFG_PWRSYS_BG_TR, 0x40004688
 488              	.set CYDEV_MFGCFG_PWRSYS_WAKE_TR2, 0x40004689
 489              	.set CYDEV_MFGCFG_PWRSYS_WAKE_TR3, 0x4000468a
 490              	.set CYDEV_MFGCFG_ILO_BASE, 0x40004690
 491              	.set CYDEV_MFGCFG_ILO_SIZE, 0x00000002
 492              	.set CYDEV_MFGCFG_ILO_TR0, 0x40004690
 493              	.set CYDEV_MFGCFG_ILO_TR1, 0x40004691
 494              	.set CYDEV_MFGCFG_X32_BASE, 0x40004698
 495              	.set CYDEV_MFGCFG_X32_SIZE, 0x00000001
 496              	.set CYDEV_MFGCFG_X32_TR, 0x40004698
 497              	.set CYDEV_MFGCFG_IMO_BASE, 0x400046a0
 498              	.set CYDEV_MFGCFG_IMO_SIZE, 0x00000005
 499              	.set CYDEV_MFGCFG_IMO_TR0, 0x400046a0
 500              	.set CYDEV_MFGCFG_IMO_TR1, 0x400046a1
 501              	.set CYDEV_MFGCFG_IMO_GAIN, 0x400046a2
 502              	.set CYDEV_MFGCFG_IMO_C36M, 0x400046a3
 503              	.set CYDEV_MFGCFG_IMO_TR2, 0x400046a4
 504              	.set CYDEV_MFGCFG_XMHZ_BASE, 0x400046a8
 505              	.set CYDEV_MFGCFG_XMHZ_SIZE, 0x00000001
 506              	.set CYDEV_MFGCFG_XMHZ_TR, 0x400046a8
 507              	.set CYDEV_MFGCFG_DLY, 0x400046c0
 508              	.set CYDEV_MFGCFG_MLOGIC_BASE, 0x400046e0
 509              	.set CYDEV_MFGCFG_MLOGIC_SIZE, 0x0000000d
 510              	.set CYDEV_MFGCFG_MLOGIC_DMPSTR, 0x400046e2
 511              	.set CYDEV_MFGCFG_MLOGIC_SEG_BASE, 0x400046e4
 512              	.set CYDEV_MFGCFG_MLOGIC_SEG_SIZE, 0x00000002
 513              	.set CYDEV_MFGCFG_MLOGIC_SEG_CR, 0x400046e4
 514              	.set CYDEV_MFGCFG_MLOGIC_SEG_CFG0, 0x400046e5
 515              	.set CYDEV_MFGCFG_MLOGIC_DEBUG, 0x400046e8
 516              	.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE, 0x400046ea
 517              	.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE, 0x00000001
 518              	.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR, 0x400046ea
 519              	.set CYDEV_MFGCFG_MLOGIC_REV_ID, 0x400046ec
 520              	.set CYDEV_RESET_BASE, 0x400046f0
 521              	.set CYDEV_RESET_SIZE, 0x0000000f
 522              	.set CYDEV_RESET_IPOR_CR0, 0x400046f0
 523              	.set CYDEV_RESET_IPOR_CR1, 0x400046f1
 524              	.set CYDEV_RESET_IPOR_CR2, 0x400046f2
 525              	.set CYDEV_RESET_IPOR_CR3, 0x400046f3
 526              	.set CYDEV_RESET_CR0, 0x400046f4
 527              	.set CYDEV_RESET_CR1, 0x400046f5
 528              	.set CYDEV_RESET_CR2, 0x400046f6
 529              	.set CYDEV_RESET_CR3, 0x400046f7
 530              	.set CYDEV_RESET_CR4, 0x400046f8
 531              	.set CYDEV_RESET_CR5, 0x400046f9
 532              	.set CYDEV_RESET_SR0, 0x400046fa
 533              	.set CYDEV_RESET_SR1, 0x400046fb
 534              	.set CYDEV_RESET_SR2, 0x400046fc
 535              	.set CYDEV_RESET_SR3, 0x400046fd
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 11


 536              	.set CYDEV_RESET_TR, 0x400046fe
 537              	.set CYDEV_SPC_BASE, 0x40004700
 538              	.set CYDEV_SPC_SIZE, 0x00000100
 539              	.set CYDEV_SPC_FM_EE_CR, 0x40004700
 540              	.set CYDEV_SPC_FM_EE_WAKE_CNT, 0x40004701
 541              	.set CYDEV_SPC_EE_SCR, 0x40004702
 542              	.set CYDEV_SPC_EE_ERR, 0x40004703
 543              	.set CYDEV_SPC_CPU_DATA, 0x40004720
 544              	.set CYDEV_SPC_DMA_DATA, 0x40004721
 545              	.set CYDEV_SPC_SR, 0x40004722
 546              	.set CYDEV_SPC_CR, 0x40004723
 547              	.set CYDEV_SPC_DMM_MAP_BASE, 0x40004780
 548              	.set CYDEV_SPC_DMM_MAP_SIZE, 0x00000080
 549              	.set CYDEV_SPC_DMM_MAP_SRAM_MBASE, 0x40004780
 550              	.set CYDEV_SPC_DMM_MAP_SRAM_MSIZE, 0x00000080
 551              	.set CYDEV_CACHE_BASE, 0x40004800
 552              	.set CYDEV_CACHE_SIZE, 0x0000009c
 553              	.set CYDEV_CACHE_CC_CTL, 0x40004800
 554              	.set CYDEV_CACHE_ECC_CORR, 0x40004880
 555              	.set CYDEV_CACHE_ECC_ERR, 0x40004888
 556              	.set CYDEV_CACHE_FLASH_ERR, 0x40004890
 557              	.set CYDEV_CACHE_HITMISS, 0x40004898
 558              	.set CYDEV_I2C_BASE, 0x40004900
 559              	.set CYDEV_I2C_SIZE, 0x000000e1
 560              	.set CYDEV_I2C_XCFG, 0x400049c8
 561              	.set CYDEV_I2C_ADR, 0x400049ca
 562              	.set CYDEV_I2C_CFG, 0x400049d6
 563              	.set CYDEV_I2C_CSR, 0x400049d7
 564              	.set CYDEV_I2C_D, 0x400049d8
 565              	.set CYDEV_I2C_MCSR, 0x400049d9
 566              	.set CYDEV_I2C_CLK_DIV1, 0x400049db
 567              	.set CYDEV_I2C_CLK_DIV2, 0x400049dc
 568              	.set CYDEV_I2C_TMOUT_CSR, 0x400049dd
 569              	.set CYDEV_I2C_TMOUT_SR, 0x400049de
 570              	.set CYDEV_I2C_TMOUT_CFG0, 0x400049df
 571              	.set CYDEV_I2C_TMOUT_CFG1, 0x400049e0
 572              	.set CYDEV_DEC_BASE, 0x40004e00
 573              	.set CYDEV_DEC_SIZE, 0x00000015
 574              	.set CYDEV_DEC_CR, 0x40004e00
 575              	.set CYDEV_DEC_SR, 0x40004e01
 576              	.set CYDEV_DEC_SHIFT1, 0x40004e02
 577              	.set CYDEV_DEC_SHIFT2, 0x40004e03
 578              	.set CYDEV_DEC_DR2, 0x40004e04
 579              	.set CYDEV_DEC_DR2H, 0x40004e05
 580              	.set CYDEV_DEC_DR1, 0x40004e06
 581              	.set CYDEV_DEC_OCOR, 0x40004e08
 582              	.set CYDEV_DEC_OCORM, 0x40004e09
 583              	.set CYDEV_DEC_OCORH, 0x40004e0a
 584              	.set CYDEV_DEC_GCOR, 0x40004e0c
 585              	.set CYDEV_DEC_GCORH, 0x40004e0d
 586              	.set CYDEV_DEC_GVAL, 0x40004e0e
 587              	.set CYDEV_DEC_OUTSAMP, 0x40004e10
 588              	.set CYDEV_DEC_OUTSAMPM, 0x40004e11
 589              	.set CYDEV_DEC_OUTSAMPH, 0x40004e12
 590              	.set CYDEV_DEC_OUTSAMPS, 0x40004e13
 591              	.set CYDEV_DEC_COHER, 0x40004e14
 592              	.set CYDEV_TMR0_BASE, 0x40004f00
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 12


 593              	.set CYDEV_TMR0_SIZE, 0x0000000c
 594              	.set CYDEV_TMR0_CFG0, 0x40004f00
 595              	.set CYDEV_TMR0_CFG1, 0x40004f01
 596              	.set CYDEV_TMR0_CFG2, 0x40004f02
 597              	.set CYDEV_TMR0_SR0, 0x40004f03
 598              	.set CYDEV_TMR0_PER0, 0x40004f04
 599              	.set CYDEV_TMR0_PER1, 0x40004f05
 600              	.set CYDEV_TMR0_CNT_CMP0, 0x40004f06
 601              	.set CYDEV_TMR0_CNT_CMP1, 0x40004f07
 602              	.set CYDEV_TMR0_CAP0, 0x40004f08
 603              	.set CYDEV_TMR0_CAP1, 0x40004f09
 604              	.set CYDEV_TMR0_RT0, 0x40004f0a
 605              	.set CYDEV_TMR0_RT1, 0x40004f0b
 606              	.set CYDEV_TMR1_BASE, 0x40004f0c
 607              	.set CYDEV_TMR1_SIZE, 0x0000000c
 608              	.set CYDEV_TMR1_CFG0, 0x40004f0c
 609              	.set CYDEV_TMR1_CFG1, 0x40004f0d
 610              	.set CYDEV_TMR1_CFG2, 0x40004f0e
 611              	.set CYDEV_TMR1_SR0, 0x40004f0f
 612              	.set CYDEV_TMR1_PER0, 0x40004f10
 613              	.set CYDEV_TMR1_PER1, 0x40004f11
 614              	.set CYDEV_TMR1_CNT_CMP0, 0x40004f12
 615              	.set CYDEV_TMR1_CNT_CMP1, 0x40004f13
 616              	.set CYDEV_TMR1_CAP0, 0x40004f14
 617              	.set CYDEV_TMR1_CAP1, 0x40004f15
 618              	.set CYDEV_TMR1_RT0, 0x40004f16
 619              	.set CYDEV_TMR1_RT1, 0x40004f17
 620              	.set CYDEV_TMR2_BASE, 0x40004f18
 621              	.set CYDEV_TMR2_SIZE, 0x0000000c
 622              	.set CYDEV_TMR2_CFG0, 0x40004f18
 623              	.set CYDEV_TMR2_CFG1, 0x40004f19
 624              	.set CYDEV_TMR2_CFG2, 0x40004f1a
 625              	.set CYDEV_TMR2_SR0, 0x40004f1b
 626              	.set CYDEV_TMR2_PER0, 0x40004f1c
 627              	.set CYDEV_TMR2_PER1, 0x40004f1d
 628              	.set CYDEV_TMR2_CNT_CMP0, 0x40004f1e
 629              	.set CYDEV_TMR2_CNT_CMP1, 0x40004f1f
 630              	.set CYDEV_TMR2_CAP0, 0x40004f20
 631              	.set CYDEV_TMR2_CAP1, 0x40004f21
 632              	.set CYDEV_TMR2_RT0, 0x40004f22
 633              	.set CYDEV_TMR2_RT1, 0x40004f23
 634              	.set CYDEV_TMR3_BASE, 0x40004f24
 635              	.set CYDEV_TMR3_SIZE, 0x0000000c
 636              	.set CYDEV_TMR3_CFG0, 0x40004f24
 637              	.set CYDEV_TMR3_CFG1, 0x40004f25
 638              	.set CYDEV_TMR3_CFG2, 0x40004f26
 639              	.set CYDEV_TMR3_SR0, 0x40004f27
 640              	.set CYDEV_TMR3_PER0, 0x40004f28
 641              	.set CYDEV_TMR3_PER1, 0x40004f29
 642              	.set CYDEV_TMR3_CNT_CMP0, 0x40004f2a
 643              	.set CYDEV_TMR3_CNT_CMP1, 0x40004f2b
 644              	.set CYDEV_TMR3_CAP0, 0x40004f2c
 645              	.set CYDEV_TMR3_CAP1, 0x40004f2d
 646              	.set CYDEV_TMR3_RT0, 0x40004f2e
 647              	.set CYDEV_TMR3_RT1, 0x40004f2f
 648              	.set CYDEV_IO_BASE, 0x40005000
 649              	.set CYDEV_IO_SIZE, 0x00000200
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 13


 650              	.set CYDEV_IO_PC_BASE, 0x40005000
 651              	.set CYDEV_IO_PC_SIZE, 0x00000080
 652              	.set CYDEV_IO_PC_PRT0_BASE, 0x40005000
 653              	.set CYDEV_IO_PC_PRT0_SIZE, 0x00000008
 654              	.set CYDEV_IO_PC_PRT0_PC0, 0x40005000
 655              	.set CYDEV_IO_PC_PRT0_PC1, 0x40005001
 656              	.set CYDEV_IO_PC_PRT0_PC2, 0x40005002
 657              	.set CYDEV_IO_PC_PRT0_PC3, 0x40005003
 658              	.set CYDEV_IO_PC_PRT0_PC4, 0x40005004
 659              	.set CYDEV_IO_PC_PRT0_PC5, 0x40005005
 660              	.set CYDEV_IO_PC_PRT0_PC6, 0x40005006
 661              	.set CYDEV_IO_PC_PRT0_PC7, 0x40005007
 662              	.set CYDEV_IO_PC_PRT1_BASE, 0x40005008
 663              	.set CYDEV_IO_PC_PRT1_SIZE, 0x00000008
 664              	.set CYDEV_IO_PC_PRT1_PC0, 0x40005008
 665              	.set CYDEV_IO_PC_PRT1_PC1, 0x40005009
 666              	.set CYDEV_IO_PC_PRT1_PC2, 0x4000500a
 667              	.set CYDEV_IO_PC_PRT1_PC3, 0x4000500b
 668              	.set CYDEV_IO_PC_PRT1_PC4, 0x4000500c
 669              	.set CYDEV_IO_PC_PRT1_PC5, 0x4000500d
 670              	.set CYDEV_IO_PC_PRT1_PC6, 0x4000500e
 671              	.set CYDEV_IO_PC_PRT1_PC7, 0x4000500f
 672              	.set CYDEV_IO_PC_PRT2_BASE, 0x40005010
 673              	.set CYDEV_IO_PC_PRT2_SIZE, 0x00000008
 674              	.set CYDEV_IO_PC_PRT2_PC0, 0x40005010
 675              	.set CYDEV_IO_PC_PRT2_PC1, 0x40005011
 676              	.set CYDEV_IO_PC_PRT2_PC2, 0x40005012
 677              	.set CYDEV_IO_PC_PRT2_PC3, 0x40005013
 678              	.set CYDEV_IO_PC_PRT2_PC4, 0x40005014
 679              	.set CYDEV_IO_PC_PRT2_PC5, 0x40005015
 680              	.set CYDEV_IO_PC_PRT2_PC6, 0x40005016
 681              	.set CYDEV_IO_PC_PRT2_PC7, 0x40005017
 682              	.set CYDEV_IO_PC_PRT3_BASE, 0x40005018
 683              	.set CYDEV_IO_PC_PRT3_SIZE, 0x00000008
 684              	.set CYDEV_IO_PC_PRT3_PC0, 0x40005018
 685              	.set CYDEV_IO_PC_PRT3_PC1, 0x40005019
 686              	.set CYDEV_IO_PC_PRT3_PC2, 0x4000501a
 687              	.set CYDEV_IO_PC_PRT3_PC3, 0x4000501b
 688              	.set CYDEV_IO_PC_PRT3_PC4, 0x4000501c
 689              	.set CYDEV_IO_PC_PRT3_PC5, 0x4000501d
 690              	.set CYDEV_IO_PC_PRT3_PC6, 0x4000501e
 691              	.set CYDEV_IO_PC_PRT3_PC7, 0x4000501f
 692              	.set CYDEV_IO_PC_PRT4_BASE, 0x40005020
 693              	.set CYDEV_IO_PC_PRT4_SIZE, 0x00000008
 694              	.set CYDEV_IO_PC_PRT4_PC0, 0x40005020
 695              	.set CYDEV_IO_PC_PRT4_PC1, 0x40005021
 696              	.set CYDEV_IO_PC_PRT4_PC2, 0x40005022
 697              	.set CYDEV_IO_PC_PRT4_PC3, 0x40005023
 698              	.set CYDEV_IO_PC_PRT4_PC4, 0x40005024
 699              	.set CYDEV_IO_PC_PRT4_PC5, 0x40005025
 700              	.set CYDEV_IO_PC_PRT4_PC6, 0x40005026
 701              	.set CYDEV_IO_PC_PRT4_PC7, 0x40005027
 702              	.set CYDEV_IO_PC_PRT5_BASE, 0x40005028
 703              	.set CYDEV_IO_PC_PRT5_SIZE, 0x00000008
 704              	.set CYDEV_IO_PC_PRT5_PC0, 0x40005028
 705              	.set CYDEV_IO_PC_PRT5_PC1, 0x40005029
 706              	.set CYDEV_IO_PC_PRT5_PC2, 0x4000502a
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 14


 707              	.set CYDEV_IO_PC_PRT5_PC3, 0x4000502b
 708              	.set CYDEV_IO_PC_PRT5_PC4, 0x4000502c
 709              	.set CYDEV_IO_PC_PRT5_PC5, 0x4000502d
 710              	.set CYDEV_IO_PC_PRT5_PC6, 0x4000502e
 711              	.set CYDEV_IO_PC_PRT5_PC7, 0x4000502f
 712              	.set CYDEV_IO_PC_PRT6_BASE, 0x40005030
 713              	.set CYDEV_IO_PC_PRT6_SIZE, 0x00000008
 714              	.set CYDEV_IO_PC_PRT6_PC0, 0x40005030
 715              	.set CYDEV_IO_PC_PRT6_PC1, 0x40005031
 716              	.set CYDEV_IO_PC_PRT6_PC2, 0x40005032
 717              	.set CYDEV_IO_PC_PRT6_PC3, 0x40005033
 718              	.set CYDEV_IO_PC_PRT6_PC4, 0x40005034
 719              	.set CYDEV_IO_PC_PRT6_PC5, 0x40005035
 720              	.set CYDEV_IO_PC_PRT6_PC6, 0x40005036
 721              	.set CYDEV_IO_PC_PRT6_PC7, 0x40005037
 722              	.set CYDEV_IO_PC_PRT12_BASE, 0x40005060
 723              	.set CYDEV_IO_PC_PRT12_SIZE, 0x00000008
 724              	.set CYDEV_IO_PC_PRT12_PC0, 0x40005060
 725              	.set CYDEV_IO_PC_PRT12_PC1, 0x40005061
 726              	.set CYDEV_IO_PC_PRT12_PC2, 0x40005062
 727              	.set CYDEV_IO_PC_PRT12_PC3, 0x40005063
 728              	.set CYDEV_IO_PC_PRT12_PC4, 0x40005064
 729              	.set CYDEV_IO_PC_PRT12_PC5, 0x40005065
 730              	.set CYDEV_IO_PC_PRT12_PC6, 0x40005066
 731              	.set CYDEV_IO_PC_PRT12_PC7, 0x40005067
 732              	.set CYDEV_IO_PC_PRT15_BASE, 0x40005078
 733              	.set CYDEV_IO_PC_PRT15_SIZE, 0x00000006
 734              	.set CYDEV_IO_PC_PRT15_PC0, 0x40005078
 735              	.set CYDEV_IO_PC_PRT15_PC1, 0x40005079
 736              	.set CYDEV_IO_PC_PRT15_PC2, 0x4000507a
 737              	.set CYDEV_IO_PC_PRT15_PC3, 0x4000507b
 738              	.set CYDEV_IO_PC_PRT15_PC4, 0x4000507c
 739              	.set CYDEV_IO_PC_PRT15_PC5, 0x4000507d
 740              	.set CYDEV_IO_PC_PRT15_7_6_BASE, 0x4000507e
 741              	.set CYDEV_IO_PC_PRT15_7_6_SIZE, 0x00000002
 742              	.set CYDEV_IO_PC_PRT15_7_6_PC0, 0x4000507e
 743              	.set CYDEV_IO_PC_PRT15_7_6_PC1, 0x4000507f
 744              	.set CYDEV_IO_DR_BASE, 0x40005080
 745              	.set CYDEV_IO_DR_SIZE, 0x00000010
 746              	.set CYDEV_IO_DR_PRT0_BASE, 0x40005080
 747              	.set CYDEV_IO_DR_PRT0_SIZE, 0x00000001
 748              	.set CYDEV_IO_DR_PRT0_DR_ALIAS, 0x40005080
 749              	.set CYDEV_IO_DR_PRT1_BASE, 0x40005081
 750              	.set CYDEV_IO_DR_PRT1_SIZE, 0x00000001
 751              	.set CYDEV_IO_DR_PRT1_DR_ALIAS, 0x40005081
 752              	.set CYDEV_IO_DR_PRT2_BASE, 0x40005082
 753              	.set CYDEV_IO_DR_PRT2_SIZE, 0x00000001
 754              	.set CYDEV_IO_DR_PRT2_DR_ALIAS, 0x40005082
 755              	.set CYDEV_IO_DR_PRT3_BASE, 0x40005083
 756              	.set CYDEV_IO_DR_PRT3_SIZE, 0x00000001
 757              	.set CYDEV_IO_DR_PRT3_DR_ALIAS, 0x40005083
 758              	.set CYDEV_IO_DR_PRT4_BASE, 0x40005084
 759              	.set CYDEV_IO_DR_PRT4_SIZE, 0x00000001
 760              	.set CYDEV_IO_DR_PRT4_DR_ALIAS, 0x40005084
 761              	.set CYDEV_IO_DR_PRT5_BASE, 0x40005085
 762              	.set CYDEV_IO_DR_PRT5_SIZE, 0x00000001
 763              	.set CYDEV_IO_DR_PRT5_DR_ALIAS, 0x40005085
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 15


 764              	.set CYDEV_IO_DR_PRT6_BASE, 0x40005086
 765              	.set CYDEV_IO_DR_PRT6_SIZE, 0x00000001
 766              	.set CYDEV_IO_DR_PRT6_DR_ALIAS, 0x40005086
 767              	.set CYDEV_IO_DR_PRT12_BASE, 0x4000508c
 768              	.set CYDEV_IO_DR_PRT12_SIZE, 0x00000001
 769              	.set CYDEV_IO_DR_PRT12_DR_ALIAS, 0x4000508c
 770              	.set CYDEV_IO_DR_PRT15_BASE, 0x4000508f
 771              	.set CYDEV_IO_DR_PRT15_SIZE, 0x00000001
 772              	.set CYDEV_IO_DR_PRT15_DR_15_ALIAS, 0x4000508f
 773              	.set CYDEV_IO_PS_BASE, 0x40005090
 774              	.set CYDEV_IO_PS_SIZE, 0x00000010
 775              	.set CYDEV_IO_PS_PRT0_BASE, 0x40005090
 776              	.set CYDEV_IO_PS_PRT0_SIZE, 0x00000001
 777              	.set CYDEV_IO_PS_PRT0_PS_ALIAS, 0x40005090
 778              	.set CYDEV_IO_PS_PRT1_BASE, 0x40005091
 779              	.set CYDEV_IO_PS_PRT1_SIZE, 0x00000001
 780              	.set CYDEV_IO_PS_PRT1_PS_ALIAS, 0x40005091
 781              	.set CYDEV_IO_PS_PRT2_BASE, 0x40005092
 782              	.set CYDEV_IO_PS_PRT2_SIZE, 0x00000001
 783              	.set CYDEV_IO_PS_PRT2_PS_ALIAS, 0x40005092
 784              	.set CYDEV_IO_PS_PRT3_BASE, 0x40005093
 785              	.set CYDEV_IO_PS_PRT3_SIZE, 0x00000001
 786              	.set CYDEV_IO_PS_PRT3_PS_ALIAS, 0x40005093
 787              	.set CYDEV_IO_PS_PRT4_BASE, 0x40005094
 788              	.set CYDEV_IO_PS_PRT4_SIZE, 0x00000001
 789              	.set CYDEV_IO_PS_PRT4_PS_ALIAS, 0x40005094
 790              	.set CYDEV_IO_PS_PRT5_BASE, 0x40005095
 791              	.set CYDEV_IO_PS_PRT5_SIZE, 0x00000001
 792              	.set CYDEV_IO_PS_PRT5_PS_ALIAS, 0x40005095
 793              	.set CYDEV_IO_PS_PRT6_BASE, 0x40005096
 794              	.set CYDEV_IO_PS_PRT6_SIZE, 0x00000001
 795              	.set CYDEV_IO_PS_PRT6_PS_ALIAS, 0x40005096
 796              	.set CYDEV_IO_PS_PRT12_BASE, 0x4000509c
 797              	.set CYDEV_IO_PS_PRT12_SIZE, 0x00000001
 798              	.set CYDEV_IO_PS_PRT12_PS_ALIAS, 0x4000509c
 799              	.set CYDEV_IO_PS_PRT15_BASE, 0x4000509f
 800              	.set CYDEV_IO_PS_PRT15_SIZE, 0x00000001
 801              	.set CYDEV_IO_PS_PRT15_PS15_ALIAS, 0x4000509f
 802              	.set CYDEV_IO_PRT_BASE, 0x40005100
 803              	.set CYDEV_IO_PRT_SIZE, 0x00000100
 804              	.set CYDEV_IO_PRT_PRT0_BASE, 0x40005100
 805              	.set CYDEV_IO_PRT_PRT0_SIZE, 0x00000010
 806              	.set CYDEV_IO_PRT_PRT0_DR, 0x40005100
 807              	.set CYDEV_IO_PRT_PRT0_PS, 0x40005101
 808              	.set CYDEV_IO_PRT_PRT0_DM0, 0x40005102
 809              	.set CYDEV_IO_PRT_PRT0_DM1, 0x40005103
 810              	.set CYDEV_IO_PRT_PRT0_DM2, 0x40005104
 811              	.set CYDEV_IO_PRT_PRT0_SLW, 0x40005105
 812              	.set CYDEV_IO_PRT_PRT0_BYP, 0x40005106
 813              	.set CYDEV_IO_PRT_PRT0_BIE, 0x40005107
 814              	.set CYDEV_IO_PRT_PRT0_INP_DIS, 0x40005108
 815              	.set CYDEV_IO_PRT_PRT0_CTL, 0x40005109
 816              	.set CYDEV_IO_PRT_PRT0_PRT, 0x4000510a
 817              	.set CYDEV_IO_PRT_PRT0_BIT_MASK, 0x4000510b
 818              	.set CYDEV_IO_PRT_PRT0_AMUX, 0x4000510c
 819              	.set CYDEV_IO_PRT_PRT0_AG, 0x4000510d
 820              	.set CYDEV_IO_PRT_PRT0_LCD_COM_SEG, 0x4000510e
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 16


 821              	.set CYDEV_IO_PRT_PRT0_LCD_EN, 0x4000510f
 822              	.set CYDEV_IO_PRT_PRT1_BASE, 0x40005110
 823              	.set CYDEV_IO_PRT_PRT1_SIZE, 0x00000010
 824              	.set CYDEV_IO_PRT_PRT1_DR, 0x40005110
 825              	.set CYDEV_IO_PRT_PRT1_PS, 0x40005111
 826              	.set CYDEV_IO_PRT_PRT1_DM0, 0x40005112
 827              	.set CYDEV_IO_PRT_PRT1_DM1, 0x40005113
 828              	.set CYDEV_IO_PRT_PRT1_DM2, 0x40005114
 829              	.set CYDEV_IO_PRT_PRT1_SLW, 0x40005115
 830              	.set CYDEV_IO_PRT_PRT1_BYP, 0x40005116
 831              	.set CYDEV_IO_PRT_PRT1_BIE, 0x40005117
 832              	.set CYDEV_IO_PRT_PRT1_INP_DIS, 0x40005118
 833              	.set CYDEV_IO_PRT_PRT1_CTL, 0x40005119
 834              	.set CYDEV_IO_PRT_PRT1_PRT, 0x4000511a
 835              	.set CYDEV_IO_PRT_PRT1_BIT_MASK, 0x4000511b
 836              	.set CYDEV_IO_PRT_PRT1_AMUX, 0x4000511c
 837              	.set CYDEV_IO_PRT_PRT1_AG, 0x4000511d
 838              	.set CYDEV_IO_PRT_PRT1_LCD_COM_SEG, 0x4000511e
 839              	.set CYDEV_IO_PRT_PRT1_LCD_EN, 0x4000511f
 840              	.set CYDEV_IO_PRT_PRT2_BASE, 0x40005120
 841              	.set CYDEV_IO_PRT_PRT2_SIZE, 0x00000010
 842              	.set CYDEV_IO_PRT_PRT2_DR, 0x40005120
 843              	.set CYDEV_IO_PRT_PRT2_PS, 0x40005121
 844              	.set CYDEV_IO_PRT_PRT2_DM0, 0x40005122
 845              	.set CYDEV_IO_PRT_PRT2_DM1, 0x40005123
 846              	.set CYDEV_IO_PRT_PRT2_DM2, 0x40005124
 847              	.set CYDEV_IO_PRT_PRT2_SLW, 0x40005125
 848              	.set CYDEV_IO_PRT_PRT2_BYP, 0x40005126
 849              	.set CYDEV_IO_PRT_PRT2_BIE, 0x40005127
 850              	.set CYDEV_IO_PRT_PRT2_INP_DIS, 0x40005128
 851              	.set CYDEV_IO_PRT_PRT2_CTL, 0x40005129
 852              	.set CYDEV_IO_PRT_PRT2_PRT, 0x4000512a
 853              	.set CYDEV_IO_PRT_PRT2_BIT_MASK, 0x4000512b
 854              	.set CYDEV_IO_PRT_PRT2_AMUX, 0x4000512c
 855              	.set CYDEV_IO_PRT_PRT2_AG, 0x4000512d
 856              	.set CYDEV_IO_PRT_PRT2_LCD_COM_SEG, 0x4000512e
 857              	.set CYDEV_IO_PRT_PRT2_LCD_EN, 0x4000512f
 858              	.set CYDEV_IO_PRT_PRT3_BASE, 0x40005130
 859              	.set CYDEV_IO_PRT_PRT3_SIZE, 0x00000010
 860              	.set CYDEV_IO_PRT_PRT3_DR, 0x40005130
 861              	.set CYDEV_IO_PRT_PRT3_PS, 0x40005131
 862              	.set CYDEV_IO_PRT_PRT3_DM0, 0x40005132
 863              	.set CYDEV_IO_PRT_PRT3_DM1, 0x40005133
 864              	.set CYDEV_IO_PRT_PRT3_DM2, 0x40005134
 865              	.set CYDEV_IO_PRT_PRT3_SLW, 0x40005135
 866              	.set CYDEV_IO_PRT_PRT3_BYP, 0x40005136
 867              	.set CYDEV_IO_PRT_PRT3_BIE, 0x40005137
 868              	.set CYDEV_IO_PRT_PRT3_INP_DIS, 0x40005138
 869              	.set CYDEV_IO_PRT_PRT3_CTL, 0x40005139
 870              	.set CYDEV_IO_PRT_PRT3_PRT, 0x4000513a
 871              	.set CYDEV_IO_PRT_PRT3_BIT_MASK, 0x4000513b
 872              	.set CYDEV_IO_PRT_PRT3_AMUX, 0x4000513c
 873              	.set CYDEV_IO_PRT_PRT3_AG, 0x4000513d
 874              	.set CYDEV_IO_PRT_PRT3_LCD_COM_SEG, 0x4000513e
 875              	.set CYDEV_IO_PRT_PRT3_LCD_EN, 0x4000513f
 876              	.set CYDEV_IO_PRT_PRT4_BASE, 0x40005140
 877              	.set CYDEV_IO_PRT_PRT4_SIZE, 0x00000010
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 17


 878              	.set CYDEV_IO_PRT_PRT4_DR, 0x40005140
 879              	.set CYDEV_IO_PRT_PRT4_PS, 0x40005141
 880              	.set CYDEV_IO_PRT_PRT4_DM0, 0x40005142
 881              	.set CYDEV_IO_PRT_PRT4_DM1, 0x40005143
 882              	.set CYDEV_IO_PRT_PRT4_DM2, 0x40005144
 883              	.set CYDEV_IO_PRT_PRT4_SLW, 0x40005145
 884              	.set CYDEV_IO_PRT_PRT4_BYP, 0x40005146
 885              	.set CYDEV_IO_PRT_PRT4_BIE, 0x40005147
 886              	.set CYDEV_IO_PRT_PRT4_INP_DIS, 0x40005148
 887              	.set CYDEV_IO_PRT_PRT4_CTL, 0x40005149
 888              	.set CYDEV_IO_PRT_PRT4_PRT, 0x4000514a
 889              	.set CYDEV_IO_PRT_PRT4_BIT_MASK, 0x4000514b
 890              	.set CYDEV_IO_PRT_PRT4_AMUX, 0x4000514c
 891              	.set CYDEV_IO_PRT_PRT4_AG, 0x4000514d
 892              	.set CYDEV_IO_PRT_PRT4_LCD_COM_SEG, 0x4000514e
 893              	.set CYDEV_IO_PRT_PRT4_LCD_EN, 0x4000514f
 894              	.set CYDEV_IO_PRT_PRT5_BASE, 0x40005150
 895              	.set CYDEV_IO_PRT_PRT5_SIZE, 0x00000010
 896              	.set CYDEV_IO_PRT_PRT5_DR, 0x40005150
 897              	.set CYDEV_IO_PRT_PRT5_PS, 0x40005151
 898              	.set CYDEV_IO_PRT_PRT5_DM0, 0x40005152
 899              	.set CYDEV_IO_PRT_PRT5_DM1, 0x40005153
 900              	.set CYDEV_IO_PRT_PRT5_DM2, 0x40005154
 901              	.set CYDEV_IO_PRT_PRT5_SLW, 0x40005155
 902              	.set CYDEV_IO_PRT_PRT5_BYP, 0x40005156
 903              	.set CYDEV_IO_PRT_PRT5_BIE, 0x40005157
 904              	.set CYDEV_IO_PRT_PRT5_INP_DIS, 0x40005158
 905              	.set CYDEV_IO_PRT_PRT5_CTL, 0x40005159
 906              	.set CYDEV_IO_PRT_PRT5_PRT, 0x4000515a
 907              	.set CYDEV_IO_PRT_PRT5_BIT_MASK, 0x4000515b
 908              	.set CYDEV_IO_PRT_PRT5_AMUX, 0x4000515c
 909              	.set CYDEV_IO_PRT_PRT5_AG, 0x4000515d
 910              	.set CYDEV_IO_PRT_PRT5_LCD_COM_SEG, 0x4000515e
 911              	.set CYDEV_IO_PRT_PRT5_LCD_EN, 0x4000515f
 912              	.set CYDEV_IO_PRT_PRT6_BASE, 0x40005160
 913              	.set CYDEV_IO_PRT_PRT6_SIZE, 0x00000010
 914              	.set CYDEV_IO_PRT_PRT6_DR, 0x40005160
 915              	.set CYDEV_IO_PRT_PRT6_PS, 0x40005161
 916              	.set CYDEV_IO_PRT_PRT6_DM0, 0x40005162
 917              	.set CYDEV_IO_PRT_PRT6_DM1, 0x40005163
 918              	.set CYDEV_IO_PRT_PRT6_DM2, 0x40005164
 919              	.set CYDEV_IO_PRT_PRT6_SLW, 0x40005165
 920              	.set CYDEV_IO_PRT_PRT6_BYP, 0x40005166
 921              	.set CYDEV_IO_PRT_PRT6_BIE, 0x40005167
 922              	.set CYDEV_IO_PRT_PRT6_INP_DIS, 0x40005168
 923              	.set CYDEV_IO_PRT_PRT6_CTL, 0x40005169
 924              	.set CYDEV_IO_PRT_PRT6_PRT, 0x4000516a
 925              	.set CYDEV_IO_PRT_PRT6_BIT_MASK, 0x4000516b
 926              	.set CYDEV_IO_PRT_PRT6_AMUX, 0x4000516c
 927              	.set CYDEV_IO_PRT_PRT6_AG, 0x4000516d
 928              	.set CYDEV_IO_PRT_PRT6_LCD_COM_SEG, 0x4000516e
 929              	.set CYDEV_IO_PRT_PRT6_LCD_EN, 0x4000516f
 930              	.set CYDEV_IO_PRT_PRT12_BASE, 0x400051c0
 931              	.set CYDEV_IO_PRT_PRT12_SIZE, 0x00000010
 932              	.set CYDEV_IO_PRT_PRT12_DR, 0x400051c0
 933              	.set CYDEV_IO_PRT_PRT12_PS, 0x400051c1
 934              	.set CYDEV_IO_PRT_PRT12_DM0, 0x400051c2
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 18


 935              	.set CYDEV_IO_PRT_PRT12_DM1, 0x400051c3
 936              	.set CYDEV_IO_PRT_PRT12_DM2, 0x400051c4
 937              	.set CYDEV_IO_PRT_PRT12_SLW, 0x400051c5
 938              	.set CYDEV_IO_PRT_PRT12_BYP, 0x400051c6
 939              	.set CYDEV_IO_PRT_PRT12_BIE, 0x400051c7
 940              	.set CYDEV_IO_PRT_PRT12_INP_DIS, 0x400051c8
 941              	.set CYDEV_IO_PRT_PRT12_SIO_HYST_EN, 0x400051c9
 942              	.set CYDEV_IO_PRT_PRT12_PRT, 0x400051ca
 943              	.set CYDEV_IO_PRT_PRT12_BIT_MASK, 0x400051cb
 944              	.set CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ, 0x400051cc
 945              	.set CYDEV_IO_PRT_PRT12_AG, 0x400051cd
 946              	.set CYDEV_IO_PRT_PRT12_SIO_CFG, 0x400051ce
 947              	.set CYDEV_IO_PRT_PRT12_SIO_DIFF, 0x400051cf
 948              	.set CYDEV_IO_PRT_PRT15_BASE, 0x400051f0
 949              	.set CYDEV_IO_PRT_PRT15_SIZE, 0x00000010
 950              	.set CYDEV_IO_PRT_PRT15_DR, 0x400051f0
 951              	.set CYDEV_IO_PRT_PRT15_PS, 0x400051f1
 952              	.set CYDEV_IO_PRT_PRT15_DM0, 0x400051f2
 953              	.set CYDEV_IO_PRT_PRT15_DM1, 0x400051f3
 954              	.set CYDEV_IO_PRT_PRT15_DM2, 0x400051f4
 955              	.set CYDEV_IO_PRT_PRT15_SLW, 0x400051f5
 956              	.set CYDEV_IO_PRT_PRT15_BYP, 0x400051f6
 957              	.set CYDEV_IO_PRT_PRT15_BIE, 0x400051f7
 958              	.set CYDEV_IO_PRT_PRT15_INP_DIS, 0x400051f8
 959              	.set CYDEV_IO_PRT_PRT15_CTL, 0x400051f9
 960              	.set CYDEV_IO_PRT_PRT15_PRT, 0x400051fa
 961              	.set CYDEV_IO_PRT_PRT15_BIT_MASK, 0x400051fb
 962              	.set CYDEV_IO_PRT_PRT15_AMUX, 0x400051fc
 963              	.set CYDEV_IO_PRT_PRT15_AG, 0x400051fd
 964              	.set CYDEV_IO_PRT_PRT15_LCD_COM_SEG, 0x400051fe
 965              	.set CYDEV_IO_PRT_PRT15_LCD_EN, 0x400051ff
 966              	.set CYDEV_PRTDSI_BASE, 0x40005200
 967              	.set CYDEV_PRTDSI_SIZE, 0x0000007f
 968              	.set CYDEV_PRTDSI_PRT0_BASE, 0x40005200
 969              	.set CYDEV_PRTDSI_PRT0_SIZE, 0x00000007
 970              	.set CYDEV_PRTDSI_PRT0_OUT_SEL0, 0x40005200
 971              	.set CYDEV_PRTDSI_PRT0_OUT_SEL1, 0x40005201
 972              	.set CYDEV_PRTDSI_PRT0_OE_SEL0, 0x40005202
 973              	.set CYDEV_PRTDSI_PRT0_OE_SEL1, 0x40005203
 974              	.set CYDEV_PRTDSI_PRT0_DBL_SYNC_IN, 0x40005204
 975              	.set CYDEV_PRTDSI_PRT0_SYNC_OUT, 0x40005205
 976              	.set CYDEV_PRTDSI_PRT0_CAPS_SEL, 0x40005206
 977              	.set CYDEV_PRTDSI_PRT1_BASE, 0x40005208
 978              	.set CYDEV_PRTDSI_PRT1_SIZE, 0x00000007
 979              	.set CYDEV_PRTDSI_PRT1_OUT_SEL0, 0x40005208
 980              	.set CYDEV_PRTDSI_PRT1_OUT_SEL1, 0x40005209
 981              	.set CYDEV_PRTDSI_PRT1_OE_SEL0, 0x4000520a
 982              	.set CYDEV_PRTDSI_PRT1_OE_SEL1, 0x4000520b
 983              	.set CYDEV_PRTDSI_PRT1_DBL_SYNC_IN, 0x4000520c
 984              	.set CYDEV_PRTDSI_PRT1_SYNC_OUT, 0x4000520d
 985              	.set CYDEV_PRTDSI_PRT1_CAPS_SEL, 0x4000520e
 986              	.set CYDEV_PRTDSI_PRT2_BASE, 0x40005210
 987              	.set CYDEV_PRTDSI_PRT2_SIZE, 0x00000007
 988              	.set CYDEV_PRTDSI_PRT2_OUT_SEL0, 0x40005210
 989              	.set CYDEV_PRTDSI_PRT2_OUT_SEL1, 0x40005211
 990              	.set CYDEV_PRTDSI_PRT2_OE_SEL0, 0x40005212
 991              	.set CYDEV_PRTDSI_PRT2_OE_SEL1, 0x40005213
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 19


 992              	.set CYDEV_PRTDSI_PRT2_DBL_SYNC_IN, 0x40005214
 993              	.set CYDEV_PRTDSI_PRT2_SYNC_OUT, 0x40005215
 994              	.set CYDEV_PRTDSI_PRT2_CAPS_SEL, 0x40005216
 995              	.set CYDEV_PRTDSI_PRT3_BASE, 0x40005218
 996              	.set CYDEV_PRTDSI_PRT3_SIZE, 0x00000007
 997              	.set CYDEV_PRTDSI_PRT3_OUT_SEL0, 0x40005218
 998              	.set CYDEV_PRTDSI_PRT3_OUT_SEL1, 0x40005219
 999              	.set CYDEV_PRTDSI_PRT3_OE_SEL0, 0x4000521a
 1000              	.set CYDEV_PRTDSI_PRT3_OE_SEL1, 0x4000521b
 1001              	.set CYDEV_PRTDSI_PRT3_DBL_SYNC_IN, 0x4000521c
 1002              	.set CYDEV_PRTDSI_PRT3_SYNC_OUT, 0x4000521d
 1003              	.set CYDEV_PRTDSI_PRT3_CAPS_SEL, 0x4000521e
 1004              	.set CYDEV_PRTDSI_PRT4_BASE, 0x40005220
 1005              	.set CYDEV_PRTDSI_PRT4_SIZE, 0x00000007
 1006              	.set CYDEV_PRTDSI_PRT4_OUT_SEL0, 0x40005220
 1007              	.set CYDEV_PRTDSI_PRT4_OUT_SEL1, 0x40005221
 1008              	.set CYDEV_PRTDSI_PRT4_OE_SEL0, 0x40005222
 1009              	.set CYDEV_PRTDSI_PRT4_OE_SEL1, 0x40005223
 1010              	.set CYDEV_PRTDSI_PRT4_DBL_SYNC_IN, 0x40005224
 1011              	.set CYDEV_PRTDSI_PRT4_SYNC_OUT, 0x40005225
 1012              	.set CYDEV_PRTDSI_PRT4_CAPS_SEL, 0x40005226
 1013              	.set CYDEV_PRTDSI_PRT5_BASE, 0x40005228
 1014              	.set CYDEV_PRTDSI_PRT5_SIZE, 0x00000007
 1015              	.set CYDEV_PRTDSI_PRT5_OUT_SEL0, 0x40005228
 1016              	.set CYDEV_PRTDSI_PRT5_OUT_SEL1, 0x40005229
 1017              	.set CYDEV_PRTDSI_PRT5_OE_SEL0, 0x4000522a
 1018              	.set CYDEV_PRTDSI_PRT5_OE_SEL1, 0x4000522b
 1019              	.set CYDEV_PRTDSI_PRT5_DBL_SYNC_IN, 0x4000522c
 1020              	.set CYDEV_PRTDSI_PRT5_SYNC_OUT, 0x4000522d
 1021              	.set CYDEV_PRTDSI_PRT5_CAPS_SEL, 0x4000522e
 1022              	.set CYDEV_PRTDSI_PRT6_BASE, 0x40005230
 1023              	.set CYDEV_PRTDSI_PRT6_SIZE, 0x00000007
 1024              	.set CYDEV_PRTDSI_PRT6_OUT_SEL0, 0x40005230
 1025              	.set CYDEV_PRTDSI_PRT6_OUT_SEL1, 0x40005231
 1026              	.set CYDEV_PRTDSI_PRT6_OE_SEL0, 0x40005232
 1027              	.set CYDEV_PRTDSI_PRT6_OE_SEL1, 0x40005233
 1028              	.set CYDEV_PRTDSI_PRT6_DBL_SYNC_IN, 0x40005234
 1029              	.set CYDEV_PRTDSI_PRT6_SYNC_OUT, 0x40005235
 1030              	.set CYDEV_PRTDSI_PRT6_CAPS_SEL, 0x40005236
 1031              	.set CYDEV_PRTDSI_PRT12_BASE, 0x40005260
 1032              	.set CYDEV_PRTDSI_PRT12_SIZE, 0x00000006
 1033              	.set CYDEV_PRTDSI_PRT12_OUT_SEL0, 0x40005260
 1034              	.set CYDEV_PRTDSI_PRT12_OUT_SEL1, 0x40005261
 1035              	.set CYDEV_PRTDSI_PRT12_OE_SEL0, 0x40005262
 1036              	.set CYDEV_PRTDSI_PRT12_OE_SEL1, 0x40005263
 1037              	.set CYDEV_PRTDSI_PRT12_DBL_SYNC_IN, 0x40005264
 1038              	.set CYDEV_PRTDSI_PRT12_SYNC_OUT, 0x40005265
 1039              	.set CYDEV_PRTDSI_PRT15_BASE, 0x40005278
 1040              	.set CYDEV_PRTDSI_PRT15_SIZE, 0x00000007
 1041              	.set CYDEV_PRTDSI_PRT15_OUT_SEL0, 0x40005278
 1042              	.set CYDEV_PRTDSI_PRT15_OUT_SEL1, 0x40005279
 1043              	.set CYDEV_PRTDSI_PRT15_OE_SEL0, 0x4000527a
 1044              	.set CYDEV_PRTDSI_PRT15_OE_SEL1, 0x4000527b
 1045              	.set CYDEV_PRTDSI_PRT15_DBL_SYNC_IN, 0x4000527c
 1046              	.set CYDEV_PRTDSI_PRT15_SYNC_OUT, 0x4000527d
 1047              	.set CYDEV_PRTDSI_PRT15_CAPS_SEL, 0x4000527e
 1048              	.set CYDEV_EMIF_BASE, 0x40005400
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 20


 1049              	.set CYDEV_EMIF_SIZE, 0x00000007
 1050              	.set CYDEV_EMIF_NO_UDB, 0x40005400
 1051              	.set CYDEV_EMIF_RP_WAIT_STATES, 0x40005401
 1052              	.set CYDEV_EMIF_MEM_DWN, 0x40005402
 1053              	.set CYDEV_EMIF_MEMCLK_DIV, 0x40005403
 1054              	.set CYDEV_EMIF_CLOCK_EN, 0x40005404
 1055              	.set CYDEV_EMIF_EM_TYPE, 0x40005405
 1056              	.set CYDEV_EMIF_WP_WAIT_STATES, 0x40005406
 1057              	.set CYDEV_ANAIF_BASE, 0x40005800
 1058              	.set CYDEV_ANAIF_SIZE, 0x000003a9
 1059              	.set CYDEV_ANAIF_CFG_BASE, 0x40005800
 1060              	.set CYDEV_ANAIF_CFG_SIZE, 0x0000010f
 1061              	.set CYDEV_ANAIF_CFG_SC0_BASE, 0x40005800
 1062              	.set CYDEV_ANAIF_CFG_SC0_SIZE, 0x00000003
 1063              	.set CYDEV_ANAIF_CFG_SC0_CR0, 0x40005800
 1064              	.set CYDEV_ANAIF_CFG_SC0_CR1, 0x40005801
 1065              	.set CYDEV_ANAIF_CFG_SC0_CR2, 0x40005802
 1066              	.set CYDEV_ANAIF_CFG_SC1_BASE, 0x40005804
 1067              	.set CYDEV_ANAIF_CFG_SC1_SIZE, 0x00000003
 1068              	.set CYDEV_ANAIF_CFG_SC1_CR0, 0x40005804
 1069              	.set CYDEV_ANAIF_CFG_SC1_CR1, 0x40005805
 1070              	.set CYDEV_ANAIF_CFG_SC1_CR2, 0x40005806
 1071              	.set CYDEV_ANAIF_CFG_SC2_BASE, 0x40005808
 1072              	.set CYDEV_ANAIF_CFG_SC2_SIZE, 0x00000003
 1073              	.set CYDEV_ANAIF_CFG_SC2_CR0, 0x40005808
 1074              	.set CYDEV_ANAIF_CFG_SC2_CR1, 0x40005809
 1075              	.set CYDEV_ANAIF_CFG_SC2_CR2, 0x4000580a
 1076              	.set CYDEV_ANAIF_CFG_SC3_BASE, 0x4000580c
 1077              	.set CYDEV_ANAIF_CFG_SC3_SIZE, 0x00000003
 1078              	.set CYDEV_ANAIF_CFG_SC3_CR0, 0x4000580c
 1079              	.set CYDEV_ANAIF_CFG_SC3_CR1, 0x4000580d
 1080              	.set CYDEV_ANAIF_CFG_SC3_CR2, 0x4000580e
 1081              	.set CYDEV_ANAIF_CFG_DAC0_BASE, 0x40005820
 1082              	.set CYDEV_ANAIF_CFG_DAC0_SIZE, 0x00000003
 1083              	.set CYDEV_ANAIF_CFG_DAC0_CR0, 0x40005820
 1084              	.set CYDEV_ANAIF_CFG_DAC0_CR1, 0x40005821
 1085              	.set CYDEV_ANAIF_CFG_DAC0_TST, 0x40005822
 1086              	.set CYDEV_ANAIF_CFG_DAC1_BASE, 0x40005824
 1087              	.set CYDEV_ANAIF_CFG_DAC1_SIZE, 0x00000003
 1088              	.set CYDEV_ANAIF_CFG_DAC1_CR0, 0x40005824
 1089              	.set CYDEV_ANAIF_CFG_DAC1_CR1, 0x40005825
 1090              	.set CYDEV_ANAIF_CFG_DAC1_TST, 0x40005826
 1091              	.set CYDEV_ANAIF_CFG_DAC2_BASE, 0x40005828
 1092              	.set CYDEV_ANAIF_CFG_DAC2_SIZE, 0x00000003
 1093              	.set CYDEV_ANAIF_CFG_DAC2_CR0, 0x40005828
 1094              	.set CYDEV_ANAIF_CFG_DAC2_CR1, 0x40005829
 1095              	.set CYDEV_ANAIF_CFG_DAC2_TST, 0x4000582a
 1096              	.set CYDEV_ANAIF_CFG_DAC3_BASE, 0x4000582c
 1097              	.set CYDEV_ANAIF_CFG_DAC3_SIZE, 0x00000003
 1098              	.set CYDEV_ANAIF_CFG_DAC3_CR0, 0x4000582c
 1099              	.set CYDEV_ANAIF_CFG_DAC3_CR1, 0x4000582d
 1100              	.set CYDEV_ANAIF_CFG_DAC3_TST, 0x4000582e
 1101              	.set CYDEV_ANAIF_CFG_CMP0_BASE, 0x40005840
 1102              	.set CYDEV_ANAIF_CFG_CMP0_SIZE, 0x00000001
 1103              	.set CYDEV_ANAIF_CFG_CMP0_CR, 0x40005840
 1104              	.set CYDEV_ANAIF_CFG_CMP1_BASE, 0x40005841
 1105              	.set CYDEV_ANAIF_CFG_CMP1_SIZE, 0x00000001
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 21


 1106              	.set CYDEV_ANAIF_CFG_CMP1_CR, 0x40005841
 1107              	.set CYDEV_ANAIF_CFG_CMP2_BASE, 0x40005842
 1108              	.set CYDEV_ANAIF_CFG_CMP2_SIZE, 0x00000001
 1109              	.set CYDEV_ANAIF_CFG_CMP2_CR, 0x40005842
 1110              	.set CYDEV_ANAIF_CFG_CMP3_BASE, 0x40005843
 1111              	.set CYDEV_ANAIF_CFG_CMP3_SIZE, 0x00000001
 1112              	.set CYDEV_ANAIF_CFG_CMP3_CR, 0x40005843
 1113              	.set CYDEV_ANAIF_CFG_LUT0_BASE, 0x40005848
 1114              	.set CYDEV_ANAIF_CFG_LUT0_SIZE, 0x00000002
 1115              	.set CYDEV_ANAIF_CFG_LUT0_CR, 0x40005848
 1116              	.set CYDEV_ANAIF_CFG_LUT0_MX, 0x40005849
 1117              	.set CYDEV_ANAIF_CFG_LUT1_BASE, 0x4000584a
 1118              	.set CYDEV_ANAIF_CFG_LUT1_SIZE, 0x00000002
 1119              	.set CYDEV_ANAIF_CFG_LUT1_CR, 0x4000584a
 1120              	.set CYDEV_ANAIF_CFG_LUT1_MX, 0x4000584b
 1121              	.set CYDEV_ANAIF_CFG_LUT2_BASE, 0x4000584c
 1122              	.set CYDEV_ANAIF_CFG_LUT2_SIZE, 0x00000002
 1123              	.set CYDEV_ANAIF_CFG_LUT2_CR, 0x4000584c
 1124              	.set CYDEV_ANAIF_CFG_LUT2_MX, 0x4000584d
 1125              	.set CYDEV_ANAIF_CFG_LUT3_BASE, 0x4000584e
 1126              	.set CYDEV_ANAIF_CFG_LUT3_SIZE, 0x00000002
 1127              	.set CYDEV_ANAIF_CFG_LUT3_CR, 0x4000584e
 1128              	.set CYDEV_ANAIF_CFG_LUT3_MX, 0x4000584f
 1129              	.set CYDEV_ANAIF_CFG_OPAMP0_BASE, 0x40005858
 1130              	.set CYDEV_ANAIF_CFG_OPAMP0_SIZE, 0x00000002
 1131              	.set CYDEV_ANAIF_CFG_OPAMP0_CR, 0x40005858
 1132              	.set CYDEV_ANAIF_CFG_OPAMP0_RSVD, 0x40005859
 1133              	.set CYDEV_ANAIF_CFG_OPAMP1_BASE, 0x4000585a
 1134              	.set CYDEV_ANAIF_CFG_OPAMP1_SIZE, 0x00000002
 1135              	.set CYDEV_ANAIF_CFG_OPAMP1_CR, 0x4000585a
 1136              	.set CYDEV_ANAIF_CFG_OPAMP1_RSVD, 0x4000585b
 1137              	.set CYDEV_ANAIF_CFG_OPAMP2_BASE, 0x4000585c
 1138              	.set CYDEV_ANAIF_CFG_OPAMP2_SIZE, 0x00000002
 1139              	.set CYDEV_ANAIF_CFG_OPAMP2_CR, 0x4000585c
 1140              	.set CYDEV_ANAIF_CFG_OPAMP2_RSVD, 0x4000585d
 1141              	.set CYDEV_ANAIF_CFG_OPAMP3_BASE, 0x4000585e
 1142              	.set CYDEV_ANAIF_CFG_OPAMP3_SIZE, 0x00000002
 1143              	.set CYDEV_ANAIF_CFG_OPAMP3_CR, 0x4000585e
 1144              	.set CYDEV_ANAIF_CFG_OPAMP3_RSVD, 0x4000585f
 1145              	.set CYDEV_ANAIF_CFG_LCDDAC_BASE, 0x40005868
 1146              	.set CYDEV_ANAIF_CFG_LCDDAC_SIZE, 0x00000002
 1147              	.set CYDEV_ANAIF_CFG_LCDDAC_CR0, 0x40005868
 1148              	.set CYDEV_ANAIF_CFG_LCDDAC_CR1, 0x40005869
 1149              	.set CYDEV_ANAIF_CFG_LCDDRV_BASE, 0x4000586a
 1150              	.set CYDEV_ANAIF_CFG_LCDDRV_SIZE, 0x00000001
 1151              	.set CYDEV_ANAIF_CFG_LCDDRV_CR, 0x4000586a
 1152              	.set CYDEV_ANAIF_CFG_LCDTMR_BASE, 0x4000586b
 1153              	.set CYDEV_ANAIF_CFG_LCDTMR_SIZE, 0x00000001
 1154              	.set CYDEV_ANAIF_CFG_LCDTMR_CFG, 0x4000586b
 1155              	.set CYDEV_ANAIF_CFG_BG_BASE, 0x4000586c
 1156              	.set CYDEV_ANAIF_CFG_BG_SIZE, 0x00000004
 1157              	.set CYDEV_ANAIF_CFG_BG_CR0, 0x4000586c
 1158              	.set CYDEV_ANAIF_CFG_BG_RSVD, 0x4000586d
 1159              	.set CYDEV_ANAIF_CFG_BG_DFT0, 0x4000586e
 1160              	.set CYDEV_ANAIF_CFG_BG_DFT1, 0x4000586f
 1161              	.set CYDEV_ANAIF_CFG_CAPSL_BASE, 0x40005870
 1162              	.set CYDEV_ANAIF_CFG_CAPSL_SIZE, 0x00000002
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 22


 1163              	.set CYDEV_ANAIF_CFG_CAPSL_CFG0, 0x40005870
 1164              	.set CYDEV_ANAIF_CFG_CAPSL_CFG1, 0x40005871
 1165              	.set CYDEV_ANAIF_CFG_CAPSR_BASE, 0x40005872
 1166              	.set CYDEV_ANAIF_CFG_CAPSR_SIZE, 0x00000002
 1167              	.set CYDEV_ANAIF_CFG_CAPSR_CFG0, 0x40005872
 1168              	.set CYDEV_ANAIF_CFG_CAPSR_CFG1, 0x40005873
 1169              	.set CYDEV_ANAIF_CFG_PUMP_BASE, 0x40005876
 1170              	.set CYDEV_ANAIF_CFG_PUMP_SIZE, 0x00000002
 1171              	.set CYDEV_ANAIF_CFG_PUMP_CR0, 0x40005876
 1172              	.set CYDEV_ANAIF_CFG_PUMP_CR1, 0x40005877
 1173              	.set CYDEV_ANAIF_CFG_LPF0_BASE, 0x40005878
 1174              	.set CYDEV_ANAIF_CFG_LPF0_SIZE, 0x00000002
 1175              	.set CYDEV_ANAIF_CFG_LPF0_CR0, 0x40005878
 1176              	.set CYDEV_ANAIF_CFG_LPF0_RSVD, 0x40005879
 1177              	.set CYDEV_ANAIF_CFG_LPF1_BASE, 0x4000587a
 1178              	.set CYDEV_ANAIF_CFG_LPF1_SIZE, 0x00000002
 1179              	.set CYDEV_ANAIF_CFG_LPF1_CR0, 0x4000587a
 1180              	.set CYDEV_ANAIF_CFG_LPF1_RSVD, 0x4000587b
 1181              	.set CYDEV_ANAIF_CFG_MISC_BASE, 0x4000587c
 1182              	.set CYDEV_ANAIF_CFG_MISC_SIZE, 0x00000001
 1183              	.set CYDEV_ANAIF_CFG_MISC_CR0, 0x4000587c
 1184              	.set CYDEV_ANAIF_CFG_DSM0_BASE, 0x40005880
 1185              	.set CYDEV_ANAIF_CFG_DSM0_SIZE, 0x00000020
 1186              	.set CYDEV_ANAIF_CFG_DSM0_CR0, 0x40005880
 1187              	.set CYDEV_ANAIF_CFG_DSM0_CR1, 0x40005881
 1188              	.set CYDEV_ANAIF_CFG_DSM0_CR2, 0x40005882
 1189              	.set CYDEV_ANAIF_CFG_DSM0_CR3, 0x40005883
 1190              	.set CYDEV_ANAIF_CFG_DSM0_CR4, 0x40005884
 1191              	.set CYDEV_ANAIF_CFG_DSM0_CR5, 0x40005885
 1192              	.set CYDEV_ANAIF_CFG_DSM0_CR6, 0x40005886
 1193              	.set CYDEV_ANAIF_CFG_DSM0_CR7, 0x40005887
 1194              	.set CYDEV_ANAIF_CFG_DSM0_CR8, 0x40005888
 1195              	.set CYDEV_ANAIF_CFG_DSM0_CR9, 0x40005889
 1196              	.set CYDEV_ANAIF_CFG_DSM0_CR10, 0x4000588a
 1197              	.set CYDEV_ANAIF_CFG_DSM0_CR11, 0x4000588b
 1198              	.set CYDEV_ANAIF_CFG_DSM0_CR12, 0x4000588c
 1199              	.set CYDEV_ANAIF_CFG_DSM0_CR13, 0x4000588d
 1200              	.set CYDEV_ANAIF_CFG_DSM0_CR14, 0x4000588e
 1201              	.set CYDEV_ANAIF_CFG_DSM0_CR15, 0x4000588f
 1202              	.set CYDEV_ANAIF_CFG_DSM0_CR16, 0x40005890
 1203              	.set CYDEV_ANAIF_CFG_DSM0_CR17, 0x40005891
 1204              	.set CYDEV_ANAIF_CFG_DSM0_REF0, 0x40005892
 1205              	.set CYDEV_ANAIF_CFG_DSM0_REF1, 0x40005893
 1206              	.set CYDEV_ANAIF_CFG_DSM0_REF2, 0x40005894
 1207              	.set CYDEV_ANAIF_CFG_DSM0_REF3, 0x40005895
 1208              	.set CYDEV_ANAIF_CFG_DSM0_DEM0, 0x40005896
 1209              	.set CYDEV_ANAIF_CFG_DSM0_DEM1, 0x40005897
 1210              	.set CYDEV_ANAIF_CFG_DSM0_TST0, 0x40005898
 1211              	.set CYDEV_ANAIF_CFG_DSM0_TST1, 0x40005899
 1212              	.set CYDEV_ANAIF_CFG_DSM0_BUF0, 0x4000589a
 1213              	.set CYDEV_ANAIF_CFG_DSM0_BUF1, 0x4000589b
 1214              	.set CYDEV_ANAIF_CFG_DSM0_BUF2, 0x4000589c
 1215              	.set CYDEV_ANAIF_CFG_DSM0_BUF3, 0x4000589d
 1216              	.set CYDEV_ANAIF_CFG_DSM0_MISC, 0x4000589e
 1217              	.set CYDEV_ANAIF_CFG_DSM0_RSVD1, 0x4000589f
 1218              	.set CYDEV_ANAIF_CFG_SAR0_BASE, 0x40005900
 1219              	.set CYDEV_ANAIF_CFG_SAR0_SIZE, 0x00000007
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 23


 1220              	.set CYDEV_ANAIF_CFG_SAR0_CSR0, 0x40005900
 1221              	.set CYDEV_ANAIF_CFG_SAR0_CSR1, 0x40005901
 1222              	.set CYDEV_ANAIF_CFG_SAR0_CSR2, 0x40005902
 1223              	.set CYDEV_ANAIF_CFG_SAR0_CSR3, 0x40005903
 1224              	.set CYDEV_ANAIF_CFG_SAR0_CSR4, 0x40005904
 1225              	.set CYDEV_ANAIF_CFG_SAR0_CSR5, 0x40005905
 1226              	.set CYDEV_ANAIF_CFG_SAR0_CSR6, 0x40005906
 1227              	.set CYDEV_ANAIF_CFG_SAR1_BASE, 0x40005908
 1228              	.set CYDEV_ANAIF_CFG_SAR1_SIZE, 0x00000007
 1229              	.set CYDEV_ANAIF_CFG_SAR1_CSR0, 0x40005908
 1230              	.set CYDEV_ANAIF_CFG_SAR1_CSR1, 0x40005909
 1231              	.set CYDEV_ANAIF_CFG_SAR1_CSR2, 0x4000590a
 1232              	.set CYDEV_ANAIF_CFG_SAR1_CSR3, 0x4000590b
 1233              	.set CYDEV_ANAIF_CFG_SAR1_CSR4, 0x4000590c
 1234              	.set CYDEV_ANAIF_CFG_SAR1_CSR5, 0x4000590d
 1235              	.set CYDEV_ANAIF_CFG_SAR1_CSR6, 0x4000590e
 1236              	.set CYDEV_ANAIF_RT_BASE, 0x40005a00
 1237              	.set CYDEV_ANAIF_RT_SIZE, 0x00000162
 1238              	.set CYDEV_ANAIF_RT_SC0_BASE, 0x40005a00
 1239              	.set CYDEV_ANAIF_RT_SC0_SIZE, 0x0000000d
 1240              	.set CYDEV_ANAIF_RT_SC0_SW0, 0x40005a00
 1241              	.set CYDEV_ANAIF_RT_SC0_SW2, 0x40005a02
 1242              	.set CYDEV_ANAIF_RT_SC0_SW3, 0x40005a03
 1243              	.set CYDEV_ANAIF_RT_SC0_SW4, 0x40005a04
 1244              	.set CYDEV_ANAIF_RT_SC0_SW6, 0x40005a06
 1245              	.set CYDEV_ANAIF_RT_SC0_SW7, 0x40005a07
 1246              	.set CYDEV_ANAIF_RT_SC0_SW8, 0x40005a08
 1247              	.set CYDEV_ANAIF_RT_SC0_SW10, 0x40005a0a
 1248              	.set CYDEV_ANAIF_RT_SC0_CLK, 0x40005a0b
 1249              	.set CYDEV_ANAIF_RT_SC0_BST, 0x40005a0c
 1250              	.set CYDEV_ANAIF_RT_SC1_BASE, 0x40005a10
 1251              	.set CYDEV_ANAIF_RT_SC1_SIZE, 0x0000000d
 1252              	.set CYDEV_ANAIF_RT_SC1_SW0, 0x40005a10
 1253              	.set CYDEV_ANAIF_RT_SC1_SW2, 0x40005a12
 1254              	.set CYDEV_ANAIF_RT_SC1_SW3, 0x40005a13
 1255              	.set CYDEV_ANAIF_RT_SC1_SW4, 0x40005a14
 1256              	.set CYDEV_ANAIF_RT_SC1_SW6, 0x40005a16
 1257              	.set CYDEV_ANAIF_RT_SC1_SW7, 0x40005a17
 1258              	.set CYDEV_ANAIF_RT_SC1_SW8, 0x40005a18
 1259              	.set CYDEV_ANAIF_RT_SC1_SW10, 0x40005a1a
 1260              	.set CYDEV_ANAIF_RT_SC1_CLK, 0x40005a1b
 1261              	.set CYDEV_ANAIF_RT_SC1_BST, 0x40005a1c
 1262              	.set CYDEV_ANAIF_RT_SC2_BASE, 0x40005a20
 1263              	.set CYDEV_ANAIF_RT_SC2_SIZE, 0x0000000d
 1264              	.set CYDEV_ANAIF_RT_SC2_SW0, 0x40005a20
 1265              	.set CYDEV_ANAIF_RT_SC2_SW2, 0x40005a22
 1266              	.set CYDEV_ANAIF_RT_SC2_SW3, 0x40005a23
 1267              	.set CYDEV_ANAIF_RT_SC2_SW4, 0x40005a24
 1268              	.set CYDEV_ANAIF_RT_SC2_SW6, 0x40005a26
 1269              	.set CYDEV_ANAIF_RT_SC2_SW7, 0x40005a27
 1270              	.set CYDEV_ANAIF_RT_SC2_SW8, 0x40005a28
 1271              	.set CYDEV_ANAIF_RT_SC2_SW10, 0x40005a2a
 1272              	.set CYDEV_ANAIF_RT_SC2_CLK, 0x40005a2b
 1273              	.set CYDEV_ANAIF_RT_SC2_BST, 0x40005a2c
 1274              	.set CYDEV_ANAIF_RT_SC3_BASE, 0x40005a30
 1275              	.set CYDEV_ANAIF_RT_SC3_SIZE, 0x0000000d
 1276              	.set CYDEV_ANAIF_RT_SC3_SW0, 0x40005a30
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 24


 1277              	.set CYDEV_ANAIF_RT_SC3_SW2, 0x40005a32
 1278              	.set CYDEV_ANAIF_RT_SC3_SW3, 0x40005a33
 1279              	.set CYDEV_ANAIF_RT_SC3_SW4, 0x40005a34
 1280              	.set CYDEV_ANAIF_RT_SC3_SW6, 0x40005a36
 1281              	.set CYDEV_ANAIF_RT_SC3_SW7, 0x40005a37
 1282              	.set CYDEV_ANAIF_RT_SC3_SW8, 0x40005a38
 1283              	.set CYDEV_ANAIF_RT_SC3_SW10, 0x40005a3a
 1284              	.set CYDEV_ANAIF_RT_SC3_CLK, 0x40005a3b
 1285              	.set CYDEV_ANAIF_RT_SC3_BST, 0x40005a3c
 1286              	.set CYDEV_ANAIF_RT_DAC0_BASE, 0x40005a80
 1287              	.set CYDEV_ANAIF_RT_DAC0_SIZE, 0x00000008
 1288              	.set CYDEV_ANAIF_RT_DAC0_SW0, 0x40005a80
 1289              	.set CYDEV_ANAIF_RT_DAC0_SW2, 0x40005a82
 1290              	.set CYDEV_ANAIF_RT_DAC0_SW3, 0x40005a83
 1291              	.set CYDEV_ANAIF_RT_DAC0_SW4, 0x40005a84
 1292              	.set CYDEV_ANAIF_RT_DAC0_STROBE, 0x40005a87
 1293              	.set CYDEV_ANAIF_RT_DAC1_BASE, 0x40005a88
 1294              	.set CYDEV_ANAIF_RT_DAC1_SIZE, 0x00000008
 1295              	.set CYDEV_ANAIF_RT_DAC1_SW0, 0x40005a88
 1296              	.set CYDEV_ANAIF_RT_DAC1_SW2, 0x40005a8a
 1297              	.set CYDEV_ANAIF_RT_DAC1_SW3, 0x40005a8b
 1298              	.set CYDEV_ANAIF_RT_DAC1_SW4, 0x40005a8c
 1299              	.set CYDEV_ANAIF_RT_DAC1_STROBE, 0x40005a8f
 1300              	.set CYDEV_ANAIF_RT_DAC2_BASE, 0x40005a90
 1301              	.set CYDEV_ANAIF_RT_DAC2_SIZE, 0x00000008
 1302              	.set CYDEV_ANAIF_RT_DAC2_SW0, 0x40005a90
 1303              	.set CYDEV_ANAIF_RT_DAC2_SW2, 0x40005a92
 1304              	.set CYDEV_ANAIF_RT_DAC2_SW3, 0x40005a93
 1305              	.set CYDEV_ANAIF_RT_DAC2_SW4, 0x40005a94
 1306              	.set CYDEV_ANAIF_RT_DAC2_STROBE, 0x40005a97
 1307              	.set CYDEV_ANAIF_RT_DAC3_BASE, 0x40005a98
 1308              	.set CYDEV_ANAIF_RT_DAC3_SIZE, 0x00000008
 1309              	.set CYDEV_ANAIF_RT_DAC3_SW0, 0x40005a98
 1310              	.set CYDEV_ANAIF_RT_DAC3_SW2, 0x40005a9a
 1311              	.set CYDEV_ANAIF_RT_DAC3_SW3, 0x40005a9b
 1312              	.set CYDEV_ANAIF_RT_DAC3_SW4, 0x40005a9c
 1313              	.set CYDEV_ANAIF_RT_DAC3_STROBE, 0x40005a9f
 1314              	.set CYDEV_ANAIF_RT_CMP0_BASE, 0x40005ac0
 1315              	.set CYDEV_ANAIF_RT_CMP0_SIZE, 0x00000008
 1316              	.set CYDEV_ANAIF_RT_CMP0_SW0, 0x40005ac0
 1317              	.set CYDEV_ANAIF_RT_CMP0_SW2, 0x40005ac2
 1318              	.set CYDEV_ANAIF_RT_CMP0_SW3, 0x40005ac3
 1319              	.set CYDEV_ANAIF_RT_CMP0_SW4, 0x40005ac4
 1320              	.set CYDEV_ANAIF_RT_CMP0_SW6, 0x40005ac6
 1321              	.set CYDEV_ANAIF_RT_CMP0_CLK, 0x40005ac7
 1322              	.set CYDEV_ANAIF_RT_CMP1_BASE, 0x40005ac8
 1323              	.set CYDEV_ANAIF_RT_CMP1_SIZE, 0x00000008
 1324              	.set CYDEV_ANAIF_RT_CMP1_SW0, 0x40005ac8
 1325              	.set CYDEV_ANAIF_RT_CMP1_SW2, 0x40005aca
 1326              	.set CYDEV_ANAIF_RT_CMP1_SW3, 0x40005acb
 1327              	.set CYDEV_ANAIF_RT_CMP1_SW4, 0x40005acc
 1328              	.set CYDEV_ANAIF_RT_CMP1_SW6, 0x40005ace
 1329              	.set CYDEV_ANAIF_RT_CMP1_CLK, 0x40005acf
 1330              	.set CYDEV_ANAIF_RT_CMP2_BASE, 0x40005ad0
 1331              	.set CYDEV_ANAIF_RT_CMP2_SIZE, 0x00000008
 1332              	.set CYDEV_ANAIF_RT_CMP2_SW0, 0x40005ad0
 1333              	.set CYDEV_ANAIF_RT_CMP2_SW2, 0x40005ad2
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 25


 1334              	.set CYDEV_ANAIF_RT_CMP2_SW3, 0x40005ad3
 1335              	.set CYDEV_ANAIF_RT_CMP2_SW4, 0x40005ad4
 1336              	.set CYDEV_ANAIF_RT_CMP2_SW6, 0x40005ad6
 1337              	.set CYDEV_ANAIF_RT_CMP2_CLK, 0x40005ad7
 1338              	.set CYDEV_ANAIF_RT_CMP3_BASE, 0x40005ad8
 1339              	.set CYDEV_ANAIF_RT_CMP3_SIZE, 0x00000008
 1340              	.set CYDEV_ANAIF_RT_CMP3_SW0, 0x40005ad8
 1341              	.set CYDEV_ANAIF_RT_CMP3_SW2, 0x40005ada
 1342              	.set CYDEV_ANAIF_RT_CMP3_SW3, 0x40005adb
 1343              	.set CYDEV_ANAIF_RT_CMP3_SW4, 0x40005adc
 1344              	.set CYDEV_ANAIF_RT_CMP3_SW6, 0x40005ade
 1345              	.set CYDEV_ANAIF_RT_CMP3_CLK, 0x40005adf
 1346              	.set CYDEV_ANAIF_RT_DSM0_BASE, 0x40005b00
 1347              	.set CYDEV_ANAIF_RT_DSM0_SIZE, 0x00000008
 1348              	.set CYDEV_ANAIF_RT_DSM0_SW0, 0x40005b00
 1349              	.set CYDEV_ANAIF_RT_DSM0_SW2, 0x40005b02
 1350              	.set CYDEV_ANAIF_RT_DSM0_SW3, 0x40005b03
 1351              	.set CYDEV_ANAIF_RT_DSM0_SW4, 0x40005b04
 1352              	.set CYDEV_ANAIF_RT_DSM0_SW6, 0x40005b06
 1353              	.set CYDEV_ANAIF_RT_DSM0_CLK, 0x40005b07
 1354              	.set CYDEV_ANAIF_RT_SAR0_BASE, 0x40005b20
 1355              	.set CYDEV_ANAIF_RT_SAR0_SIZE, 0x00000008
 1356              	.set CYDEV_ANAIF_RT_SAR0_SW0, 0x40005b20
 1357              	.set CYDEV_ANAIF_RT_SAR0_SW2, 0x40005b22
 1358              	.set CYDEV_ANAIF_RT_SAR0_SW3, 0x40005b23
 1359              	.set CYDEV_ANAIF_RT_SAR0_SW4, 0x40005b24
 1360              	.set CYDEV_ANAIF_RT_SAR0_SW6, 0x40005b26
 1361              	.set CYDEV_ANAIF_RT_SAR0_CLK, 0x40005b27
 1362              	.set CYDEV_ANAIF_RT_SAR1_BASE, 0x40005b28
 1363              	.set CYDEV_ANAIF_RT_SAR1_SIZE, 0x00000008
 1364              	.set CYDEV_ANAIF_RT_SAR1_SW0, 0x40005b28
 1365              	.set CYDEV_ANAIF_RT_SAR1_SW2, 0x40005b2a
 1366              	.set CYDEV_ANAIF_RT_SAR1_SW3, 0x40005b2b
 1367              	.set CYDEV_ANAIF_RT_SAR1_SW4, 0x40005b2c
 1368              	.set CYDEV_ANAIF_RT_SAR1_SW6, 0x40005b2e
 1369              	.set CYDEV_ANAIF_RT_SAR1_CLK, 0x40005b2f
 1370              	.set CYDEV_ANAIF_RT_OPAMP0_BASE, 0x40005b40
 1371              	.set CYDEV_ANAIF_RT_OPAMP0_SIZE, 0x00000002
 1372              	.set CYDEV_ANAIF_RT_OPAMP0_MX, 0x40005b40
 1373              	.set CYDEV_ANAIF_RT_OPAMP0_SW, 0x40005b41
 1374              	.set CYDEV_ANAIF_RT_OPAMP1_BASE, 0x40005b42
 1375              	.set CYDEV_ANAIF_RT_OPAMP1_SIZE, 0x00000002
 1376              	.set CYDEV_ANAIF_RT_OPAMP1_MX, 0x40005b42
 1377              	.set CYDEV_ANAIF_RT_OPAMP1_SW, 0x40005b43
 1378              	.set CYDEV_ANAIF_RT_OPAMP2_BASE, 0x40005b44
 1379              	.set CYDEV_ANAIF_RT_OPAMP2_SIZE, 0x00000002
 1380              	.set CYDEV_ANAIF_RT_OPAMP2_MX, 0x40005b44
 1381              	.set CYDEV_ANAIF_RT_OPAMP2_SW, 0x40005b45
 1382              	.set CYDEV_ANAIF_RT_OPAMP3_BASE, 0x40005b46
 1383              	.set CYDEV_ANAIF_RT_OPAMP3_SIZE, 0x00000002
 1384              	.set CYDEV_ANAIF_RT_OPAMP3_MX, 0x40005b46
 1385              	.set CYDEV_ANAIF_RT_OPAMP3_SW, 0x40005b47
 1386              	.set CYDEV_ANAIF_RT_LCDDAC_BASE, 0x40005b50
 1387              	.set CYDEV_ANAIF_RT_LCDDAC_SIZE, 0x00000005
 1388              	.set CYDEV_ANAIF_RT_LCDDAC_SW0, 0x40005b50
 1389              	.set CYDEV_ANAIF_RT_LCDDAC_SW1, 0x40005b51
 1390              	.set CYDEV_ANAIF_RT_LCDDAC_SW2, 0x40005b52
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 26


 1391              	.set CYDEV_ANAIF_RT_LCDDAC_SW3, 0x40005b53
 1392              	.set CYDEV_ANAIF_RT_LCDDAC_SW4, 0x40005b54
 1393              	.set CYDEV_ANAIF_RT_SC_BASE, 0x40005b56
 1394              	.set CYDEV_ANAIF_RT_SC_SIZE, 0x00000001
 1395              	.set CYDEV_ANAIF_RT_SC_MISC, 0x40005b56
 1396              	.set CYDEV_ANAIF_RT_BUS_BASE, 0x40005b58
 1397              	.set CYDEV_ANAIF_RT_BUS_SIZE, 0x00000004
 1398              	.set CYDEV_ANAIF_RT_BUS_SW0, 0x40005b58
 1399              	.set CYDEV_ANAIF_RT_BUS_SW2, 0x40005b5a
 1400              	.set CYDEV_ANAIF_RT_BUS_SW3, 0x40005b5b
 1401              	.set CYDEV_ANAIF_RT_DFT_BASE, 0x40005b5c
 1402              	.set CYDEV_ANAIF_RT_DFT_SIZE, 0x00000006
 1403              	.set CYDEV_ANAIF_RT_DFT_CR0, 0x40005b5c
 1404              	.set CYDEV_ANAIF_RT_DFT_CR1, 0x40005b5d
 1405              	.set CYDEV_ANAIF_RT_DFT_CR2, 0x40005b5e
 1406              	.set CYDEV_ANAIF_RT_DFT_CR3, 0x40005b5f
 1407              	.set CYDEV_ANAIF_RT_DFT_CR4, 0x40005b60
 1408              	.set CYDEV_ANAIF_RT_DFT_CR5, 0x40005b61
 1409              	.set CYDEV_ANAIF_WRK_BASE, 0x40005b80
 1410              	.set CYDEV_ANAIF_WRK_SIZE, 0x00000029
 1411              	.set CYDEV_ANAIF_WRK_DAC0_BASE, 0x40005b80
 1412              	.set CYDEV_ANAIF_WRK_DAC0_SIZE, 0x00000001
 1413              	.set CYDEV_ANAIF_WRK_DAC0_D, 0x40005b80
 1414              	.set CYDEV_ANAIF_WRK_DAC1_BASE, 0x40005b81
 1415              	.set CYDEV_ANAIF_WRK_DAC1_SIZE, 0x00000001
 1416              	.set CYDEV_ANAIF_WRK_DAC1_D, 0x40005b81
 1417              	.set CYDEV_ANAIF_WRK_DAC2_BASE, 0x40005b82
 1418              	.set CYDEV_ANAIF_WRK_DAC2_SIZE, 0x00000001
 1419              	.set CYDEV_ANAIF_WRK_DAC2_D, 0x40005b82
 1420              	.set CYDEV_ANAIF_WRK_DAC3_BASE, 0x40005b83
 1421              	.set CYDEV_ANAIF_WRK_DAC3_SIZE, 0x00000001
 1422              	.set CYDEV_ANAIF_WRK_DAC3_D, 0x40005b83
 1423              	.set CYDEV_ANAIF_WRK_DSM0_BASE, 0x40005b88
 1424              	.set CYDEV_ANAIF_WRK_DSM0_SIZE, 0x00000002
 1425              	.set CYDEV_ANAIF_WRK_DSM0_OUT0, 0x40005b88
 1426              	.set CYDEV_ANAIF_WRK_DSM0_OUT1, 0x40005b89
 1427              	.set CYDEV_ANAIF_WRK_LUT_BASE, 0x40005b90
 1428              	.set CYDEV_ANAIF_WRK_LUT_SIZE, 0x00000005
 1429              	.set CYDEV_ANAIF_WRK_LUT_SR, 0x40005b90
 1430              	.set CYDEV_ANAIF_WRK_LUT_WRK1, 0x40005b91
 1431              	.set CYDEV_ANAIF_WRK_LUT_MSK, 0x40005b92
 1432              	.set CYDEV_ANAIF_WRK_LUT_CLK, 0x40005b93
 1433              	.set CYDEV_ANAIF_WRK_LUT_CPTR, 0x40005b94
 1434              	.set CYDEV_ANAIF_WRK_CMP_BASE, 0x40005b96
 1435              	.set CYDEV_ANAIF_WRK_CMP_SIZE, 0x00000002
 1436              	.set CYDEV_ANAIF_WRK_CMP_WRK, 0x40005b96
 1437              	.set CYDEV_ANAIF_WRK_CMP_TST, 0x40005b97
 1438              	.set CYDEV_ANAIF_WRK_SC_BASE, 0x40005b98
 1439              	.set CYDEV_ANAIF_WRK_SC_SIZE, 0x00000005
 1440              	.set CYDEV_ANAIF_WRK_SC_SR, 0x40005b98
 1441              	.set CYDEV_ANAIF_WRK_SC_WRK1, 0x40005b99
 1442              	.set CYDEV_ANAIF_WRK_SC_MSK, 0x40005b9a
 1443              	.set CYDEV_ANAIF_WRK_SC_CMPINV, 0x40005b9b
 1444              	.set CYDEV_ANAIF_WRK_SC_CPTR, 0x40005b9c
 1445              	.set CYDEV_ANAIF_WRK_SAR0_BASE, 0x40005ba0
 1446              	.set CYDEV_ANAIF_WRK_SAR0_SIZE, 0x00000002
 1447              	.set CYDEV_ANAIF_WRK_SAR0_WRK0, 0x40005ba0
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 27


 1448              	.set CYDEV_ANAIF_WRK_SAR0_WRK1, 0x40005ba1
 1449              	.set CYDEV_ANAIF_WRK_SAR1_BASE, 0x40005ba2
 1450              	.set CYDEV_ANAIF_WRK_SAR1_SIZE, 0x00000002
 1451              	.set CYDEV_ANAIF_WRK_SAR1_WRK0, 0x40005ba2
 1452              	.set CYDEV_ANAIF_WRK_SAR1_WRK1, 0x40005ba3
 1453              	.set CYDEV_ANAIF_WRK_SARS_BASE, 0x40005ba8
 1454              	.set CYDEV_ANAIF_WRK_SARS_SIZE, 0x00000001
 1455              	.set CYDEV_ANAIF_WRK_SARS_SOF, 0x40005ba8
 1456              	.set CYDEV_USB_BASE, 0x40006000
 1457              	.set CYDEV_USB_SIZE, 0x00000300
 1458              	.set CYDEV_USB_EP0_DR0, 0x40006000
 1459              	.set CYDEV_USB_EP0_DR1, 0x40006001
 1460              	.set CYDEV_USB_EP0_DR2, 0x40006002
 1461              	.set CYDEV_USB_EP0_DR3, 0x40006003
 1462              	.set CYDEV_USB_EP0_DR4, 0x40006004
 1463              	.set CYDEV_USB_EP0_DR5, 0x40006005
 1464              	.set CYDEV_USB_EP0_DR6, 0x40006006
 1465              	.set CYDEV_USB_EP0_DR7, 0x40006007
 1466              	.set CYDEV_USB_CR0, 0x40006008
 1467              	.set CYDEV_USB_CR1, 0x40006009
 1468              	.set CYDEV_USB_SIE_EP_INT_EN, 0x4000600a
 1469              	.set CYDEV_USB_SIE_EP_INT_SR, 0x4000600b
 1470              	.set CYDEV_USB_SIE_EP1_BASE, 0x4000600c
 1471              	.set CYDEV_USB_SIE_EP1_SIZE, 0x00000003
 1472              	.set CYDEV_USB_SIE_EP1_CNT0, 0x4000600c
 1473              	.set CYDEV_USB_SIE_EP1_CNT1, 0x4000600d
 1474              	.set CYDEV_USB_SIE_EP1_CR0, 0x4000600e
 1475              	.set CYDEV_USB_USBIO_CR0, 0x40006010
 1476              	.set CYDEV_USB_USBIO_CR1, 0x40006012
 1477              	.set CYDEV_USB_DYN_RECONFIG, 0x40006014
 1478              	.set CYDEV_USB_SOF0, 0x40006018
 1479              	.set CYDEV_USB_SOF1, 0x40006019
 1480              	.set CYDEV_USB_SIE_EP2_BASE, 0x4000601c
 1481              	.set CYDEV_USB_SIE_EP2_SIZE, 0x00000003
 1482              	.set CYDEV_USB_SIE_EP2_CNT0, 0x4000601c
 1483              	.set CYDEV_USB_SIE_EP2_CNT1, 0x4000601d
 1484              	.set CYDEV_USB_SIE_EP2_CR0, 0x4000601e
 1485              	.set CYDEV_USB_EP0_CR, 0x40006028
 1486              	.set CYDEV_USB_EP0_CNT, 0x40006029
 1487              	.set CYDEV_USB_SIE_EP3_BASE, 0x4000602c
 1488              	.set CYDEV_USB_SIE_EP3_SIZE, 0x00000003
 1489              	.set CYDEV_USB_SIE_EP3_CNT0, 0x4000602c
 1490              	.set CYDEV_USB_SIE_EP3_CNT1, 0x4000602d
 1491              	.set CYDEV_USB_SIE_EP3_CR0, 0x4000602e
 1492              	.set CYDEV_USB_SIE_EP4_BASE, 0x4000603c
 1493              	.set CYDEV_USB_SIE_EP4_SIZE, 0x00000003
 1494              	.set CYDEV_USB_SIE_EP4_CNT0, 0x4000603c
 1495              	.set CYDEV_USB_SIE_EP4_CNT1, 0x4000603d
 1496              	.set CYDEV_USB_SIE_EP4_CR0, 0x4000603e
 1497              	.set CYDEV_USB_SIE_EP5_BASE, 0x4000604c
 1498              	.set CYDEV_USB_SIE_EP5_SIZE, 0x00000003
 1499              	.set CYDEV_USB_SIE_EP5_CNT0, 0x4000604c
 1500              	.set CYDEV_USB_SIE_EP5_CNT1, 0x4000604d
 1501              	.set CYDEV_USB_SIE_EP5_CR0, 0x4000604e
 1502              	.set CYDEV_USB_SIE_EP6_BASE, 0x4000605c
 1503              	.set CYDEV_USB_SIE_EP6_SIZE, 0x00000003
 1504              	.set CYDEV_USB_SIE_EP6_CNT0, 0x4000605c
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 28


 1505              	.set CYDEV_USB_SIE_EP6_CNT1, 0x4000605d
 1506              	.set CYDEV_USB_SIE_EP6_CR0, 0x4000605e
 1507              	.set CYDEV_USB_SIE_EP7_BASE, 0x4000606c
 1508              	.set CYDEV_USB_SIE_EP7_SIZE, 0x00000003
 1509              	.set CYDEV_USB_SIE_EP7_CNT0, 0x4000606c
 1510              	.set CYDEV_USB_SIE_EP7_CNT1, 0x4000606d
 1511              	.set CYDEV_USB_SIE_EP7_CR0, 0x4000606e
 1512              	.set CYDEV_USB_SIE_EP8_BASE, 0x4000607c
 1513              	.set CYDEV_USB_SIE_EP8_SIZE, 0x00000003
 1514              	.set CYDEV_USB_SIE_EP8_CNT0, 0x4000607c
 1515              	.set CYDEV_USB_SIE_EP8_CNT1, 0x4000607d
 1516              	.set CYDEV_USB_SIE_EP8_CR0, 0x4000607e
 1517              	.set CYDEV_USB_ARB_EP1_BASE, 0x40006080
 1518              	.set CYDEV_USB_ARB_EP1_SIZE, 0x00000003
 1519              	.set CYDEV_USB_ARB_EP1_CFG, 0x40006080
 1520              	.set CYDEV_USB_ARB_EP1_INT_EN, 0x40006081
 1521              	.set CYDEV_USB_ARB_EP1_SR, 0x40006082
 1522              	.set CYDEV_USB_ARB_RW1_BASE, 0x40006084
 1523              	.set CYDEV_USB_ARB_RW1_SIZE, 0x00000005
 1524              	.set CYDEV_USB_ARB_RW1_WA, 0x40006084
 1525              	.set CYDEV_USB_ARB_RW1_WA_MSB, 0x40006085
 1526              	.set CYDEV_USB_ARB_RW1_RA, 0x40006086
 1527              	.set CYDEV_USB_ARB_RW1_RA_MSB, 0x40006087
 1528              	.set CYDEV_USB_ARB_RW1_DR, 0x40006088
 1529              	.set CYDEV_USB_BUF_SIZE, 0x4000608c
 1530              	.set CYDEV_USB_EP_ACTIVE, 0x4000608e
 1531              	.set CYDEV_USB_EP_TYPE, 0x4000608f
 1532              	.set CYDEV_USB_ARB_EP2_BASE, 0x40006090
 1533              	.set CYDEV_USB_ARB_EP2_SIZE, 0x00000003
 1534              	.set CYDEV_USB_ARB_EP2_CFG, 0x40006090
 1535              	.set CYDEV_USB_ARB_EP2_INT_EN, 0x40006091
 1536              	.set CYDEV_USB_ARB_EP2_SR, 0x40006092
 1537              	.set CYDEV_USB_ARB_RW2_BASE, 0x40006094
 1538              	.set CYDEV_USB_ARB_RW2_SIZE, 0x00000005
 1539              	.set CYDEV_USB_ARB_RW2_WA, 0x40006094
 1540              	.set CYDEV_USB_ARB_RW2_WA_MSB, 0x40006095
 1541              	.set CYDEV_USB_ARB_RW2_RA, 0x40006096
 1542              	.set CYDEV_USB_ARB_RW2_RA_MSB, 0x40006097
 1543              	.set CYDEV_USB_ARB_RW2_DR, 0x40006098
 1544              	.set CYDEV_USB_ARB_CFG, 0x4000609c
 1545              	.set CYDEV_USB_USB_CLK_EN, 0x4000609d
 1546              	.set CYDEV_USB_ARB_INT_EN, 0x4000609e
 1547              	.set CYDEV_USB_ARB_INT_SR, 0x4000609f
 1548              	.set CYDEV_USB_ARB_EP3_BASE, 0x400060a0
 1549              	.set CYDEV_USB_ARB_EP3_SIZE, 0x00000003
 1550              	.set CYDEV_USB_ARB_EP3_CFG, 0x400060a0
 1551              	.set CYDEV_USB_ARB_EP3_INT_EN, 0x400060a1
 1552              	.set CYDEV_USB_ARB_EP3_SR, 0x400060a2
 1553              	.set CYDEV_USB_ARB_RW3_BASE, 0x400060a4
 1554              	.set CYDEV_USB_ARB_RW3_SIZE, 0x00000005
 1555              	.set CYDEV_USB_ARB_RW3_WA, 0x400060a4
 1556              	.set CYDEV_USB_ARB_RW3_WA_MSB, 0x400060a5
 1557              	.set CYDEV_USB_ARB_RW3_RA, 0x400060a6
 1558              	.set CYDEV_USB_ARB_RW3_RA_MSB, 0x400060a7
 1559              	.set CYDEV_USB_ARB_RW3_DR, 0x400060a8
 1560              	.set CYDEV_USB_CWA, 0x400060ac
 1561              	.set CYDEV_USB_CWA_MSB, 0x400060ad
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 29


 1562              	.set CYDEV_USB_ARB_EP4_BASE, 0x400060b0
 1563              	.set CYDEV_USB_ARB_EP4_SIZE, 0x00000003
 1564              	.set CYDEV_USB_ARB_EP4_CFG, 0x400060b0
 1565              	.set CYDEV_USB_ARB_EP4_INT_EN, 0x400060b1
 1566              	.set CYDEV_USB_ARB_EP4_SR, 0x400060b2
 1567              	.set CYDEV_USB_ARB_RW4_BASE, 0x400060b4
 1568              	.set CYDEV_USB_ARB_RW4_SIZE, 0x00000005
 1569              	.set CYDEV_USB_ARB_RW4_WA, 0x400060b4
 1570              	.set CYDEV_USB_ARB_RW4_WA_MSB, 0x400060b5
 1571              	.set CYDEV_USB_ARB_RW4_RA, 0x400060b6
 1572              	.set CYDEV_USB_ARB_RW4_RA_MSB, 0x400060b7
 1573              	.set CYDEV_USB_ARB_RW4_DR, 0x400060b8
 1574              	.set CYDEV_USB_DMA_THRES, 0x400060bc
 1575              	.set CYDEV_USB_DMA_THRES_MSB, 0x400060bd
 1576              	.set CYDEV_USB_ARB_EP5_BASE, 0x400060c0
 1577              	.set CYDEV_USB_ARB_EP5_SIZE, 0x00000003
 1578              	.set CYDEV_USB_ARB_EP5_CFG, 0x400060c0
 1579              	.set CYDEV_USB_ARB_EP5_INT_EN, 0x400060c1
 1580              	.set CYDEV_USB_ARB_EP5_SR, 0x400060c2
 1581              	.set CYDEV_USB_ARB_RW5_BASE, 0x400060c4
 1582              	.set CYDEV_USB_ARB_RW5_SIZE, 0x00000005
 1583              	.set CYDEV_USB_ARB_RW5_WA, 0x400060c4
 1584              	.set CYDEV_USB_ARB_RW5_WA_MSB, 0x400060c5
 1585              	.set CYDEV_USB_ARB_RW5_RA, 0x400060c6
 1586              	.set CYDEV_USB_ARB_RW5_RA_MSB, 0x400060c7
 1587              	.set CYDEV_USB_ARB_RW5_DR, 0x400060c8
 1588              	.set CYDEV_USB_BUS_RST_CNT, 0x400060cc
 1589              	.set CYDEV_USB_ARB_EP6_BASE, 0x400060d0
 1590              	.set CYDEV_USB_ARB_EP6_SIZE, 0x00000003
 1591              	.set CYDEV_USB_ARB_EP6_CFG, 0x400060d0
 1592              	.set CYDEV_USB_ARB_EP6_INT_EN, 0x400060d1
 1593              	.set CYDEV_USB_ARB_EP6_SR, 0x400060d2
 1594              	.set CYDEV_USB_ARB_RW6_BASE, 0x400060d4
 1595              	.set CYDEV_USB_ARB_RW6_SIZE, 0x00000005
 1596              	.set CYDEV_USB_ARB_RW6_WA, 0x400060d4
 1597              	.set CYDEV_USB_ARB_RW6_WA_MSB, 0x400060d5
 1598              	.set CYDEV_USB_ARB_RW6_RA, 0x400060d6
 1599              	.set CYDEV_USB_ARB_RW6_RA_MSB, 0x400060d7
 1600              	.set CYDEV_USB_ARB_RW6_DR, 0x400060d8
 1601              	.set CYDEV_USB_ARB_EP7_BASE, 0x400060e0
 1602              	.set CYDEV_USB_ARB_EP7_SIZE, 0x00000003
 1603              	.set CYDEV_USB_ARB_EP7_CFG, 0x400060e0
 1604              	.set CYDEV_USB_ARB_EP7_INT_EN, 0x400060e1
 1605              	.set CYDEV_USB_ARB_EP7_SR, 0x400060e2
 1606              	.set CYDEV_USB_ARB_RW7_BASE, 0x400060e4
 1607              	.set CYDEV_USB_ARB_RW7_SIZE, 0x00000005
 1608              	.set CYDEV_USB_ARB_RW7_WA, 0x400060e4
 1609              	.set CYDEV_USB_ARB_RW7_WA_MSB, 0x400060e5
 1610              	.set CYDEV_USB_ARB_RW7_RA, 0x400060e6
 1611              	.set CYDEV_USB_ARB_RW7_RA_MSB, 0x400060e7
 1612              	.set CYDEV_USB_ARB_RW7_DR, 0x400060e8
 1613              	.set CYDEV_USB_ARB_EP8_BASE, 0x400060f0
 1614              	.set CYDEV_USB_ARB_EP8_SIZE, 0x00000003
 1615              	.set CYDEV_USB_ARB_EP8_CFG, 0x400060f0
 1616              	.set CYDEV_USB_ARB_EP8_INT_EN, 0x400060f1
 1617              	.set CYDEV_USB_ARB_EP8_SR, 0x400060f2
 1618              	.set CYDEV_USB_ARB_RW8_BASE, 0x400060f4
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 30


 1619              	.set CYDEV_USB_ARB_RW8_SIZE, 0x00000005
 1620              	.set CYDEV_USB_ARB_RW8_WA, 0x400060f4
 1621              	.set CYDEV_USB_ARB_RW8_WA_MSB, 0x400060f5
 1622              	.set CYDEV_USB_ARB_RW8_RA, 0x400060f6
 1623              	.set CYDEV_USB_ARB_RW8_RA_MSB, 0x400060f7
 1624              	.set CYDEV_USB_ARB_RW8_DR, 0x400060f8
 1625              	.set CYDEV_USB_MEM_BASE, 0x40006100
 1626              	.set CYDEV_USB_MEM_SIZE, 0x00000200
 1627              	.set CYDEV_USB_MEM_DATA_MBASE, 0x40006100
 1628              	.set CYDEV_USB_MEM_DATA_MSIZE, 0x00000200
 1629              	.set CYDEV_UWRK_BASE, 0x40006400
 1630              	.set CYDEV_UWRK_SIZE, 0x00000b60
 1631              	.set CYDEV_UWRK_UWRK8_BASE, 0x40006400
 1632              	.set CYDEV_UWRK_UWRK8_SIZE, 0x000003b0
 1633              	.set CYDEV_UWRK_UWRK8_B0_BASE, 0x40006400
 1634              	.set CYDEV_UWRK_UWRK8_B0_SIZE, 0x000000b0
 1635              	.set CYDEV_UWRK_UWRK8_B0_UDB00_A0, 0x40006400
 1636              	.set CYDEV_UWRK_UWRK8_B0_UDB01_A0, 0x40006401
 1637              	.set CYDEV_UWRK_UWRK8_B0_UDB02_A0, 0x40006402
 1638              	.set CYDEV_UWRK_UWRK8_B0_UDB03_A0, 0x40006403
 1639              	.set CYDEV_UWRK_UWRK8_B0_UDB04_A0, 0x40006404
 1640              	.set CYDEV_UWRK_UWRK8_B0_UDB05_A0, 0x40006405
 1641              	.set CYDEV_UWRK_UWRK8_B0_UDB06_A0, 0x40006406
 1642              	.set CYDEV_UWRK_UWRK8_B0_UDB07_A0, 0x40006407
 1643              	.set CYDEV_UWRK_UWRK8_B0_UDB08_A0, 0x40006408
 1644              	.set CYDEV_UWRK_UWRK8_B0_UDB09_A0, 0x40006409
 1645              	.set CYDEV_UWRK_UWRK8_B0_UDB10_A0, 0x4000640a
 1646              	.set CYDEV_UWRK_UWRK8_B0_UDB11_A0, 0x4000640b
 1647              	.set CYDEV_UWRK_UWRK8_B0_UDB12_A0, 0x4000640c
 1648              	.set CYDEV_UWRK_UWRK8_B0_UDB13_A0, 0x4000640d
 1649              	.set CYDEV_UWRK_UWRK8_B0_UDB14_A0, 0x4000640e
 1650              	.set CYDEV_UWRK_UWRK8_B0_UDB15_A0, 0x4000640f
 1651              	.set CYDEV_UWRK_UWRK8_B0_UDB00_A1, 0x40006410
 1652              	.set CYDEV_UWRK_UWRK8_B0_UDB01_A1, 0x40006411
 1653              	.set CYDEV_UWRK_UWRK8_B0_UDB02_A1, 0x40006412
 1654              	.set CYDEV_UWRK_UWRK8_B0_UDB03_A1, 0x40006413
 1655              	.set CYDEV_UWRK_UWRK8_B0_UDB04_A1, 0x40006414
 1656              	.set CYDEV_UWRK_UWRK8_B0_UDB05_A1, 0x40006415
 1657              	.set CYDEV_UWRK_UWRK8_B0_UDB06_A1, 0x40006416
 1658              	.set CYDEV_UWRK_UWRK8_B0_UDB07_A1, 0x40006417
 1659              	.set CYDEV_UWRK_UWRK8_B0_UDB08_A1, 0x40006418
 1660              	.set CYDEV_UWRK_UWRK8_B0_UDB09_A1, 0x40006419
 1661              	.set CYDEV_UWRK_UWRK8_B0_UDB10_A1, 0x4000641a
 1662              	.set CYDEV_UWRK_UWRK8_B0_UDB11_A1, 0x4000641b
 1663              	.set CYDEV_UWRK_UWRK8_B0_UDB12_A1, 0x4000641c
 1664              	.set CYDEV_UWRK_UWRK8_B0_UDB13_A1, 0x4000641d
 1665              	.set CYDEV_UWRK_UWRK8_B0_UDB14_A1, 0x4000641e
 1666              	.set CYDEV_UWRK_UWRK8_B0_UDB15_A1, 0x4000641f
 1667              	.set CYDEV_UWRK_UWRK8_B0_UDB00_D0, 0x40006420
 1668              	.set CYDEV_UWRK_UWRK8_B0_UDB01_D0, 0x40006421
 1669              	.set CYDEV_UWRK_UWRK8_B0_UDB02_D0, 0x40006422
 1670              	.set CYDEV_UWRK_UWRK8_B0_UDB03_D0, 0x40006423
 1671              	.set CYDEV_UWRK_UWRK8_B0_UDB04_D0, 0x40006424
 1672              	.set CYDEV_UWRK_UWRK8_B0_UDB05_D0, 0x40006425
 1673              	.set CYDEV_UWRK_UWRK8_B0_UDB06_D0, 0x40006426
 1674              	.set CYDEV_UWRK_UWRK8_B0_UDB07_D0, 0x40006427
 1675              	.set CYDEV_UWRK_UWRK8_B0_UDB08_D0, 0x40006428
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 31


 1676              	.set CYDEV_UWRK_UWRK8_B0_UDB09_D0, 0x40006429
 1677              	.set CYDEV_UWRK_UWRK8_B0_UDB10_D0, 0x4000642a
 1678              	.set CYDEV_UWRK_UWRK8_B0_UDB11_D0, 0x4000642b
 1679              	.set CYDEV_UWRK_UWRK8_B0_UDB12_D0, 0x4000642c
 1680              	.set CYDEV_UWRK_UWRK8_B0_UDB13_D0, 0x4000642d
 1681              	.set CYDEV_UWRK_UWRK8_B0_UDB14_D0, 0x4000642e
 1682              	.set CYDEV_UWRK_UWRK8_B0_UDB15_D0, 0x4000642f
 1683              	.set CYDEV_UWRK_UWRK8_B0_UDB00_D1, 0x40006430
 1684              	.set CYDEV_UWRK_UWRK8_B0_UDB01_D1, 0x40006431
 1685              	.set CYDEV_UWRK_UWRK8_B0_UDB02_D1, 0x40006432
 1686              	.set CYDEV_UWRK_UWRK8_B0_UDB03_D1, 0x40006433
 1687              	.set CYDEV_UWRK_UWRK8_B0_UDB04_D1, 0x40006434
 1688              	.set CYDEV_UWRK_UWRK8_B0_UDB05_D1, 0x40006435
 1689              	.set CYDEV_UWRK_UWRK8_B0_UDB06_D1, 0x40006436
 1690              	.set CYDEV_UWRK_UWRK8_B0_UDB07_D1, 0x40006437
 1691              	.set CYDEV_UWRK_UWRK8_B0_UDB08_D1, 0x40006438
 1692              	.set CYDEV_UWRK_UWRK8_B0_UDB09_D1, 0x40006439
 1693              	.set CYDEV_UWRK_UWRK8_B0_UDB10_D1, 0x4000643a
 1694              	.set CYDEV_UWRK_UWRK8_B0_UDB11_D1, 0x4000643b
 1695              	.set CYDEV_UWRK_UWRK8_B0_UDB12_D1, 0x4000643c
 1696              	.set CYDEV_UWRK_UWRK8_B0_UDB13_D1, 0x4000643d
 1697              	.set CYDEV_UWRK_UWRK8_B0_UDB14_D1, 0x4000643e
 1698              	.set CYDEV_UWRK_UWRK8_B0_UDB15_D1, 0x4000643f
 1699              	.set CYDEV_UWRK_UWRK8_B0_UDB00_F0, 0x40006440
 1700              	.set CYDEV_UWRK_UWRK8_B0_UDB01_F0, 0x40006441
 1701              	.set CYDEV_UWRK_UWRK8_B0_UDB02_F0, 0x40006442
 1702              	.set CYDEV_UWRK_UWRK8_B0_UDB03_F0, 0x40006443
 1703              	.set CYDEV_UWRK_UWRK8_B0_UDB04_F0, 0x40006444
 1704              	.set CYDEV_UWRK_UWRK8_B0_UDB05_F0, 0x40006445
 1705              	.set CYDEV_UWRK_UWRK8_B0_UDB06_F0, 0x40006446
 1706              	.set CYDEV_UWRK_UWRK8_B0_UDB07_F0, 0x40006447
 1707              	.set CYDEV_UWRK_UWRK8_B0_UDB08_F0, 0x40006448
 1708              	.set CYDEV_UWRK_UWRK8_B0_UDB09_F0, 0x40006449
 1709              	.set CYDEV_UWRK_UWRK8_B0_UDB10_F0, 0x4000644a
 1710              	.set CYDEV_UWRK_UWRK8_B0_UDB11_F0, 0x4000644b
 1711              	.set CYDEV_UWRK_UWRK8_B0_UDB12_F0, 0x4000644c
 1712              	.set CYDEV_UWRK_UWRK8_B0_UDB13_F0, 0x4000644d
 1713              	.set CYDEV_UWRK_UWRK8_B0_UDB14_F0, 0x4000644e
 1714              	.set CYDEV_UWRK_UWRK8_B0_UDB15_F0, 0x4000644f
 1715              	.set CYDEV_UWRK_UWRK8_B0_UDB00_F1, 0x40006450
 1716              	.set CYDEV_UWRK_UWRK8_B0_UDB01_F1, 0x40006451
 1717              	.set CYDEV_UWRK_UWRK8_B0_UDB02_F1, 0x40006452
 1718              	.set CYDEV_UWRK_UWRK8_B0_UDB03_F1, 0x40006453
 1719              	.set CYDEV_UWRK_UWRK8_B0_UDB04_F1, 0x40006454
 1720              	.set CYDEV_UWRK_UWRK8_B0_UDB05_F1, 0x40006455
 1721              	.set CYDEV_UWRK_UWRK8_B0_UDB06_F1, 0x40006456
 1722              	.set CYDEV_UWRK_UWRK8_B0_UDB07_F1, 0x40006457
 1723              	.set CYDEV_UWRK_UWRK8_B0_UDB08_F1, 0x40006458
 1724              	.set CYDEV_UWRK_UWRK8_B0_UDB09_F1, 0x40006459
 1725              	.set CYDEV_UWRK_UWRK8_B0_UDB10_F1, 0x4000645a
 1726              	.set CYDEV_UWRK_UWRK8_B0_UDB11_F1, 0x4000645b
 1727              	.set CYDEV_UWRK_UWRK8_B0_UDB12_F1, 0x4000645c
 1728              	.set CYDEV_UWRK_UWRK8_B0_UDB13_F1, 0x4000645d
 1729              	.set CYDEV_UWRK_UWRK8_B0_UDB14_F1, 0x4000645e
 1730              	.set CYDEV_UWRK_UWRK8_B0_UDB15_F1, 0x4000645f
 1731              	.set CYDEV_UWRK_UWRK8_B0_UDB00_ST, 0x40006460
 1732              	.set CYDEV_UWRK_UWRK8_B0_UDB01_ST, 0x40006461
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 32


 1733              	.set CYDEV_UWRK_UWRK8_B0_UDB02_ST, 0x40006462
 1734              	.set CYDEV_UWRK_UWRK8_B0_UDB03_ST, 0x40006463
 1735              	.set CYDEV_UWRK_UWRK8_B0_UDB04_ST, 0x40006464
 1736              	.set CYDEV_UWRK_UWRK8_B0_UDB05_ST, 0x40006465
 1737              	.set CYDEV_UWRK_UWRK8_B0_UDB06_ST, 0x40006466
 1738              	.set CYDEV_UWRK_UWRK8_B0_UDB07_ST, 0x40006467
 1739              	.set CYDEV_UWRK_UWRK8_B0_UDB08_ST, 0x40006468
 1740              	.set CYDEV_UWRK_UWRK8_B0_UDB09_ST, 0x40006469
 1741              	.set CYDEV_UWRK_UWRK8_B0_UDB10_ST, 0x4000646a
 1742              	.set CYDEV_UWRK_UWRK8_B0_UDB11_ST, 0x4000646b
 1743              	.set CYDEV_UWRK_UWRK8_B0_UDB12_ST, 0x4000646c
 1744              	.set CYDEV_UWRK_UWRK8_B0_UDB13_ST, 0x4000646d
 1745              	.set CYDEV_UWRK_UWRK8_B0_UDB14_ST, 0x4000646e
 1746              	.set CYDEV_UWRK_UWRK8_B0_UDB15_ST, 0x4000646f
 1747              	.set CYDEV_UWRK_UWRK8_B0_UDB00_CTL, 0x40006470
 1748              	.set CYDEV_UWRK_UWRK8_B0_UDB01_CTL, 0x40006471
 1749              	.set CYDEV_UWRK_UWRK8_B0_UDB02_CTL, 0x40006472
 1750              	.set CYDEV_UWRK_UWRK8_B0_UDB03_CTL, 0x40006473
 1751              	.set CYDEV_UWRK_UWRK8_B0_UDB04_CTL, 0x40006474
 1752              	.set CYDEV_UWRK_UWRK8_B0_UDB05_CTL, 0x40006475
 1753              	.set CYDEV_UWRK_UWRK8_B0_UDB06_CTL, 0x40006476
 1754              	.set CYDEV_UWRK_UWRK8_B0_UDB07_CTL, 0x40006477
 1755              	.set CYDEV_UWRK_UWRK8_B0_UDB08_CTL, 0x40006478
 1756              	.set CYDEV_UWRK_UWRK8_B0_UDB09_CTL, 0x40006479
 1757              	.set CYDEV_UWRK_UWRK8_B0_UDB10_CTL, 0x4000647a
 1758              	.set CYDEV_UWRK_UWRK8_B0_UDB11_CTL, 0x4000647b
 1759              	.set CYDEV_UWRK_UWRK8_B0_UDB12_CTL, 0x4000647c
 1760              	.set CYDEV_UWRK_UWRK8_B0_UDB13_CTL, 0x4000647d
 1761              	.set CYDEV_UWRK_UWRK8_B0_UDB14_CTL, 0x4000647e
 1762              	.set CYDEV_UWRK_UWRK8_B0_UDB15_CTL, 0x4000647f
 1763              	.set CYDEV_UWRK_UWRK8_B0_UDB00_MSK, 0x40006480
 1764              	.set CYDEV_UWRK_UWRK8_B0_UDB01_MSK, 0x40006481
 1765              	.set CYDEV_UWRK_UWRK8_B0_UDB02_MSK, 0x40006482
 1766              	.set CYDEV_UWRK_UWRK8_B0_UDB03_MSK, 0x40006483
 1767              	.set CYDEV_UWRK_UWRK8_B0_UDB04_MSK, 0x40006484
 1768              	.set CYDEV_UWRK_UWRK8_B0_UDB05_MSK, 0x40006485
 1769              	.set CYDEV_UWRK_UWRK8_B0_UDB06_MSK, 0x40006486
 1770              	.set CYDEV_UWRK_UWRK8_B0_UDB07_MSK, 0x40006487
 1771              	.set CYDEV_UWRK_UWRK8_B0_UDB08_MSK, 0x40006488
 1772              	.set CYDEV_UWRK_UWRK8_B0_UDB09_MSK, 0x40006489
 1773              	.set CYDEV_UWRK_UWRK8_B0_UDB10_MSK, 0x4000648a
 1774              	.set CYDEV_UWRK_UWRK8_B0_UDB11_MSK, 0x4000648b
 1775              	.set CYDEV_UWRK_UWRK8_B0_UDB12_MSK, 0x4000648c
 1776              	.set CYDEV_UWRK_UWRK8_B0_UDB13_MSK, 0x4000648d
 1777              	.set CYDEV_UWRK_UWRK8_B0_UDB14_MSK, 0x4000648e
 1778              	.set CYDEV_UWRK_UWRK8_B0_UDB15_MSK, 0x4000648f
 1779              	.set CYDEV_UWRK_UWRK8_B0_UDB00_ACTL, 0x40006490
 1780              	.set CYDEV_UWRK_UWRK8_B0_UDB01_ACTL, 0x40006491
 1781              	.set CYDEV_UWRK_UWRK8_B0_UDB02_ACTL, 0x40006492
 1782              	.set CYDEV_UWRK_UWRK8_B0_UDB03_ACTL, 0x40006493
 1783              	.set CYDEV_UWRK_UWRK8_B0_UDB04_ACTL, 0x40006494
 1784              	.set CYDEV_UWRK_UWRK8_B0_UDB05_ACTL, 0x40006495
 1785              	.set CYDEV_UWRK_UWRK8_B0_UDB06_ACTL, 0x40006496
 1786              	.set CYDEV_UWRK_UWRK8_B0_UDB07_ACTL, 0x40006497
 1787              	.set CYDEV_UWRK_UWRK8_B0_UDB08_ACTL, 0x40006498
 1788              	.set CYDEV_UWRK_UWRK8_B0_UDB09_ACTL, 0x40006499
 1789              	.set CYDEV_UWRK_UWRK8_B0_UDB10_ACTL, 0x4000649a
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 33


 1790              	.set CYDEV_UWRK_UWRK8_B0_UDB11_ACTL, 0x4000649b
 1791              	.set CYDEV_UWRK_UWRK8_B0_UDB12_ACTL, 0x4000649c
 1792              	.set CYDEV_UWRK_UWRK8_B0_UDB13_ACTL, 0x4000649d
 1793              	.set CYDEV_UWRK_UWRK8_B0_UDB14_ACTL, 0x4000649e
 1794              	.set CYDEV_UWRK_UWRK8_B0_UDB15_ACTL, 0x4000649f
 1795              	.set CYDEV_UWRK_UWRK8_B0_UDB00_MC, 0x400064a0
 1796              	.set CYDEV_UWRK_UWRK8_B0_UDB01_MC, 0x400064a1
 1797              	.set CYDEV_UWRK_UWRK8_B0_UDB02_MC, 0x400064a2
 1798              	.set CYDEV_UWRK_UWRK8_B0_UDB03_MC, 0x400064a3
 1799              	.set CYDEV_UWRK_UWRK8_B0_UDB04_MC, 0x400064a4
 1800              	.set CYDEV_UWRK_UWRK8_B0_UDB05_MC, 0x400064a5
 1801              	.set CYDEV_UWRK_UWRK8_B0_UDB06_MC, 0x400064a6
 1802              	.set CYDEV_UWRK_UWRK8_B0_UDB07_MC, 0x400064a7
 1803              	.set CYDEV_UWRK_UWRK8_B0_UDB08_MC, 0x400064a8
 1804              	.set CYDEV_UWRK_UWRK8_B0_UDB09_MC, 0x400064a9
 1805              	.set CYDEV_UWRK_UWRK8_B0_UDB10_MC, 0x400064aa
 1806              	.set CYDEV_UWRK_UWRK8_B0_UDB11_MC, 0x400064ab
 1807              	.set CYDEV_UWRK_UWRK8_B0_UDB12_MC, 0x400064ac
 1808              	.set CYDEV_UWRK_UWRK8_B0_UDB13_MC, 0x400064ad
 1809              	.set CYDEV_UWRK_UWRK8_B0_UDB14_MC, 0x400064ae
 1810              	.set CYDEV_UWRK_UWRK8_B0_UDB15_MC, 0x400064af
 1811              	.set CYDEV_UWRK_UWRK8_B1_BASE, 0x40006500
 1812              	.set CYDEV_UWRK_UWRK8_B1_SIZE, 0x000000b0
 1813              	.set CYDEV_UWRK_UWRK8_B1_UDB04_A0, 0x40006504
 1814              	.set CYDEV_UWRK_UWRK8_B1_UDB05_A0, 0x40006505
 1815              	.set CYDEV_UWRK_UWRK8_B1_UDB06_A0, 0x40006506
 1816              	.set CYDEV_UWRK_UWRK8_B1_UDB07_A0, 0x40006507
 1817              	.set CYDEV_UWRK_UWRK8_B1_UDB08_A0, 0x40006508
 1818              	.set CYDEV_UWRK_UWRK8_B1_UDB09_A0, 0x40006509
 1819              	.set CYDEV_UWRK_UWRK8_B1_UDB10_A0, 0x4000650a
 1820              	.set CYDEV_UWRK_UWRK8_B1_UDB11_A0, 0x4000650b
 1821              	.set CYDEV_UWRK_UWRK8_B1_UDB04_A1, 0x40006514
 1822              	.set CYDEV_UWRK_UWRK8_B1_UDB05_A1, 0x40006515
 1823              	.set CYDEV_UWRK_UWRK8_B1_UDB06_A1, 0x40006516
 1824              	.set CYDEV_UWRK_UWRK8_B1_UDB07_A1, 0x40006517
 1825              	.set CYDEV_UWRK_UWRK8_B1_UDB08_A1, 0x40006518
 1826              	.set CYDEV_UWRK_UWRK8_B1_UDB09_A1, 0x40006519
 1827              	.set CYDEV_UWRK_UWRK8_B1_UDB10_A1, 0x4000651a
 1828              	.set CYDEV_UWRK_UWRK8_B1_UDB11_A1, 0x4000651b
 1829              	.set CYDEV_UWRK_UWRK8_B1_UDB04_D0, 0x40006524
 1830              	.set CYDEV_UWRK_UWRK8_B1_UDB05_D0, 0x40006525
 1831              	.set CYDEV_UWRK_UWRK8_B1_UDB06_D0, 0x40006526
 1832              	.set CYDEV_UWRK_UWRK8_B1_UDB07_D0, 0x40006527
 1833              	.set CYDEV_UWRK_UWRK8_B1_UDB08_D0, 0x40006528
 1834              	.set CYDEV_UWRK_UWRK8_B1_UDB09_D0, 0x40006529
 1835              	.set CYDEV_UWRK_UWRK8_B1_UDB10_D0, 0x4000652a
 1836              	.set CYDEV_UWRK_UWRK8_B1_UDB11_D0, 0x4000652b
 1837              	.set CYDEV_UWRK_UWRK8_B1_UDB04_D1, 0x40006534
 1838              	.set CYDEV_UWRK_UWRK8_B1_UDB05_D1, 0x40006535
 1839              	.set CYDEV_UWRK_UWRK8_B1_UDB06_D1, 0x40006536
 1840              	.set CYDEV_UWRK_UWRK8_B1_UDB07_D1, 0x40006537
 1841              	.set CYDEV_UWRK_UWRK8_B1_UDB08_D1, 0x40006538
 1842              	.set CYDEV_UWRK_UWRK8_B1_UDB09_D1, 0x40006539
 1843              	.set CYDEV_UWRK_UWRK8_B1_UDB10_D1, 0x4000653a
 1844              	.set CYDEV_UWRK_UWRK8_B1_UDB11_D1, 0x4000653b
 1845              	.set CYDEV_UWRK_UWRK8_B1_UDB04_F0, 0x40006544
 1846              	.set CYDEV_UWRK_UWRK8_B1_UDB05_F0, 0x40006545
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 34


 1847              	.set CYDEV_UWRK_UWRK8_B1_UDB06_F0, 0x40006546
 1848              	.set CYDEV_UWRK_UWRK8_B1_UDB07_F0, 0x40006547
 1849              	.set CYDEV_UWRK_UWRK8_B1_UDB08_F0, 0x40006548
 1850              	.set CYDEV_UWRK_UWRK8_B1_UDB09_F0, 0x40006549
 1851              	.set CYDEV_UWRK_UWRK8_B1_UDB10_F0, 0x4000654a
 1852              	.set CYDEV_UWRK_UWRK8_B1_UDB11_F0, 0x4000654b
 1853              	.set CYDEV_UWRK_UWRK8_B1_UDB04_F1, 0x40006554
 1854              	.set CYDEV_UWRK_UWRK8_B1_UDB05_F1, 0x40006555
 1855              	.set CYDEV_UWRK_UWRK8_B1_UDB06_F1, 0x40006556
 1856              	.set CYDEV_UWRK_UWRK8_B1_UDB07_F1, 0x40006557
 1857              	.set CYDEV_UWRK_UWRK8_B1_UDB08_F1, 0x40006558
 1858              	.set CYDEV_UWRK_UWRK8_B1_UDB09_F1, 0x40006559
 1859              	.set CYDEV_UWRK_UWRK8_B1_UDB10_F1, 0x4000655a
 1860              	.set CYDEV_UWRK_UWRK8_B1_UDB11_F1, 0x4000655b
 1861              	.set CYDEV_UWRK_UWRK8_B1_UDB04_ST, 0x40006564
 1862              	.set CYDEV_UWRK_UWRK8_B1_UDB05_ST, 0x40006565
 1863              	.set CYDEV_UWRK_UWRK8_B1_UDB06_ST, 0x40006566
 1864              	.set CYDEV_UWRK_UWRK8_B1_UDB07_ST, 0x40006567
 1865              	.set CYDEV_UWRK_UWRK8_B1_UDB08_ST, 0x40006568
 1866              	.set CYDEV_UWRK_UWRK8_B1_UDB09_ST, 0x40006569
 1867              	.set CYDEV_UWRK_UWRK8_B1_UDB10_ST, 0x4000656a
 1868              	.set CYDEV_UWRK_UWRK8_B1_UDB11_ST, 0x4000656b
 1869              	.set CYDEV_UWRK_UWRK8_B1_UDB04_CTL, 0x40006574
 1870              	.set CYDEV_UWRK_UWRK8_B1_UDB05_CTL, 0x40006575
 1871              	.set CYDEV_UWRK_UWRK8_B1_UDB06_CTL, 0x40006576
 1872              	.set CYDEV_UWRK_UWRK8_B1_UDB07_CTL, 0x40006577
 1873              	.set CYDEV_UWRK_UWRK8_B1_UDB08_CTL, 0x40006578
 1874              	.set CYDEV_UWRK_UWRK8_B1_UDB09_CTL, 0x40006579
 1875              	.set CYDEV_UWRK_UWRK8_B1_UDB10_CTL, 0x4000657a
 1876              	.set CYDEV_UWRK_UWRK8_B1_UDB11_CTL, 0x4000657b
 1877              	.set CYDEV_UWRK_UWRK8_B1_UDB04_MSK, 0x40006584
 1878              	.set CYDEV_UWRK_UWRK8_B1_UDB05_MSK, 0x40006585
 1879              	.set CYDEV_UWRK_UWRK8_B1_UDB06_MSK, 0x40006586
 1880              	.set CYDEV_UWRK_UWRK8_B1_UDB07_MSK, 0x40006587
 1881              	.set CYDEV_UWRK_UWRK8_B1_UDB08_MSK, 0x40006588
 1882              	.set CYDEV_UWRK_UWRK8_B1_UDB09_MSK, 0x40006589
 1883              	.set CYDEV_UWRK_UWRK8_B1_UDB10_MSK, 0x4000658a
 1884              	.set CYDEV_UWRK_UWRK8_B1_UDB11_MSK, 0x4000658b
 1885              	.set CYDEV_UWRK_UWRK8_B1_UDB04_ACTL, 0x40006594
 1886              	.set CYDEV_UWRK_UWRK8_B1_UDB05_ACTL, 0x40006595
 1887              	.set CYDEV_UWRK_UWRK8_B1_UDB06_ACTL, 0x40006596
 1888              	.set CYDEV_UWRK_UWRK8_B1_UDB07_ACTL, 0x40006597
 1889              	.set CYDEV_UWRK_UWRK8_B1_UDB08_ACTL, 0x40006598
 1890              	.set CYDEV_UWRK_UWRK8_B1_UDB09_ACTL, 0x40006599
 1891              	.set CYDEV_UWRK_UWRK8_B1_UDB10_ACTL, 0x4000659a
 1892              	.set CYDEV_UWRK_UWRK8_B1_UDB11_ACTL, 0x4000659b
 1893              	.set CYDEV_UWRK_UWRK8_B1_UDB04_MC, 0x400065a4
 1894              	.set CYDEV_UWRK_UWRK8_B1_UDB05_MC, 0x400065a5
 1895              	.set CYDEV_UWRK_UWRK8_B1_UDB06_MC, 0x400065a6
 1896              	.set CYDEV_UWRK_UWRK8_B1_UDB07_MC, 0x400065a7
 1897              	.set CYDEV_UWRK_UWRK8_B1_UDB08_MC, 0x400065a8
 1898              	.set CYDEV_UWRK_UWRK8_B1_UDB09_MC, 0x400065a9
 1899              	.set CYDEV_UWRK_UWRK8_B1_UDB10_MC, 0x400065aa
 1900              	.set CYDEV_UWRK_UWRK8_B1_UDB11_MC, 0x400065ab
 1901              	.set CYDEV_UWRK_UWRK16_BASE, 0x40006800
 1902              	.set CYDEV_UWRK_UWRK16_SIZE, 0x00000760
 1903              	.set CYDEV_UWRK_UWRK16_CAT_BASE, 0x40006800
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 35


 1904              	.set CYDEV_UWRK_UWRK16_CAT_SIZE, 0x00000760
 1905              	.set CYDEV_UWRK_UWRK16_CAT_B0_BASE, 0x40006800
 1906              	.set CYDEV_UWRK_UWRK16_CAT_B0_SIZE, 0x00000160
 1907              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1, 0x40006800
 1908              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1, 0x40006802
 1909              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1, 0x40006804
 1910              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1, 0x40006806
 1911              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1, 0x40006808
 1912              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1, 0x4000680a
 1913              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1, 0x4000680c
 1914              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1, 0x4000680e
 1915              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1, 0x40006810
 1916              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1, 0x40006812
 1917              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1, 0x40006814
 1918              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1, 0x40006816
 1919              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1, 0x40006818
 1920              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1, 0x4000681a
 1921              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1, 0x4000681c
 1922              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1, 0x4000681e
 1923              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1, 0x40006840
 1924              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1, 0x40006842
 1925              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1, 0x40006844
 1926              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1, 0x40006846
 1927              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1, 0x40006848
 1928              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1, 0x4000684a
 1929              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1, 0x4000684c
 1930              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1, 0x4000684e
 1931              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1, 0x40006850
 1932              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1, 0x40006852
 1933              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1, 0x40006854
 1934              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1, 0x40006856
 1935              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1, 0x40006858
 1936              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1, 0x4000685a
 1937              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1, 0x4000685c
 1938              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1, 0x4000685e
 1939              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1, 0x40006880
 1940              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1, 0x40006882
 1941              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1, 0x40006884
 1942              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1, 0x40006886
 1943              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1, 0x40006888
 1944              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1, 0x4000688a
 1945              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1, 0x4000688c
 1946              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1, 0x4000688e
 1947              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1, 0x40006890
 1948              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1, 0x40006892
 1949              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1, 0x40006894
 1950              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1, 0x40006896
 1951              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1, 0x40006898
 1952              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1, 0x4000689a
 1953              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1, 0x4000689c
 1954              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1, 0x4000689e
 1955              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL, 0x400068c0
 1956              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL, 0x400068c2
 1957              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL, 0x400068c4
 1958              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL, 0x400068c6
 1959              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL, 0x400068c8
 1960              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL, 0x400068ca
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 36


 1961              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL, 0x400068cc
 1962              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL, 0x400068ce
 1963              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL, 0x400068d0
 1964              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL, 0x400068d2
 1965              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL, 0x400068d4
 1966              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL, 0x400068d6
 1967              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL, 0x400068d8
 1968              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL, 0x400068da
 1969              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL, 0x400068dc
 1970              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL, 0x400068de
 1971              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL, 0x40006900
 1972              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL, 0x40006902
 1973              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL, 0x40006904
 1974              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL, 0x40006906
 1975              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL, 0x40006908
 1976              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL, 0x4000690a
 1977              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL, 0x4000690c
 1978              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL, 0x4000690e
 1979              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL, 0x40006910
 1980              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL, 0x40006912
 1981              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL, 0x40006914
 1982              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL, 0x40006916
 1983              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL, 0x40006918
 1984              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL, 0x4000691a
 1985              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL, 0x4000691c
 1986              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL, 0x4000691e
 1987              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00, 0x40006940
 1988              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00, 0x40006942
 1989              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00, 0x40006944
 1990              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00, 0x40006946
 1991              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00, 0x40006948
 1992              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00, 0x4000694a
 1993              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00, 0x4000694c
 1994              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00, 0x4000694e
 1995              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00, 0x40006950
 1996              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00, 0x40006952
 1997              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00, 0x40006954
 1998              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00, 0x40006956
 1999              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00, 0x40006958
 2000              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00, 0x4000695a
 2001              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00, 0x4000695c
 2002              	.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00, 0x4000695e
 2003              	.set CYDEV_UWRK_UWRK16_CAT_B1_BASE, 0x40006a00
 2004              	.set CYDEV_UWRK_UWRK16_CAT_B1_SIZE, 0x00000160
 2005              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1, 0x40006a08
 2006              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1, 0x40006a0a
 2007              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1, 0x40006a0c
 2008              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1, 0x40006a0e
 2009              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1, 0x40006a10
 2010              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1, 0x40006a12
 2011              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1, 0x40006a14
 2012              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1, 0x40006a16
 2013              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1, 0x40006a48
 2014              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1, 0x40006a4a
 2015              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1, 0x40006a4c
 2016              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1, 0x40006a4e
 2017              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1, 0x40006a50
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 37


 2018              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1, 0x40006a52
 2019              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1, 0x40006a54
 2020              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1, 0x40006a56
 2021              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1, 0x40006a88
 2022              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1, 0x40006a8a
 2023              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1, 0x40006a8c
 2024              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1, 0x40006a8e
 2025              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1, 0x40006a90
 2026              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1, 0x40006a92
 2027              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1, 0x40006a94
 2028              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1, 0x40006a96
 2029              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL, 0x40006ac8
 2030              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL, 0x40006aca
 2031              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL, 0x40006acc
 2032              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL, 0x40006ace
 2033              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL, 0x40006ad0
 2034              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL, 0x40006ad2
 2035              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL, 0x40006ad4
 2036              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL, 0x40006ad6
 2037              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL, 0x40006b08
 2038              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL, 0x40006b0a
 2039              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL, 0x40006b0c
 2040              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL, 0x40006b0e
 2041              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL, 0x40006b10
 2042              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL, 0x40006b12
 2043              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL, 0x40006b14
 2044              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL, 0x40006b16
 2045              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00, 0x40006b48
 2046              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00, 0x40006b4a
 2047              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00, 0x40006b4c
 2048              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00, 0x40006b4e
 2049              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00, 0x40006b50
 2050              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00, 0x40006b52
 2051              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00, 0x40006b54
 2052              	.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00, 0x40006b56
 2053              	.set CYDEV_UWRK_UWRK16_DEF_BASE, 0x40006800
 2054              	.set CYDEV_UWRK_UWRK16_DEF_SIZE, 0x0000075e
 2055              	.set CYDEV_UWRK_UWRK16_DEF_B0_BASE, 0x40006800
 2056              	.set CYDEV_UWRK_UWRK16_DEF_B0_SIZE, 0x0000015e
 2057              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0, 0x40006800
 2058              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0, 0x40006802
 2059              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0, 0x40006804
 2060              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0, 0x40006806
 2061              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0, 0x40006808
 2062              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0, 0x4000680a
 2063              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0, 0x4000680c
 2064              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0, 0x4000680e
 2065              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0, 0x40006810
 2066              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0, 0x40006812
 2067              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0, 0x40006814
 2068              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0, 0x40006816
 2069              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0, 0x40006818
 2070              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0, 0x4000681a
 2071              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0, 0x4000681c
 2072              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1, 0x40006820
 2073              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1, 0x40006822
 2074              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1, 0x40006824
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 38


 2075              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1, 0x40006826
 2076              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1, 0x40006828
 2077              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1, 0x4000682a
 2078              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1, 0x4000682c
 2079              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1, 0x4000682e
 2080              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1, 0x40006830
 2081              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1, 0x40006832
 2082              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1, 0x40006834
 2083              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1, 0x40006836
 2084              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1, 0x40006838
 2085              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1, 0x4000683a
 2086              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1, 0x4000683c
 2087              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0, 0x40006840
 2088              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0, 0x40006842
 2089              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0, 0x40006844
 2090              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0, 0x40006846
 2091              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0, 0x40006848
 2092              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0, 0x4000684a
 2093              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0, 0x4000684c
 2094              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0, 0x4000684e
 2095              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0, 0x40006850
 2096              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0, 0x40006852
 2097              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0, 0x40006854
 2098              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0, 0x40006856
 2099              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0, 0x40006858
 2100              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0, 0x4000685a
 2101              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0, 0x4000685c
 2102              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1, 0x40006860
 2103              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1, 0x40006862
 2104              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1, 0x40006864
 2105              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1, 0x40006866
 2106              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1, 0x40006868
 2107              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1, 0x4000686a
 2108              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1, 0x4000686c
 2109              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1, 0x4000686e
 2110              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1, 0x40006870
 2111              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1, 0x40006872
 2112              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1, 0x40006874
 2113              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1, 0x40006876
 2114              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1, 0x40006878
 2115              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1, 0x4000687a
 2116              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1, 0x4000687c
 2117              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0, 0x40006880
 2118              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0, 0x40006882
 2119              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0, 0x40006884
 2120              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0, 0x40006886
 2121              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0, 0x40006888
 2122              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0, 0x4000688a
 2123              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0, 0x4000688c
 2124              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0, 0x4000688e
 2125              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0, 0x40006890
 2126              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0, 0x40006892
 2127              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0, 0x40006894
 2128              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0, 0x40006896
 2129              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0, 0x40006898
 2130              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0, 0x4000689a
 2131              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0, 0x4000689c
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 39


 2132              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1, 0x400068a0
 2133              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1, 0x400068a2
 2134              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1, 0x400068a4
 2135              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1, 0x400068a6
 2136              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1, 0x400068a8
 2137              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1, 0x400068aa
 2138              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1, 0x400068ac
 2139              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1, 0x400068ae
 2140              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1, 0x400068b0
 2141              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1, 0x400068b2
 2142              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1, 0x400068b4
 2143              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1, 0x400068b6
 2144              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1, 0x400068b8
 2145              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1, 0x400068ba
 2146              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1, 0x400068bc
 2147              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST, 0x400068c0
 2148              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST, 0x400068c2
 2149              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST, 0x400068c4
 2150              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST, 0x400068c6
 2151              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST, 0x400068c8
 2152              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST, 0x400068ca
 2153              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST, 0x400068cc
 2154              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST, 0x400068ce
 2155              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST, 0x400068d0
 2156              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST, 0x400068d2
 2157              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST, 0x400068d4
 2158              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST, 0x400068d6
 2159              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST, 0x400068d8
 2160              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST, 0x400068da
 2161              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST, 0x400068dc
 2162              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL, 0x400068e0
 2163              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL, 0x400068e2
 2164              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL, 0x400068e4
 2165              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL, 0x400068e6
 2166              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL, 0x400068e8
 2167              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL, 0x400068ea
 2168              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL, 0x400068ec
 2169              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL, 0x400068ee
 2170              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL, 0x400068f0
 2171              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL, 0x400068f2
 2172              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL, 0x400068f4
 2173              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL, 0x400068f6
 2174              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL, 0x400068f8
 2175              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL, 0x400068fa
 2176              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL, 0x400068fc
 2177              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK, 0x40006900
 2178              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK, 0x40006902
 2179              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK, 0x40006904
 2180              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK, 0x40006906
 2181              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK, 0x40006908
 2182              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK, 0x4000690a
 2183              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK, 0x4000690c
 2184              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK, 0x4000690e
 2185              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK, 0x40006910
 2186              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK, 0x40006912
 2187              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK, 0x40006914
 2188              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK, 0x40006916
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 40


 2189              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK, 0x40006918
 2190              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK, 0x4000691a
 2191              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK, 0x4000691c
 2192              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL, 0x40006920
 2193              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL, 0x40006922
 2194              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL, 0x40006924
 2195              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL, 0x40006926
 2196              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL, 0x40006928
 2197              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL, 0x4000692a
 2198              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL, 0x4000692c
 2199              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL, 0x4000692e
 2200              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL, 0x40006930
 2201              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL, 0x40006932
 2202              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL, 0x40006934
 2203              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL, 0x40006936
 2204              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL, 0x40006938
 2205              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL, 0x4000693a
 2206              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL, 0x4000693c
 2207              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC, 0x40006940
 2208              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC, 0x40006942
 2209              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC, 0x40006944
 2210              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC, 0x40006946
 2211              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC, 0x40006948
 2212              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC, 0x4000694a
 2213              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC, 0x4000694c
 2214              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC, 0x4000694e
 2215              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC, 0x40006950
 2216              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC, 0x40006952
 2217              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC, 0x40006954
 2218              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC, 0x40006956
 2219              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC, 0x40006958
 2220              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC, 0x4000695a
 2221              	.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC, 0x4000695c
 2222              	.set CYDEV_UWRK_UWRK16_DEF_B1_BASE, 0x40006a00
 2223              	.set CYDEV_UWRK_UWRK16_DEF_B1_SIZE, 0x0000015e
 2224              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0, 0x40006a08
 2225              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0, 0x40006a0a
 2226              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0, 0x40006a0c
 2227              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0, 0x40006a0e
 2228              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0, 0x40006a10
 2229              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0, 0x40006a12
 2230              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0, 0x40006a14
 2231              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0, 0x40006a16
 2232              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1, 0x40006a28
 2233              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1, 0x40006a2a
 2234              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1, 0x40006a2c
 2235              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1, 0x40006a2e
 2236              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1, 0x40006a30
 2237              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1, 0x40006a32
 2238              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1, 0x40006a34
 2239              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1, 0x40006a36
 2240              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0, 0x40006a48
 2241              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0, 0x40006a4a
 2242              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0, 0x40006a4c
 2243              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0, 0x40006a4e
 2244              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0, 0x40006a50
 2245              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0, 0x40006a52
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 41


 2246              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0, 0x40006a54
 2247              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0, 0x40006a56
 2248              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1, 0x40006a68
 2249              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1, 0x40006a6a
 2250              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1, 0x40006a6c
 2251              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1, 0x40006a6e
 2252              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1, 0x40006a70
 2253              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1, 0x40006a72
 2254              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1, 0x40006a74
 2255              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1, 0x40006a76
 2256              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0, 0x40006a88
 2257              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0, 0x40006a8a
 2258              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0, 0x40006a8c
 2259              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0, 0x40006a8e
 2260              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0, 0x40006a90
 2261              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0, 0x40006a92
 2262              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0, 0x40006a94
 2263              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0, 0x40006a96
 2264              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1, 0x40006aa8
 2265              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1, 0x40006aaa
 2266              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1, 0x40006aac
 2267              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1, 0x40006aae
 2268              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1, 0x40006ab0
 2269              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1, 0x40006ab2
 2270              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1, 0x40006ab4
 2271              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1, 0x40006ab6
 2272              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST, 0x40006ac8
 2273              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST, 0x40006aca
 2274              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST, 0x40006acc
 2275              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST, 0x40006ace
 2276              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST, 0x40006ad0
 2277              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST, 0x40006ad2
 2278              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST, 0x40006ad4
 2279              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST, 0x40006ad6
 2280              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL, 0x40006ae8
 2281              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL, 0x40006aea
 2282              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL, 0x40006aec
 2283              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL, 0x40006aee
 2284              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL, 0x40006af0
 2285              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL, 0x40006af2
 2286              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL, 0x40006af4
 2287              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL, 0x40006af6
 2288              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK, 0x40006b08
 2289              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK, 0x40006b0a
 2290              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK, 0x40006b0c
 2291              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK, 0x40006b0e
 2292              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK, 0x40006b10
 2293              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK, 0x40006b12
 2294              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK, 0x40006b14
 2295              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK, 0x40006b16
 2296              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL, 0x40006b28
 2297              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL, 0x40006b2a
 2298              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL, 0x40006b2c
 2299              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL, 0x40006b2e
 2300              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL, 0x40006b30
 2301              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL, 0x40006b32
 2302              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL, 0x40006b34
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 42


 2303              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL, 0x40006b36
 2304              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC, 0x40006b48
 2305              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC, 0x40006b4a
 2306              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC, 0x40006b4c
 2307              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC, 0x40006b4e
 2308              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC, 0x40006b50
 2309              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC, 0x40006b52
 2310              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC, 0x40006b54
 2311              	.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC, 0x40006b56
 2312              	.set CYDEV_PHUB_BASE, 0x40007000
 2313              	.set CYDEV_PHUB_SIZE, 0x00000c00
 2314              	.set CYDEV_PHUB_CFG, 0x40007000
 2315              	.set CYDEV_PHUB_ERR, 0x40007004
 2316              	.set CYDEV_PHUB_ERR_ADR, 0x40007008
 2317              	.set CYDEV_PHUB_CH0_BASE, 0x40007010
 2318              	.set CYDEV_PHUB_CH0_SIZE, 0x0000000c
 2319              	.set CYDEV_PHUB_CH0_BASIC_CFG, 0x40007010
 2320              	.set CYDEV_PHUB_CH0_ACTION, 0x40007014
 2321              	.set CYDEV_PHUB_CH0_BASIC_STATUS, 0x40007018
 2322              	.set CYDEV_PHUB_CH1_BASE, 0x40007020
 2323              	.set CYDEV_PHUB_CH1_SIZE, 0x0000000c
 2324              	.set CYDEV_PHUB_CH1_BASIC_CFG, 0x40007020
 2325              	.set CYDEV_PHUB_CH1_ACTION, 0x40007024
 2326              	.set CYDEV_PHUB_CH1_BASIC_STATUS, 0x40007028
 2327              	.set CYDEV_PHUB_CH2_BASE, 0x40007030
 2328              	.set CYDEV_PHUB_CH2_SIZE, 0x0000000c
 2329              	.set CYDEV_PHUB_CH2_BASIC_CFG, 0x40007030
 2330              	.set CYDEV_PHUB_CH2_ACTION, 0x40007034
 2331              	.set CYDEV_PHUB_CH2_BASIC_STATUS, 0x40007038
 2332              	.set CYDEV_PHUB_CH3_BASE, 0x40007040
 2333              	.set CYDEV_PHUB_CH3_SIZE, 0x0000000c
 2334              	.set CYDEV_PHUB_CH3_BASIC_CFG, 0x40007040
 2335              	.set CYDEV_PHUB_CH3_ACTION, 0x40007044
 2336              	.set CYDEV_PHUB_CH3_BASIC_STATUS, 0x40007048
 2337              	.set CYDEV_PHUB_CH4_BASE, 0x40007050
 2338              	.set CYDEV_PHUB_CH4_SIZE, 0x0000000c
 2339              	.set CYDEV_PHUB_CH4_BASIC_CFG, 0x40007050
 2340              	.set CYDEV_PHUB_CH4_ACTION, 0x40007054
 2341              	.set CYDEV_PHUB_CH4_BASIC_STATUS, 0x40007058
 2342              	.set CYDEV_PHUB_CH5_BASE, 0x40007060
 2343              	.set CYDEV_PHUB_CH5_SIZE, 0x0000000c
 2344              	.set CYDEV_PHUB_CH5_BASIC_CFG, 0x40007060
 2345              	.set CYDEV_PHUB_CH5_ACTION, 0x40007064
 2346              	.set CYDEV_PHUB_CH5_BASIC_STATUS, 0x40007068
 2347              	.set CYDEV_PHUB_CH6_BASE, 0x40007070
 2348              	.set CYDEV_PHUB_CH6_SIZE, 0x0000000c
 2349              	.set CYDEV_PHUB_CH6_BASIC_CFG, 0x40007070
 2350              	.set CYDEV_PHUB_CH6_ACTION, 0x40007074
 2351              	.set CYDEV_PHUB_CH6_BASIC_STATUS, 0x40007078
 2352              	.set CYDEV_PHUB_CH7_BASE, 0x40007080
 2353              	.set CYDEV_PHUB_CH7_SIZE, 0x0000000c
 2354              	.set CYDEV_PHUB_CH7_BASIC_CFG, 0x40007080
 2355              	.set CYDEV_PHUB_CH7_ACTION, 0x40007084
 2356              	.set CYDEV_PHUB_CH7_BASIC_STATUS, 0x40007088
 2357              	.set CYDEV_PHUB_CH8_BASE, 0x40007090
 2358              	.set CYDEV_PHUB_CH8_SIZE, 0x0000000c
 2359              	.set CYDEV_PHUB_CH8_BASIC_CFG, 0x40007090
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 43


 2360              	.set CYDEV_PHUB_CH8_ACTION, 0x40007094
 2361              	.set CYDEV_PHUB_CH8_BASIC_STATUS, 0x40007098
 2362              	.set CYDEV_PHUB_CH9_BASE, 0x400070a0
 2363              	.set CYDEV_PHUB_CH9_SIZE, 0x0000000c
 2364              	.set CYDEV_PHUB_CH9_BASIC_CFG, 0x400070a0
 2365              	.set CYDEV_PHUB_CH9_ACTION, 0x400070a4
 2366              	.set CYDEV_PHUB_CH9_BASIC_STATUS, 0x400070a8
 2367              	.set CYDEV_PHUB_CH10_BASE, 0x400070b0
 2368              	.set CYDEV_PHUB_CH10_SIZE, 0x0000000c
 2369              	.set CYDEV_PHUB_CH10_BASIC_CFG, 0x400070b0
 2370              	.set CYDEV_PHUB_CH10_ACTION, 0x400070b4
 2371              	.set CYDEV_PHUB_CH10_BASIC_STATUS, 0x400070b8
 2372              	.set CYDEV_PHUB_CH11_BASE, 0x400070c0
 2373              	.set CYDEV_PHUB_CH11_SIZE, 0x0000000c
 2374              	.set CYDEV_PHUB_CH11_BASIC_CFG, 0x400070c0
 2375              	.set CYDEV_PHUB_CH11_ACTION, 0x400070c4
 2376              	.set CYDEV_PHUB_CH11_BASIC_STATUS, 0x400070c8
 2377              	.set CYDEV_PHUB_CH12_BASE, 0x400070d0
 2378              	.set CYDEV_PHUB_CH12_SIZE, 0x0000000c
 2379              	.set CYDEV_PHUB_CH12_BASIC_CFG, 0x400070d0
 2380              	.set CYDEV_PHUB_CH12_ACTION, 0x400070d4
 2381              	.set CYDEV_PHUB_CH12_BASIC_STATUS, 0x400070d8
 2382              	.set CYDEV_PHUB_CH13_BASE, 0x400070e0
 2383              	.set CYDEV_PHUB_CH13_SIZE, 0x0000000c
 2384              	.set CYDEV_PHUB_CH13_BASIC_CFG, 0x400070e0
 2385              	.set CYDEV_PHUB_CH13_ACTION, 0x400070e4
 2386              	.set CYDEV_PHUB_CH13_BASIC_STATUS, 0x400070e8
 2387              	.set CYDEV_PHUB_CH14_BASE, 0x400070f0
 2388              	.set CYDEV_PHUB_CH14_SIZE, 0x0000000c
 2389              	.set CYDEV_PHUB_CH14_BASIC_CFG, 0x400070f0
 2390              	.set CYDEV_PHUB_CH14_ACTION, 0x400070f4
 2391              	.set CYDEV_PHUB_CH14_BASIC_STATUS, 0x400070f8
 2392              	.set CYDEV_PHUB_CH15_BASE, 0x40007100
 2393              	.set CYDEV_PHUB_CH15_SIZE, 0x0000000c
 2394              	.set CYDEV_PHUB_CH15_BASIC_CFG, 0x40007100
 2395              	.set CYDEV_PHUB_CH15_ACTION, 0x40007104
 2396              	.set CYDEV_PHUB_CH15_BASIC_STATUS, 0x40007108
 2397              	.set CYDEV_PHUB_CH16_BASE, 0x40007110
 2398              	.set CYDEV_PHUB_CH16_SIZE, 0x0000000c
 2399              	.set CYDEV_PHUB_CH16_BASIC_CFG, 0x40007110
 2400              	.set CYDEV_PHUB_CH16_ACTION, 0x40007114
 2401              	.set CYDEV_PHUB_CH16_BASIC_STATUS, 0x40007118
 2402              	.set CYDEV_PHUB_CH17_BASE, 0x40007120
 2403              	.set CYDEV_PHUB_CH17_SIZE, 0x0000000c
 2404              	.set CYDEV_PHUB_CH17_BASIC_CFG, 0x40007120
 2405              	.set CYDEV_PHUB_CH17_ACTION, 0x40007124
 2406              	.set CYDEV_PHUB_CH17_BASIC_STATUS, 0x40007128
 2407              	.set CYDEV_PHUB_CH18_BASE, 0x40007130
 2408              	.set CYDEV_PHUB_CH18_SIZE, 0x0000000c
 2409              	.set CYDEV_PHUB_CH18_BASIC_CFG, 0x40007130
 2410              	.set CYDEV_PHUB_CH18_ACTION, 0x40007134
 2411              	.set CYDEV_PHUB_CH18_BASIC_STATUS, 0x40007138
 2412              	.set CYDEV_PHUB_CH19_BASE, 0x40007140
 2413              	.set CYDEV_PHUB_CH19_SIZE, 0x0000000c
 2414              	.set CYDEV_PHUB_CH19_BASIC_CFG, 0x40007140
 2415              	.set CYDEV_PHUB_CH19_ACTION, 0x40007144
 2416              	.set CYDEV_PHUB_CH19_BASIC_STATUS, 0x40007148
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 44


 2417              	.set CYDEV_PHUB_CH20_BASE, 0x40007150
 2418              	.set CYDEV_PHUB_CH20_SIZE, 0x0000000c
 2419              	.set CYDEV_PHUB_CH20_BASIC_CFG, 0x40007150
 2420              	.set CYDEV_PHUB_CH20_ACTION, 0x40007154
 2421              	.set CYDEV_PHUB_CH20_BASIC_STATUS, 0x40007158
 2422              	.set CYDEV_PHUB_CH21_BASE, 0x40007160
 2423              	.set CYDEV_PHUB_CH21_SIZE, 0x0000000c
 2424              	.set CYDEV_PHUB_CH21_BASIC_CFG, 0x40007160
 2425              	.set CYDEV_PHUB_CH21_ACTION, 0x40007164
 2426              	.set CYDEV_PHUB_CH21_BASIC_STATUS, 0x40007168
 2427              	.set CYDEV_PHUB_CH22_BASE, 0x40007170
 2428              	.set CYDEV_PHUB_CH22_SIZE, 0x0000000c
 2429              	.set CYDEV_PHUB_CH22_BASIC_CFG, 0x40007170
 2430              	.set CYDEV_PHUB_CH22_ACTION, 0x40007174
 2431              	.set CYDEV_PHUB_CH22_BASIC_STATUS, 0x40007178
 2432              	.set CYDEV_PHUB_CH23_BASE, 0x40007180
 2433              	.set CYDEV_PHUB_CH23_SIZE, 0x0000000c
 2434              	.set CYDEV_PHUB_CH23_BASIC_CFG, 0x40007180
 2435              	.set CYDEV_PHUB_CH23_ACTION, 0x40007184
 2436              	.set CYDEV_PHUB_CH23_BASIC_STATUS, 0x40007188
 2437              	.set CYDEV_PHUB_CFGMEM0_BASE, 0x40007600
 2438              	.set CYDEV_PHUB_CFGMEM0_SIZE, 0x00000008
 2439              	.set CYDEV_PHUB_CFGMEM0_CFG0, 0x40007600
 2440              	.set CYDEV_PHUB_CFGMEM0_CFG1, 0x40007604
 2441              	.set CYDEV_PHUB_CFGMEM1_BASE, 0x40007608
 2442              	.set CYDEV_PHUB_CFGMEM1_SIZE, 0x00000008
 2443              	.set CYDEV_PHUB_CFGMEM1_CFG0, 0x40007608
 2444              	.set CYDEV_PHUB_CFGMEM1_CFG1, 0x4000760c
 2445              	.set CYDEV_PHUB_CFGMEM2_BASE, 0x40007610
 2446              	.set CYDEV_PHUB_CFGMEM2_SIZE, 0x00000008
 2447              	.set CYDEV_PHUB_CFGMEM2_CFG0, 0x40007610
 2448              	.set CYDEV_PHUB_CFGMEM2_CFG1, 0x40007614
 2449              	.set CYDEV_PHUB_CFGMEM3_BASE, 0x40007618
 2450              	.set CYDEV_PHUB_CFGMEM3_SIZE, 0x00000008
 2451              	.set CYDEV_PHUB_CFGMEM3_CFG0, 0x40007618
 2452              	.set CYDEV_PHUB_CFGMEM3_CFG1, 0x4000761c
 2453              	.set CYDEV_PHUB_CFGMEM4_BASE, 0x40007620
 2454              	.set CYDEV_PHUB_CFGMEM4_SIZE, 0x00000008
 2455              	.set CYDEV_PHUB_CFGMEM4_CFG0, 0x40007620
 2456              	.set CYDEV_PHUB_CFGMEM4_CFG1, 0x40007624
 2457              	.set CYDEV_PHUB_CFGMEM5_BASE, 0x40007628
 2458              	.set CYDEV_PHUB_CFGMEM5_SIZE, 0x00000008
 2459              	.set CYDEV_PHUB_CFGMEM5_CFG0, 0x40007628
 2460              	.set CYDEV_PHUB_CFGMEM5_CFG1, 0x4000762c
 2461              	.set CYDEV_PHUB_CFGMEM6_BASE, 0x40007630
 2462              	.set CYDEV_PHUB_CFGMEM6_SIZE, 0x00000008
 2463              	.set CYDEV_PHUB_CFGMEM6_CFG0, 0x40007630
 2464              	.set CYDEV_PHUB_CFGMEM6_CFG1, 0x40007634
 2465              	.set CYDEV_PHUB_CFGMEM7_BASE, 0x40007638
 2466              	.set CYDEV_PHUB_CFGMEM7_SIZE, 0x00000008
 2467              	.set CYDEV_PHUB_CFGMEM7_CFG0, 0x40007638
 2468              	.set CYDEV_PHUB_CFGMEM7_CFG1, 0x4000763c
 2469              	.set CYDEV_PHUB_CFGMEM8_BASE, 0x40007640
 2470              	.set CYDEV_PHUB_CFGMEM8_SIZE, 0x00000008
 2471              	.set CYDEV_PHUB_CFGMEM8_CFG0, 0x40007640
 2472              	.set CYDEV_PHUB_CFGMEM8_CFG1, 0x40007644
 2473              	.set CYDEV_PHUB_CFGMEM9_BASE, 0x40007648
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 45


 2474              	.set CYDEV_PHUB_CFGMEM9_SIZE, 0x00000008
 2475              	.set CYDEV_PHUB_CFGMEM9_CFG0, 0x40007648
 2476              	.set CYDEV_PHUB_CFGMEM9_CFG1, 0x4000764c
 2477              	.set CYDEV_PHUB_CFGMEM10_BASE, 0x40007650
 2478              	.set CYDEV_PHUB_CFGMEM10_SIZE, 0x00000008
 2479              	.set CYDEV_PHUB_CFGMEM10_CFG0, 0x40007650
 2480              	.set CYDEV_PHUB_CFGMEM10_CFG1, 0x40007654
 2481              	.set CYDEV_PHUB_CFGMEM11_BASE, 0x40007658
 2482              	.set CYDEV_PHUB_CFGMEM11_SIZE, 0x00000008
 2483              	.set CYDEV_PHUB_CFGMEM11_CFG0, 0x40007658
 2484              	.set CYDEV_PHUB_CFGMEM11_CFG1, 0x4000765c
 2485              	.set CYDEV_PHUB_CFGMEM12_BASE, 0x40007660
 2486              	.set CYDEV_PHUB_CFGMEM12_SIZE, 0x00000008
 2487              	.set CYDEV_PHUB_CFGMEM12_CFG0, 0x40007660
 2488              	.set CYDEV_PHUB_CFGMEM12_CFG1, 0x40007664
 2489              	.set CYDEV_PHUB_CFGMEM13_BASE, 0x40007668
 2490              	.set CYDEV_PHUB_CFGMEM13_SIZE, 0x00000008
 2491              	.set CYDEV_PHUB_CFGMEM13_CFG0, 0x40007668
 2492              	.set CYDEV_PHUB_CFGMEM13_CFG1, 0x4000766c
 2493              	.set CYDEV_PHUB_CFGMEM14_BASE, 0x40007670
 2494              	.set CYDEV_PHUB_CFGMEM14_SIZE, 0x00000008
 2495              	.set CYDEV_PHUB_CFGMEM14_CFG0, 0x40007670
 2496              	.set CYDEV_PHUB_CFGMEM14_CFG1, 0x40007674
 2497              	.set CYDEV_PHUB_CFGMEM15_BASE, 0x40007678
 2498              	.set CYDEV_PHUB_CFGMEM15_SIZE, 0x00000008
 2499              	.set CYDEV_PHUB_CFGMEM15_CFG0, 0x40007678
 2500              	.set CYDEV_PHUB_CFGMEM15_CFG1, 0x4000767c
 2501              	.set CYDEV_PHUB_CFGMEM16_BASE, 0x40007680
 2502              	.set CYDEV_PHUB_CFGMEM16_SIZE, 0x00000008
 2503              	.set CYDEV_PHUB_CFGMEM16_CFG0, 0x40007680
 2504              	.set CYDEV_PHUB_CFGMEM16_CFG1, 0x40007684
 2505              	.set CYDEV_PHUB_CFGMEM17_BASE, 0x40007688
 2506              	.set CYDEV_PHUB_CFGMEM17_SIZE, 0x00000008
 2507              	.set CYDEV_PHUB_CFGMEM17_CFG0, 0x40007688
 2508              	.set CYDEV_PHUB_CFGMEM17_CFG1, 0x4000768c
 2509              	.set CYDEV_PHUB_CFGMEM18_BASE, 0x40007690
 2510              	.set CYDEV_PHUB_CFGMEM18_SIZE, 0x00000008
 2511              	.set CYDEV_PHUB_CFGMEM18_CFG0, 0x40007690
 2512              	.set CYDEV_PHUB_CFGMEM18_CFG1, 0x40007694
 2513              	.set CYDEV_PHUB_CFGMEM19_BASE, 0x40007698
 2514              	.set CYDEV_PHUB_CFGMEM19_SIZE, 0x00000008
 2515              	.set CYDEV_PHUB_CFGMEM19_CFG0, 0x40007698
 2516              	.set CYDEV_PHUB_CFGMEM19_CFG1, 0x4000769c
 2517              	.set CYDEV_PHUB_CFGMEM20_BASE, 0x400076a0
 2518              	.set CYDEV_PHUB_CFGMEM20_SIZE, 0x00000008
 2519              	.set CYDEV_PHUB_CFGMEM20_CFG0, 0x400076a0
 2520              	.set CYDEV_PHUB_CFGMEM20_CFG1, 0x400076a4
 2521              	.set CYDEV_PHUB_CFGMEM21_BASE, 0x400076a8
 2522              	.set CYDEV_PHUB_CFGMEM21_SIZE, 0x00000008
 2523              	.set CYDEV_PHUB_CFGMEM21_CFG0, 0x400076a8
 2524              	.set CYDEV_PHUB_CFGMEM21_CFG1, 0x400076ac
 2525              	.set CYDEV_PHUB_CFGMEM22_BASE, 0x400076b0
 2526              	.set CYDEV_PHUB_CFGMEM22_SIZE, 0x00000008
 2527              	.set CYDEV_PHUB_CFGMEM22_CFG0, 0x400076b0
 2528              	.set CYDEV_PHUB_CFGMEM22_CFG1, 0x400076b4
 2529              	.set CYDEV_PHUB_CFGMEM23_BASE, 0x400076b8
 2530              	.set CYDEV_PHUB_CFGMEM23_SIZE, 0x00000008
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 46


 2531              	.set CYDEV_PHUB_CFGMEM23_CFG0, 0x400076b8
 2532              	.set CYDEV_PHUB_CFGMEM23_CFG1, 0x400076bc
 2533              	.set CYDEV_PHUB_TDMEM0_BASE, 0x40007800
 2534              	.set CYDEV_PHUB_TDMEM0_SIZE, 0x00000008
 2535              	.set CYDEV_PHUB_TDMEM0_ORIG_TD0, 0x40007800
 2536              	.set CYDEV_PHUB_TDMEM0_ORIG_TD1, 0x40007804
 2537              	.set CYDEV_PHUB_TDMEM1_BASE, 0x40007808
 2538              	.set CYDEV_PHUB_TDMEM1_SIZE, 0x00000008
 2539              	.set CYDEV_PHUB_TDMEM1_ORIG_TD0, 0x40007808
 2540              	.set CYDEV_PHUB_TDMEM1_ORIG_TD1, 0x4000780c
 2541              	.set CYDEV_PHUB_TDMEM2_BASE, 0x40007810
 2542              	.set CYDEV_PHUB_TDMEM2_SIZE, 0x00000008
 2543              	.set CYDEV_PHUB_TDMEM2_ORIG_TD0, 0x40007810
 2544              	.set CYDEV_PHUB_TDMEM2_ORIG_TD1, 0x40007814
 2545              	.set CYDEV_PHUB_TDMEM3_BASE, 0x40007818
 2546              	.set CYDEV_PHUB_TDMEM3_SIZE, 0x00000008
 2547              	.set CYDEV_PHUB_TDMEM3_ORIG_TD0, 0x40007818
 2548              	.set CYDEV_PHUB_TDMEM3_ORIG_TD1, 0x4000781c
 2549              	.set CYDEV_PHUB_TDMEM4_BASE, 0x40007820
 2550              	.set CYDEV_PHUB_TDMEM4_SIZE, 0x00000008
 2551              	.set CYDEV_PHUB_TDMEM4_ORIG_TD0, 0x40007820
 2552              	.set CYDEV_PHUB_TDMEM4_ORIG_TD1, 0x40007824
 2553              	.set CYDEV_PHUB_TDMEM5_BASE, 0x40007828
 2554              	.set CYDEV_PHUB_TDMEM5_SIZE, 0x00000008
 2555              	.set CYDEV_PHUB_TDMEM5_ORIG_TD0, 0x40007828
 2556              	.set CYDEV_PHUB_TDMEM5_ORIG_TD1, 0x4000782c
 2557              	.set CYDEV_PHUB_TDMEM6_BASE, 0x40007830
 2558              	.set CYDEV_PHUB_TDMEM6_SIZE, 0x00000008
 2559              	.set CYDEV_PHUB_TDMEM6_ORIG_TD0, 0x40007830
 2560              	.set CYDEV_PHUB_TDMEM6_ORIG_TD1, 0x40007834
 2561              	.set CYDEV_PHUB_TDMEM7_BASE, 0x40007838
 2562              	.set CYDEV_PHUB_TDMEM7_SIZE, 0x00000008
 2563              	.set CYDEV_PHUB_TDMEM7_ORIG_TD0, 0x40007838
 2564              	.set CYDEV_PHUB_TDMEM7_ORIG_TD1, 0x4000783c
 2565              	.set CYDEV_PHUB_TDMEM8_BASE, 0x40007840
 2566              	.set CYDEV_PHUB_TDMEM8_SIZE, 0x00000008
 2567              	.set CYDEV_PHUB_TDMEM8_ORIG_TD0, 0x40007840
 2568              	.set CYDEV_PHUB_TDMEM8_ORIG_TD1, 0x40007844
 2569              	.set CYDEV_PHUB_TDMEM9_BASE, 0x40007848
 2570              	.set CYDEV_PHUB_TDMEM9_SIZE, 0x00000008
 2571              	.set CYDEV_PHUB_TDMEM9_ORIG_TD0, 0x40007848
 2572              	.set CYDEV_PHUB_TDMEM9_ORIG_TD1, 0x4000784c
 2573              	.set CYDEV_PHUB_TDMEM10_BASE, 0x40007850
 2574              	.set CYDEV_PHUB_TDMEM10_SIZE, 0x00000008
 2575              	.set CYDEV_PHUB_TDMEM10_ORIG_TD0, 0x40007850
 2576              	.set CYDEV_PHUB_TDMEM10_ORIG_TD1, 0x40007854
 2577              	.set CYDEV_PHUB_TDMEM11_BASE, 0x40007858
 2578              	.set CYDEV_PHUB_TDMEM11_SIZE, 0x00000008
 2579              	.set CYDEV_PHUB_TDMEM11_ORIG_TD0, 0x40007858
 2580              	.set CYDEV_PHUB_TDMEM11_ORIG_TD1, 0x4000785c
 2581              	.set CYDEV_PHUB_TDMEM12_BASE, 0x40007860
 2582              	.set CYDEV_PHUB_TDMEM12_SIZE, 0x00000008
 2583              	.set CYDEV_PHUB_TDMEM12_ORIG_TD0, 0x40007860
 2584              	.set CYDEV_PHUB_TDMEM12_ORIG_TD1, 0x40007864
 2585              	.set CYDEV_PHUB_TDMEM13_BASE, 0x40007868
 2586              	.set CYDEV_PHUB_TDMEM13_SIZE, 0x00000008
 2587              	.set CYDEV_PHUB_TDMEM13_ORIG_TD0, 0x40007868
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 47


 2588              	.set CYDEV_PHUB_TDMEM13_ORIG_TD1, 0x4000786c
 2589              	.set CYDEV_PHUB_TDMEM14_BASE, 0x40007870
 2590              	.set CYDEV_PHUB_TDMEM14_SIZE, 0x00000008
 2591              	.set CYDEV_PHUB_TDMEM14_ORIG_TD0, 0x40007870
 2592              	.set CYDEV_PHUB_TDMEM14_ORIG_TD1, 0x40007874
 2593              	.set CYDEV_PHUB_TDMEM15_BASE, 0x40007878
 2594              	.set CYDEV_PHUB_TDMEM15_SIZE, 0x00000008
 2595              	.set CYDEV_PHUB_TDMEM15_ORIG_TD0, 0x40007878
 2596              	.set CYDEV_PHUB_TDMEM15_ORIG_TD1, 0x4000787c
 2597              	.set CYDEV_PHUB_TDMEM16_BASE, 0x40007880
 2598              	.set CYDEV_PHUB_TDMEM16_SIZE, 0x00000008
 2599              	.set CYDEV_PHUB_TDMEM16_ORIG_TD0, 0x40007880
 2600              	.set CYDEV_PHUB_TDMEM16_ORIG_TD1, 0x40007884
 2601              	.set CYDEV_PHUB_TDMEM17_BASE, 0x40007888
 2602              	.set CYDEV_PHUB_TDMEM17_SIZE, 0x00000008
 2603              	.set CYDEV_PHUB_TDMEM17_ORIG_TD0, 0x40007888
 2604              	.set CYDEV_PHUB_TDMEM17_ORIG_TD1, 0x4000788c
 2605              	.set CYDEV_PHUB_TDMEM18_BASE, 0x40007890
 2606              	.set CYDEV_PHUB_TDMEM18_SIZE, 0x00000008
 2607              	.set CYDEV_PHUB_TDMEM18_ORIG_TD0, 0x40007890
 2608              	.set CYDEV_PHUB_TDMEM18_ORIG_TD1, 0x40007894
 2609              	.set CYDEV_PHUB_TDMEM19_BASE, 0x40007898
 2610              	.set CYDEV_PHUB_TDMEM19_SIZE, 0x00000008
 2611              	.set CYDEV_PHUB_TDMEM19_ORIG_TD0, 0x40007898
 2612              	.set CYDEV_PHUB_TDMEM19_ORIG_TD1, 0x4000789c
 2613              	.set CYDEV_PHUB_TDMEM20_BASE, 0x400078a0
 2614              	.set CYDEV_PHUB_TDMEM20_SIZE, 0x00000008
 2615              	.set CYDEV_PHUB_TDMEM20_ORIG_TD0, 0x400078a0
 2616              	.set CYDEV_PHUB_TDMEM20_ORIG_TD1, 0x400078a4
 2617              	.set CYDEV_PHUB_TDMEM21_BASE, 0x400078a8
 2618              	.set CYDEV_PHUB_TDMEM21_SIZE, 0x00000008
 2619              	.set CYDEV_PHUB_TDMEM21_ORIG_TD0, 0x400078a8
 2620              	.set CYDEV_PHUB_TDMEM21_ORIG_TD1, 0x400078ac
 2621              	.set CYDEV_PHUB_TDMEM22_BASE, 0x400078b0
 2622              	.set CYDEV_PHUB_TDMEM22_SIZE, 0x00000008
 2623              	.set CYDEV_PHUB_TDMEM22_ORIG_TD0, 0x400078b0
 2624              	.set CYDEV_PHUB_TDMEM22_ORIG_TD1, 0x400078b4
 2625              	.set CYDEV_PHUB_TDMEM23_BASE, 0x400078b8
 2626              	.set CYDEV_PHUB_TDMEM23_SIZE, 0x00000008
 2627              	.set CYDEV_PHUB_TDMEM23_ORIG_TD0, 0x400078b8
 2628              	.set CYDEV_PHUB_TDMEM23_ORIG_TD1, 0x400078bc
 2629              	.set CYDEV_PHUB_TDMEM24_BASE, 0x400078c0
 2630              	.set CYDEV_PHUB_TDMEM24_SIZE, 0x00000008
 2631              	.set CYDEV_PHUB_TDMEM24_ORIG_TD0, 0x400078c0
 2632              	.set CYDEV_PHUB_TDMEM24_ORIG_TD1, 0x400078c4
 2633              	.set CYDEV_PHUB_TDMEM25_BASE, 0x400078c8
 2634              	.set CYDEV_PHUB_TDMEM25_SIZE, 0x00000008
 2635              	.set CYDEV_PHUB_TDMEM25_ORIG_TD0, 0x400078c8
 2636              	.set CYDEV_PHUB_TDMEM25_ORIG_TD1, 0x400078cc
 2637              	.set CYDEV_PHUB_TDMEM26_BASE, 0x400078d0
 2638              	.set CYDEV_PHUB_TDMEM26_SIZE, 0x00000008
 2639              	.set CYDEV_PHUB_TDMEM26_ORIG_TD0, 0x400078d0
 2640              	.set CYDEV_PHUB_TDMEM26_ORIG_TD1, 0x400078d4
 2641              	.set CYDEV_PHUB_TDMEM27_BASE, 0x400078d8
 2642              	.set CYDEV_PHUB_TDMEM27_SIZE, 0x00000008
 2643              	.set CYDEV_PHUB_TDMEM27_ORIG_TD0, 0x400078d8
 2644              	.set CYDEV_PHUB_TDMEM27_ORIG_TD1, 0x400078dc
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 48


 2645              	.set CYDEV_PHUB_TDMEM28_BASE, 0x400078e0
 2646              	.set CYDEV_PHUB_TDMEM28_SIZE, 0x00000008
 2647              	.set CYDEV_PHUB_TDMEM28_ORIG_TD0, 0x400078e0
 2648              	.set CYDEV_PHUB_TDMEM28_ORIG_TD1, 0x400078e4
 2649              	.set CYDEV_PHUB_TDMEM29_BASE, 0x400078e8
 2650              	.set CYDEV_PHUB_TDMEM29_SIZE, 0x00000008
 2651              	.set CYDEV_PHUB_TDMEM29_ORIG_TD0, 0x400078e8
 2652              	.set CYDEV_PHUB_TDMEM29_ORIG_TD1, 0x400078ec
 2653              	.set CYDEV_PHUB_TDMEM30_BASE, 0x400078f0
 2654              	.set CYDEV_PHUB_TDMEM30_SIZE, 0x00000008
 2655              	.set CYDEV_PHUB_TDMEM30_ORIG_TD0, 0x400078f0
 2656              	.set CYDEV_PHUB_TDMEM30_ORIG_TD1, 0x400078f4
 2657              	.set CYDEV_PHUB_TDMEM31_BASE, 0x400078f8
 2658              	.set CYDEV_PHUB_TDMEM31_SIZE, 0x00000008
 2659              	.set CYDEV_PHUB_TDMEM31_ORIG_TD0, 0x400078f8
 2660              	.set CYDEV_PHUB_TDMEM31_ORIG_TD1, 0x400078fc
 2661              	.set CYDEV_PHUB_TDMEM32_BASE, 0x40007900
 2662              	.set CYDEV_PHUB_TDMEM32_SIZE, 0x00000008
 2663              	.set CYDEV_PHUB_TDMEM32_ORIG_TD0, 0x40007900
 2664              	.set CYDEV_PHUB_TDMEM32_ORIG_TD1, 0x40007904
 2665              	.set CYDEV_PHUB_TDMEM33_BASE, 0x40007908
 2666              	.set CYDEV_PHUB_TDMEM33_SIZE, 0x00000008
 2667              	.set CYDEV_PHUB_TDMEM33_ORIG_TD0, 0x40007908
 2668              	.set CYDEV_PHUB_TDMEM33_ORIG_TD1, 0x4000790c
 2669              	.set CYDEV_PHUB_TDMEM34_BASE, 0x40007910
 2670              	.set CYDEV_PHUB_TDMEM34_SIZE, 0x00000008
 2671              	.set CYDEV_PHUB_TDMEM34_ORIG_TD0, 0x40007910
 2672              	.set CYDEV_PHUB_TDMEM34_ORIG_TD1, 0x40007914
 2673              	.set CYDEV_PHUB_TDMEM35_BASE, 0x40007918
 2674              	.set CYDEV_PHUB_TDMEM35_SIZE, 0x00000008
 2675              	.set CYDEV_PHUB_TDMEM35_ORIG_TD0, 0x40007918
 2676              	.set CYDEV_PHUB_TDMEM35_ORIG_TD1, 0x4000791c
 2677              	.set CYDEV_PHUB_TDMEM36_BASE, 0x40007920
 2678              	.set CYDEV_PHUB_TDMEM36_SIZE, 0x00000008
 2679              	.set CYDEV_PHUB_TDMEM36_ORIG_TD0, 0x40007920
 2680              	.set CYDEV_PHUB_TDMEM36_ORIG_TD1, 0x40007924
 2681              	.set CYDEV_PHUB_TDMEM37_BASE, 0x40007928
 2682              	.set CYDEV_PHUB_TDMEM37_SIZE, 0x00000008
 2683              	.set CYDEV_PHUB_TDMEM37_ORIG_TD0, 0x40007928
 2684              	.set CYDEV_PHUB_TDMEM37_ORIG_TD1, 0x4000792c
 2685              	.set CYDEV_PHUB_TDMEM38_BASE, 0x40007930
 2686              	.set CYDEV_PHUB_TDMEM38_SIZE, 0x00000008
 2687              	.set CYDEV_PHUB_TDMEM38_ORIG_TD0, 0x40007930
 2688              	.set CYDEV_PHUB_TDMEM38_ORIG_TD1, 0x40007934
 2689              	.set CYDEV_PHUB_TDMEM39_BASE, 0x40007938
 2690              	.set CYDEV_PHUB_TDMEM39_SIZE, 0x00000008
 2691              	.set CYDEV_PHUB_TDMEM39_ORIG_TD0, 0x40007938
 2692              	.set CYDEV_PHUB_TDMEM39_ORIG_TD1, 0x4000793c
 2693              	.set CYDEV_PHUB_TDMEM40_BASE, 0x40007940
 2694              	.set CYDEV_PHUB_TDMEM40_SIZE, 0x00000008
 2695              	.set CYDEV_PHUB_TDMEM40_ORIG_TD0, 0x40007940
 2696              	.set CYDEV_PHUB_TDMEM40_ORIG_TD1, 0x40007944
 2697              	.set CYDEV_PHUB_TDMEM41_BASE, 0x40007948
 2698              	.set CYDEV_PHUB_TDMEM41_SIZE, 0x00000008
 2699              	.set CYDEV_PHUB_TDMEM41_ORIG_TD0, 0x40007948
 2700              	.set CYDEV_PHUB_TDMEM41_ORIG_TD1, 0x4000794c
 2701              	.set CYDEV_PHUB_TDMEM42_BASE, 0x40007950
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 49


 2702              	.set CYDEV_PHUB_TDMEM42_SIZE, 0x00000008
 2703              	.set CYDEV_PHUB_TDMEM42_ORIG_TD0, 0x40007950
 2704              	.set CYDEV_PHUB_TDMEM42_ORIG_TD1, 0x40007954
 2705              	.set CYDEV_PHUB_TDMEM43_BASE, 0x40007958
 2706              	.set CYDEV_PHUB_TDMEM43_SIZE, 0x00000008
 2707              	.set CYDEV_PHUB_TDMEM43_ORIG_TD0, 0x40007958
 2708              	.set CYDEV_PHUB_TDMEM43_ORIG_TD1, 0x4000795c
 2709              	.set CYDEV_PHUB_TDMEM44_BASE, 0x40007960
 2710              	.set CYDEV_PHUB_TDMEM44_SIZE, 0x00000008
 2711              	.set CYDEV_PHUB_TDMEM44_ORIG_TD0, 0x40007960
 2712              	.set CYDEV_PHUB_TDMEM44_ORIG_TD1, 0x40007964
 2713              	.set CYDEV_PHUB_TDMEM45_BASE, 0x40007968
 2714              	.set CYDEV_PHUB_TDMEM45_SIZE, 0x00000008
 2715              	.set CYDEV_PHUB_TDMEM45_ORIG_TD0, 0x40007968
 2716              	.set CYDEV_PHUB_TDMEM45_ORIG_TD1, 0x4000796c
 2717              	.set CYDEV_PHUB_TDMEM46_BASE, 0x40007970
 2718              	.set CYDEV_PHUB_TDMEM46_SIZE, 0x00000008
 2719              	.set CYDEV_PHUB_TDMEM46_ORIG_TD0, 0x40007970
 2720              	.set CYDEV_PHUB_TDMEM46_ORIG_TD1, 0x40007974
 2721              	.set CYDEV_PHUB_TDMEM47_BASE, 0x40007978
 2722              	.set CYDEV_PHUB_TDMEM47_SIZE, 0x00000008
 2723              	.set CYDEV_PHUB_TDMEM47_ORIG_TD0, 0x40007978
 2724              	.set CYDEV_PHUB_TDMEM47_ORIG_TD1, 0x4000797c
 2725              	.set CYDEV_PHUB_TDMEM48_BASE, 0x40007980
 2726              	.set CYDEV_PHUB_TDMEM48_SIZE, 0x00000008
 2727              	.set CYDEV_PHUB_TDMEM48_ORIG_TD0, 0x40007980
 2728              	.set CYDEV_PHUB_TDMEM48_ORIG_TD1, 0x40007984
 2729              	.set CYDEV_PHUB_TDMEM49_BASE, 0x40007988
 2730              	.set CYDEV_PHUB_TDMEM49_SIZE, 0x00000008
 2731              	.set CYDEV_PHUB_TDMEM49_ORIG_TD0, 0x40007988
 2732              	.set CYDEV_PHUB_TDMEM49_ORIG_TD1, 0x4000798c
 2733              	.set CYDEV_PHUB_TDMEM50_BASE, 0x40007990
 2734              	.set CYDEV_PHUB_TDMEM50_SIZE, 0x00000008
 2735              	.set CYDEV_PHUB_TDMEM50_ORIG_TD0, 0x40007990
 2736              	.set CYDEV_PHUB_TDMEM50_ORIG_TD1, 0x40007994
 2737              	.set CYDEV_PHUB_TDMEM51_BASE, 0x40007998
 2738              	.set CYDEV_PHUB_TDMEM51_SIZE, 0x00000008
 2739              	.set CYDEV_PHUB_TDMEM51_ORIG_TD0, 0x40007998
 2740              	.set CYDEV_PHUB_TDMEM51_ORIG_TD1, 0x4000799c
 2741              	.set CYDEV_PHUB_TDMEM52_BASE, 0x400079a0
 2742              	.set CYDEV_PHUB_TDMEM52_SIZE, 0x00000008
 2743              	.set CYDEV_PHUB_TDMEM52_ORIG_TD0, 0x400079a0
 2744              	.set CYDEV_PHUB_TDMEM52_ORIG_TD1, 0x400079a4
 2745              	.set CYDEV_PHUB_TDMEM53_BASE, 0x400079a8
 2746              	.set CYDEV_PHUB_TDMEM53_SIZE, 0x00000008
 2747              	.set CYDEV_PHUB_TDMEM53_ORIG_TD0, 0x400079a8
 2748              	.set CYDEV_PHUB_TDMEM53_ORIG_TD1, 0x400079ac
 2749              	.set CYDEV_PHUB_TDMEM54_BASE, 0x400079b0
 2750              	.set CYDEV_PHUB_TDMEM54_SIZE, 0x00000008
 2751              	.set CYDEV_PHUB_TDMEM54_ORIG_TD0, 0x400079b0
 2752              	.set CYDEV_PHUB_TDMEM54_ORIG_TD1, 0x400079b4
 2753              	.set CYDEV_PHUB_TDMEM55_BASE, 0x400079b8
 2754              	.set CYDEV_PHUB_TDMEM55_SIZE, 0x00000008
 2755              	.set CYDEV_PHUB_TDMEM55_ORIG_TD0, 0x400079b8
 2756              	.set CYDEV_PHUB_TDMEM55_ORIG_TD1, 0x400079bc
 2757              	.set CYDEV_PHUB_TDMEM56_BASE, 0x400079c0
 2758              	.set CYDEV_PHUB_TDMEM56_SIZE, 0x00000008
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 50


 2759              	.set CYDEV_PHUB_TDMEM56_ORIG_TD0, 0x400079c0
 2760              	.set CYDEV_PHUB_TDMEM56_ORIG_TD1, 0x400079c4
 2761              	.set CYDEV_PHUB_TDMEM57_BASE, 0x400079c8
 2762              	.set CYDEV_PHUB_TDMEM57_SIZE, 0x00000008
 2763              	.set CYDEV_PHUB_TDMEM57_ORIG_TD0, 0x400079c8
 2764              	.set CYDEV_PHUB_TDMEM57_ORIG_TD1, 0x400079cc
 2765              	.set CYDEV_PHUB_TDMEM58_BASE, 0x400079d0
 2766              	.set CYDEV_PHUB_TDMEM58_SIZE, 0x00000008
 2767              	.set CYDEV_PHUB_TDMEM58_ORIG_TD0, 0x400079d0
 2768              	.set CYDEV_PHUB_TDMEM58_ORIG_TD1, 0x400079d4
 2769              	.set CYDEV_PHUB_TDMEM59_BASE, 0x400079d8
 2770              	.set CYDEV_PHUB_TDMEM59_SIZE, 0x00000008
 2771              	.set CYDEV_PHUB_TDMEM59_ORIG_TD0, 0x400079d8
 2772              	.set CYDEV_PHUB_TDMEM59_ORIG_TD1, 0x400079dc
 2773              	.set CYDEV_PHUB_TDMEM60_BASE, 0x400079e0
 2774              	.set CYDEV_PHUB_TDMEM60_SIZE, 0x00000008
 2775              	.set CYDEV_PHUB_TDMEM60_ORIG_TD0, 0x400079e0
 2776              	.set CYDEV_PHUB_TDMEM60_ORIG_TD1, 0x400079e4
 2777              	.set CYDEV_PHUB_TDMEM61_BASE, 0x400079e8
 2778              	.set CYDEV_PHUB_TDMEM61_SIZE, 0x00000008
 2779              	.set CYDEV_PHUB_TDMEM61_ORIG_TD0, 0x400079e8
 2780              	.set CYDEV_PHUB_TDMEM61_ORIG_TD1, 0x400079ec
 2781              	.set CYDEV_PHUB_TDMEM62_BASE, 0x400079f0
 2782              	.set CYDEV_PHUB_TDMEM62_SIZE, 0x00000008
 2783              	.set CYDEV_PHUB_TDMEM62_ORIG_TD0, 0x400079f0
 2784              	.set CYDEV_PHUB_TDMEM62_ORIG_TD1, 0x400079f4
 2785              	.set CYDEV_PHUB_TDMEM63_BASE, 0x400079f8
 2786              	.set CYDEV_PHUB_TDMEM63_SIZE, 0x00000008
 2787              	.set CYDEV_PHUB_TDMEM63_ORIG_TD0, 0x400079f8
 2788              	.set CYDEV_PHUB_TDMEM63_ORIG_TD1, 0x400079fc
 2789              	.set CYDEV_PHUB_TDMEM64_BASE, 0x40007a00
 2790              	.set CYDEV_PHUB_TDMEM64_SIZE, 0x00000008
 2791              	.set CYDEV_PHUB_TDMEM64_ORIG_TD0, 0x40007a00
 2792              	.set CYDEV_PHUB_TDMEM64_ORIG_TD1, 0x40007a04
 2793              	.set CYDEV_PHUB_TDMEM65_BASE, 0x40007a08
 2794              	.set CYDEV_PHUB_TDMEM65_SIZE, 0x00000008
 2795              	.set CYDEV_PHUB_TDMEM65_ORIG_TD0, 0x40007a08
 2796              	.set CYDEV_PHUB_TDMEM65_ORIG_TD1, 0x40007a0c
 2797              	.set CYDEV_PHUB_TDMEM66_BASE, 0x40007a10
 2798              	.set CYDEV_PHUB_TDMEM66_SIZE, 0x00000008
 2799              	.set CYDEV_PHUB_TDMEM66_ORIG_TD0, 0x40007a10
 2800              	.set CYDEV_PHUB_TDMEM66_ORIG_TD1, 0x40007a14
 2801              	.set CYDEV_PHUB_TDMEM67_BASE, 0x40007a18
 2802              	.set CYDEV_PHUB_TDMEM67_SIZE, 0x00000008
 2803              	.set CYDEV_PHUB_TDMEM67_ORIG_TD0, 0x40007a18
 2804              	.set CYDEV_PHUB_TDMEM67_ORIG_TD1, 0x40007a1c
 2805              	.set CYDEV_PHUB_TDMEM68_BASE, 0x40007a20
 2806              	.set CYDEV_PHUB_TDMEM68_SIZE, 0x00000008
 2807              	.set CYDEV_PHUB_TDMEM68_ORIG_TD0, 0x40007a20
 2808              	.set CYDEV_PHUB_TDMEM68_ORIG_TD1, 0x40007a24
 2809              	.set CYDEV_PHUB_TDMEM69_BASE, 0x40007a28
 2810              	.set CYDEV_PHUB_TDMEM69_SIZE, 0x00000008
 2811              	.set CYDEV_PHUB_TDMEM69_ORIG_TD0, 0x40007a28
 2812              	.set CYDEV_PHUB_TDMEM69_ORIG_TD1, 0x40007a2c
 2813              	.set CYDEV_PHUB_TDMEM70_BASE, 0x40007a30
 2814              	.set CYDEV_PHUB_TDMEM70_SIZE, 0x00000008
 2815              	.set CYDEV_PHUB_TDMEM70_ORIG_TD0, 0x40007a30
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 51


 2816              	.set CYDEV_PHUB_TDMEM70_ORIG_TD1, 0x40007a34
 2817              	.set CYDEV_PHUB_TDMEM71_BASE, 0x40007a38
 2818              	.set CYDEV_PHUB_TDMEM71_SIZE, 0x00000008
 2819              	.set CYDEV_PHUB_TDMEM71_ORIG_TD0, 0x40007a38
 2820              	.set CYDEV_PHUB_TDMEM71_ORIG_TD1, 0x40007a3c
 2821              	.set CYDEV_PHUB_TDMEM72_BASE, 0x40007a40
 2822              	.set CYDEV_PHUB_TDMEM72_SIZE, 0x00000008
 2823              	.set CYDEV_PHUB_TDMEM72_ORIG_TD0, 0x40007a40
 2824              	.set CYDEV_PHUB_TDMEM72_ORIG_TD1, 0x40007a44
 2825              	.set CYDEV_PHUB_TDMEM73_BASE, 0x40007a48
 2826              	.set CYDEV_PHUB_TDMEM73_SIZE, 0x00000008
 2827              	.set CYDEV_PHUB_TDMEM73_ORIG_TD0, 0x40007a48
 2828              	.set CYDEV_PHUB_TDMEM73_ORIG_TD1, 0x40007a4c
 2829              	.set CYDEV_PHUB_TDMEM74_BASE, 0x40007a50
 2830              	.set CYDEV_PHUB_TDMEM74_SIZE, 0x00000008
 2831              	.set CYDEV_PHUB_TDMEM74_ORIG_TD0, 0x40007a50
 2832              	.set CYDEV_PHUB_TDMEM74_ORIG_TD1, 0x40007a54
 2833              	.set CYDEV_PHUB_TDMEM75_BASE, 0x40007a58
 2834              	.set CYDEV_PHUB_TDMEM75_SIZE, 0x00000008
 2835              	.set CYDEV_PHUB_TDMEM75_ORIG_TD0, 0x40007a58
 2836              	.set CYDEV_PHUB_TDMEM75_ORIG_TD1, 0x40007a5c
 2837              	.set CYDEV_PHUB_TDMEM76_BASE, 0x40007a60
 2838              	.set CYDEV_PHUB_TDMEM76_SIZE, 0x00000008
 2839              	.set CYDEV_PHUB_TDMEM76_ORIG_TD0, 0x40007a60
 2840              	.set CYDEV_PHUB_TDMEM76_ORIG_TD1, 0x40007a64
 2841              	.set CYDEV_PHUB_TDMEM77_BASE, 0x40007a68
 2842              	.set CYDEV_PHUB_TDMEM77_SIZE, 0x00000008
 2843              	.set CYDEV_PHUB_TDMEM77_ORIG_TD0, 0x40007a68
 2844              	.set CYDEV_PHUB_TDMEM77_ORIG_TD1, 0x40007a6c
 2845              	.set CYDEV_PHUB_TDMEM78_BASE, 0x40007a70
 2846              	.set CYDEV_PHUB_TDMEM78_SIZE, 0x00000008
 2847              	.set CYDEV_PHUB_TDMEM78_ORIG_TD0, 0x40007a70
 2848              	.set CYDEV_PHUB_TDMEM78_ORIG_TD1, 0x40007a74
 2849              	.set CYDEV_PHUB_TDMEM79_BASE, 0x40007a78
 2850              	.set CYDEV_PHUB_TDMEM79_SIZE, 0x00000008
 2851              	.set CYDEV_PHUB_TDMEM79_ORIG_TD0, 0x40007a78
 2852              	.set CYDEV_PHUB_TDMEM79_ORIG_TD1, 0x40007a7c
 2853              	.set CYDEV_PHUB_TDMEM80_BASE, 0x40007a80
 2854              	.set CYDEV_PHUB_TDMEM80_SIZE, 0x00000008
 2855              	.set CYDEV_PHUB_TDMEM80_ORIG_TD0, 0x40007a80
 2856              	.set CYDEV_PHUB_TDMEM80_ORIG_TD1, 0x40007a84
 2857              	.set CYDEV_PHUB_TDMEM81_BASE, 0x40007a88
 2858              	.set CYDEV_PHUB_TDMEM81_SIZE, 0x00000008
 2859              	.set CYDEV_PHUB_TDMEM81_ORIG_TD0, 0x40007a88
 2860              	.set CYDEV_PHUB_TDMEM81_ORIG_TD1, 0x40007a8c
 2861              	.set CYDEV_PHUB_TDMEM82_BASE, 0x40007a90
 2862              	.set CYDEV_PHUB_TDMEM82_SIZE, 0x00000008
 2863              	.set CYDEV_PHUB_TDMEM82_ORIG_TD0, 0x40007a90
 2864              	.set CYDEV_PHUB_TDMEM82_ORIG_TD1, 0x40007a94
 2865              	.set CYDEV_PHUB_TDMEM83_BASE, 0x40007a98
 2866              	.set CYDEV_PHUB_TDMEM83_SIZE, 0x00000008
 2867              	.set CYDEV_PHUB_TDMEM83_ORIG_TD0, 0x40007a98
 2868              	.set CYDEV_PHUB_TDMEM83_ORIG_TD1, 0x40007a9c
 2869              	.set CYDEV_PHUB_TDMEM84_BASE, 0x40007aa0
 2870              	.set CYDEV_PHUB_TDMEM84_SIZE, 0x00000008
 2871              	.set CYDEV_PHUB_TDMEM84_ORIG_TD0, 0x40007aa0
 2872              	.set CYDEV_PHUB_TDMEM84_ORIG_TD1, 0x40007aa4
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 52


 2873              	.set CYDEV_PHUB_TDMEM85_BASE, 0x40007aa8
 2874              	.set CYDEV_PHUB_TDMEM85_SIZE, 0x00000008
 2875              	.set CYDEV_PHUB_TDMEM85_ORIG_TD0, 0x40007aa8
 2876              	.set CYDEV_PHUB_TDMEM85_ORIG_TD1, 0x40007aac
 2877              	.set CYDEV_PHUB_TDMEM86_BASE, 0x40007ab0
 2878              	.set CYDEV_PHUB_TDMEM86_SIZE, 0x00000008
 2879              	.set CYDEV_PHUB_TDMEM86_ORIG_TD0, 0x40007ab0
 2880              	.set CYDEV_PHUB_TDMEM86_ORIG_TD1, 0x40007ab4
 2881              	.set CYDEV_PHUB_TDMEM87_BASE, 0x40007ab8
 2882              	.set CYDEV_PHUB_TDMEM87_SIZE, 0x00000008
 2883              	.set CYDEV_PHUB_TDMEM87_ORIG_TD0, 0x40007ab8
 2884              	.set CYDEV_PHUB_TDMEM87_ORIG_TD1, 0x40007abc
 2885              	.set CYDEV_PHUB_TDMEM88_BASE, 0x40007ac0
 2886              	.set CYDEV_PHUB_TDMEM88_SIZE, 0x00000008
 2887              	.set CYDEV_PHUB_TDMEM88_ORIG_TD0, 0x40007ac0
 2888              	.set CYDEV_PHUB_TDMEM88_ORIG_TD1, 0x40007ac4
 2889              	.set CYDEV_PHUB_TDMEM89_BASE, 0x40007ac8
 2890              	.set CYDEV_PHUB_TDMEM89_SIZE, 0x00000008
 2891              	.set CYDEV_PHUB_TDMEM89_ORIG_TD0, 0x40007ac8
 2892              	.set CYDEV_PHUB_TDMEM89_ORIG_TD1, 0x40007acc
 2893              	.set CYDEV_PHUB_TDMEM90_BASE, 0x40007ad0
 2894              	.set CYDEV_PHUB_TDMEM90_SIZE, 0x00000008
 2895              	.set CYDEV_PHUB_TDMEM90_ORIG_TD0, 0x40007ad0
 2896              	.set CYDEV_PHUB_TDMEM90_ORIG_TD1, 0x40007ad4
 2897              	.set CYDEV_PHUB_TDMEM91_BASE, 0x40007ad8
 2898              	.set CYDEV_PHUB_TDMEM91_SIZE, 0x00000008
 2899              	.set CYDEV_PHUB_TDMEM91_ORIG_TD0, 0x40007ad8
 2900              	.set CYDEV_PHUB_TDMEM91_ORIG_TD1, 0x40007adc
 2901              	.set CYDEV_PHUB_TDMEM92_BASE, 0x40007ae0
 2902              	.set CYDEV_PHUB_TDMEM92_SIZE, 0x00000008
 2903              	.set CYDEV_PHUB_TDMEM92_ORIG_TD0, 0x40007ae0
 2904              	.set CYDEV_PHUB_TDMEM92_ORIG_TD1, 0x40007ae4
 2905              	.set CYDEV_PHUB_TDMEM93_BASE, 0x40007ae8
 2906              	.set CYDEV_PHUB_TDMEM93_SIZE, 0x00000008
 2907              	.set CYDEV_PHUB_TDMEM93_ORIG_TD0, 0x40007ae8
 2908              	.set CYDEV_PHUB_TDMEM93_ORIG_TD1, 0x40007aec
 2909              	.set CYDEV_PHUB_TDMEM94_BASE, 0x40007af0
 2910              	.set CYDEV_PHUB_TDMEM94_SIZE, 0x00000008
 2911              	.set CYDEV_PHUB_TDMEM94_ORIG_TD0, 0x40007af0
 2912              	.set CYDEV_PHUB_TDMEM94_ORIG_TD1, 0x40007af4
 2913              	.set CYDEV_PHUB_TDMEM95_BASE, 0x40007af8
 2914              	.set CYDEV_PHUB_TDMEM95_SIZE, 0x00000008
 2915              	.set CYDEV_PHUB_TDMEM95_ORIG_TD0, 0x40007af8
 2916              	.set CYDEV_PHUB_TDMEM95_ORIG_TD1, 0x40007afc
 2917              	.set CYDEV_PHUB_TDMEM96_BASE, 0x40007b00
 2918              	.set CYDEV_PHUB_TDMEM96_SIZE, 0x00000008
 2919              	.set CYDEV_PHUB_TDMEM96_ORIG_TD0, 0x40007b00
 2920              	.set CYDEV_PHUB_TDMEM96_ORIG_TD1, 0x40007b04
 2921              	.set CYDEV_PHUB_TDMEM97_BASE, 0x40007b08
 2922              	.set CYDEV_PHUB_TDMEM97_SIZE, 0x00000008
 2923              	.set CYDEV_PHUB_TDMEM97_ORIG_TD0, 0x40007b08
 2924              	.set CYDEV_PHUB_TDMEM97_ORIG_TD1, 0x40007b0c
 2925              	.set CYDEV_PHUB_TDMEM98_BASE, 0x40007b10
 2926              	.set CYDEV_PHUB_TDMEM98_SIZE, 0x00000008
 2927              	.set CYDEV_PHUB_TDMEM98_ORIG_TD0, 0x40007b10
 2928              	.set CYDEV_PHUB_TDMEM98_ORIG_TD1, 0x40007b14
 2929              	.set CYDEV_PHUB_TDMEM99_BASE, 0x40007b18
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 53


 2930              	.set CYDEV_PHUB_TDMEM99_SIZE, 0x00000008
 2931              	.set CYDEV_PHUB_TDMEM99_ORIG_TD0, 0x40007b18
 2932              	.set CYDEV_PHUB_TDMEM99_ORIG_TD1, 0x40007b1c
 2933              	.set CYDEV_PHUB_TDMEM100_BASE, 0x40007b20
 2934              	.set CYDEV_PHUB_TDMEM100_SIZE, 0x00000008
 2935              	.set CYDEV_PHUB_TDMEM100_ORIG_TD0, 0x40007b20
 2936              	.set CYDEV_PHUB_TDMEM100_ORIG_TD1, 0x40007b24
 2937              	.set CYDEV_PHUB_TDMEM101_BASE, 0x40007b28
 2938              	.set CYDEV_PHUB_TDMEM101_SIZE, 0x00000008
 2939              	.set CYDEV_PHUB_TDMEM101_ORIG_TD0, 0x40007b28
 2940              	.set CYDEV_PHUB_TDMEM101_ORIG_TD1, 0x40007b2c
 2941              	.set CYDEV_PHUB_TDMEM102_BASE, 0x40007b30
 2942              	.set CYDEV_PHUB_TDMEM102_SIZE, 0x00000008
 2943              	.set CYDEV_PHUB_TDMEM102_ORIG_TD0, 0x40007b30
 2944              	.set CYDEV_PHUB_TDMEM102_ORIG_TD1, 0x40007b34
 2945              	.set CYDEV_PHUB_TDMEM103_BASE, 0x40007b38
 2946              	.set CYDEV_PHUB_TDMEM103_SIZE, 0x00000008
 2947              	.set CYDEV_PHUB_TDMEM103_ORIG_TD0, 0x40007b38
 2948              	.set CYDEV_PHUB_TDMEM103_ORIG_TD1, 0x40007b3c
 2949              	.set CYDEV_PHUB_TDMEM104_BASE, 0x40007b40
 2950              	.set CYDEV_PHUB_TDMEM104_SIZE, 0x00000008
 2951              	.set CYDEV_PHUB_TDMEM104_ORIG_TD0, 0x40007b40
 2952              	.set CYDEV_PHUB_TDMEM104_ORIG_TD1, 0x40007b44
 2953              	.set CYDEV_PHUB_TDMEM105_BASE, 0x40007b48
 2954              	.set CYDEV_PHUB_TDMEM105_SIZE, 0x00000008
 2955              	.set CYDEV_PHUB_TDMEM105_ORIG_TD0, 0x40007b48
 2956              	.set CYDEV_PHUB_TDMEM105_ORIG_TD1, 0x40007b4c
 2957              	.set CYDEV_PHUB_TDMEM106_BASE, 0x40007b50
 2958              	.set CYDEV_PHUB_TDMEM106_SIZE, 0x00000008
 2959              	.set CYDEV_PHUB_TDMEM106_ORIG_TD0, 0x40007b50
 2960              	.set CYDEV_PHUB_TDMEM106_ORIG_TD1, 0x40007b54
 2961              	.set CYDEV_PHUB_TDMEM107_BASE, 0x40007b58
 2962              	.set CYDEV_PHUB_TDMEM107_SIZE, 0x00000008
 2963              	.set CYDEV_PHUB_TDMEM107_ORIG_TD0, 0x40007b58
 2964              	.set CYDEV_PHUB_TDMEM107_ORIG_TD1, 0x40007b5c
 2965              	.set CYDEV_PHUB_TDMEM108_BASE, 0x40007b60
 2966              	.set CYDEV_PHUB_TDMEM108_SIZE, 0x00000008
 2967              	.set CYDEV_PHUB_TDMEM108_ORIG_TD0, 0x40007b60
 2968              	.set CYDEV_PHUB_TDMEM108_ORIG_TD1, 0x40007b64
 2969              	.set CYDEV_PHUB_TDMEM109_BASE, 0x40007b68
 2970              	.set CYDEV_PHUB_TDMEM109_SIZE, 0x00000008
 2971              	.set CYDEV_PHUB_TDMEM109_ORIG_TD0, 0x40007b68
 2972              	.set CYDEV_PHUB_TDMEM109_ORIG_TD1, 0x40007b6c
 2973              	.set CYDEV_PHUB_TDMEM110_BASE, 0x40007b70
 2974              	.set CYDEV_PHUB_TDMEM110_SIZE, 0x00000008
 2975              	.set CYDEV_PHUB_TDMEM110_ORIG_TD0, 0x40007b70
 2976              	.set CYDEV_PHUB_TDMEM110_ORIG_TD1, 0x40007b74
 2977              	.set CYDEV_PHUB_TDMEM111_BASE, 0x40007b78
 2978              	.set CYDEV_PHUB_TDMEM111_SIZE, 0x00000008
 2979              	.set CYDEV_PHUB_TDMEM111_ORIG_TD0, 0x40007b78
 2980              	.set CYDEV_PHUB_TDMEM111_ORIG_TD1, 0x40007b7c
 2981              	.set CYDEV_PHUB_TDMEM112_BASE, 0x40007b80
 2982              	.set CYDEV_PHUB_TDMEM112_SIZE, 0x00000008
 2983              	.set CYDEV_PHUB_TDMEM112_ORIG_TD0, 0x40007b80
 2984              	.set CYDEV_PHUB_TDMEM112_ORIG_TD1, 0x40007b84
 2985              	.set CYDEV_PHUB_TDMEM113_BASE, 0x40007b88
 2986              	.set CYDEV_PHUB_TDMEM113_SIZE, 0x00000008
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 54


 2987              	.set CYDEV_PHUB_TDMEM113_ORIG_TD0, 0x40007b88
 2988              	.set CYDEV_PHUB_TDMEM113_ORIG_TD1, 0x40007b8c
 2989              	.set CYDEV_PHUB_TDMEM114_BASE, 0x40007b90
 2990              	.set CYDEV_PHUB_TDMEM114_SIZE, 0x00000008
 2991              	.set CYDEV_PHUB_TDMEM114_ORIG_TD0, 0x40007b90
 2992              	.set CYDEV_PHUB_TDMEM114_ORIG_TD1, 0x40007b94
 2993              	.set CYDEV_PHUB_TDMEM115_BASE, 0x40007b98
 2994              	.set CYDEV_PHUB_TDMEM115_SIZE, 0x00000008
 2995              	.set CYDEV_PHUB_TDMEM115_ORIG_TD0, 0x40007b98
 2996              	.set CYDEV_PHUB_TDMEM115_ORIG_TD1, 0x40007b9c
 2997              	.set CYDEV_PHUB_TDMEM116_BASE, 0x40007ba0
 2998              	.set CYDEV_PHUB_TDMEM116_SIZE, 0x00000008
 2999              	.set CYDEV_PHUB_TDMEM116_ORIG_TD0, 0x40007ba0
 3000              	.set CYDEV_PHUB_TDMEM116_ORIG_TD1, 0x40007ba4
 3001              	.set CYDEV_PHUB_TDMEM117_BASE, 0x40007ba8
 3002              	.set CYDEV_PHUB_TDMEM117_SIZE, 0x00000008
 3003              	.set CYDEV_PHUB_TDMEM117_ORIG_TD0, 0x40007ba8
 3004              	.set CYDEV_PHUB_TDMEM117_ORIG_TD1, 0x40007bac
 3005              	.set CYDEV_PHUB_TDMEM118_BASE, 0x40007bb0
 3006              	.set CYDEV_PHUB_TDMEM118_SIZE, 0x00000008
 3007              	.set CYDEV_PHUB_TDMEM118_ORIG_TD0, 0x40007bb0
 3008              	.set CYDEV_PHUB_TDMEM118_ORIG_TD1, 0x40007bb4
 3009              	.set CYDEV_PHUB_TDMEM119_BASE, 0x40007bb8
 3010              	.set CYDEV_PHUB_TDMEM119_SIZE, 0x00000008
 3011              	.set CYDEV_PHUB_TDMEM119_ORIG_TD0, 0x40007bb8
 3012              	.set CYDEV_PHUB_TDMEM119_ORIG_TD1, 0x40007bbc
 3013              	.set CYDEV_PHUB_TDMEM120_BASE, 0x40007bc0
 3014              	.set CYDEV_PHUB_TDMEM120_SIZE, 0x00000008
 3015              	.set CYDEV_PHUB_TDMEM120_ORIG_TD0, 0x40007bc0
 3016              	.set CYDEV_PHUB_TDMEM120_ORIG_TD1, 0x40007bc4
 3017              	.set CYDEV_PHUB_TDMEM121_BASE, 0x40007bc8
 3018              	.set CYDEV_PHUB_TDMEM121_SIZE, 0x00000008
 3019              	.set CYDEV_PHUB_TDMEM121_ORIG_TD0, 0x40007bc8
 3020              	.set CYDEV_PHUB_TDMEM121_ORIG_TD1, 0x40007bcc
 3021              	.set CYDEV_PHUB_TDMEM122_BASE, 0x40007bd0
 3022              	.set CYDEV_PHUB_TDMEM122_SIZE, 0x00000008
 3023              	.set CYDEV_PHUB_TDMEM122_ORIG_TD0, 0x40007bd0
 3024              	.set CYDEV_PHUB_TDMEM122_ORIG_TD1, 0x40007bd4
 3025              	.set CYDEV_PHUB_TDMEM123_BASE, 0x40007bd8
 3026              	.set CYDEV_PHUB_TDMEM123_SIZE, 0x00000008
 3027              	.set CYDEV_PHUB_TDMEM123_ORIG_TD0, 0x40007bd8
 3028              	.set CYDEV_PHUB_TDMEM123_ORIG_TD1, 0x40007bdc
 3029              	.set CYDEV_PHUB_TDMEM124_BASE, 0x40007be0
 3030              	.set CYDEV_PHUB_TDMEM124_SIZE, 0x00000008
 3031              	.set CYDEV_PHUB_TDMEM124_ORIG_TD0, 0x40007be0
 3032              	.set CYDEV_PHUB_TDMEM124_ORIG_TD1, 0x40007be4
 3033              	.set CYDEV_PHUB_TDMEM125_BASE, 0x40007be8
 3034              	.set CYDEV_PHUB_TDMEM125_SIZE, 0x00000008
 3035              	.set CYDEV_PHUB_TDMEM125_ORIG_TD0, 0x40007be8
 3036              	.set CYDEV_PHUB_TDMEM125_ORIG_TD1, 0x40007bec
 3037              	.set CYDEV_PHUB_TDMEM126_BASE, 0x40007bf0
 3038              	.set CYDEV_PHUB_TDMEM126_SIZE, 0x00000008
 3039              	.set CYDEV_PHUB_TDMEM126_ORIG_TD0, 0x40007bf0
 3040              	.set CYDEV_PHUB_TDMEM126_ORIG_TD1, 0x40007bf4
 3041              	.set CYDEV_PHUB_TDMEM127_BASE, 0x40007bf8
 3042              	.set CYDEV_PHUB_TDMEM127_SIZE, 0x00000008
 3043              	.set CYDEV_PHUB_TDMEM127_ORIG_TD0, 0x40007bf8
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 55


 3044              	.set CYDEV_PHUB_TDMEM127_ORIG_TD1, 0x40007bfc
 3045              	.set CYDEV_EE_BASE, 0x40008000
 3046              	.set CYDEV_EE_SIZE, 0x00000800
 3047              	.set CYDEV_EE_DATA_MBASE, 0x40008000
 3048              	.set CYDEV_EE_DATA_MSIZE, 0x00000800
 3049              	.set CYDEV_CAN0_BASE, 0x4000a000
 3050              	.set CYDEV_CAN0_SIZE, 0x000002a0
 3051              	.set CYDEV_CAN0_CSR_BASE, 0x4000a000
 3052              	.set CYDEV_CAN0_CSR_SIZE, 0x00000018
 3053              	.set CYDEV_CAN0_CSR_INT_SR, 0x4000a000
 3054              	.set CYDEV_CAN0_CSR_INT_EN, 0x4000a004
 3055              	.set CYDEV_CAN0_CSR_BUF_SR, 0x4000a008
 3056              	.set CYDEV_CAN0_CSR_ERR_SR, 0x4000a00c
 3057              	.set CYDEV_CAN0_CSR_CMD, 0x4000a010
 3058              	.set CYDEV_CAN0_CSR_CFG, 0x4000a014
 3059              	.set CYDEV_CAN0_TX0_BASE, 0x4000a020
 3060              	.set CYDEV_CAN0_TX0_SIZE, 0x00000010
 3061              	.set CYDEV_CAN0_TX0_CMD, 0x4000a020
 3062              	.set CYDEV_CAN0_TX0_ID, 0x4000a024
 3063              	.set CYDEV_CAN0_TX0_DH, 0x4000a028
 3064              	.set CYDEV_CAN0_TX0_DL, 0x4000a02c
 3065              	.set CYDEV_CAN0_TX1_BASE, 0x4000a030
 3066              	.set CYDEV_CAN0_TX1_SIZE, 0x00000010
 3067              	.set CYDEV_CAN0_TX1_CMD, 0x4000a030
 3068              	.set CYDEV_CAN0_TX1_ID, 0x4000a034
 3069              	.set CYDEV_CAN0_TX1_DH, 0x4000a038
 3070              	.set CYDEV_CAN0_TX1_DL, 0x4000a03c
 3071              	.set CYDEV_CAN0_TX2_BASE, 0x4000a040
 3072              	.set CYDEV_CAN0_TX2_SIZE, 0x00000010
 3073              	.set CYDEV_CAN0_TX2_CMD, 0x4000a040
 3074              	.set CYDEV_CAN0_TX2_ID, 0x4000a044
 3075              	.set CYDEV_CAN0_TX2_DH, 0x4000a048
 3076              	.set CYDEV_CAN0_TX2_DL, 0x4000a04c
 3077              	.set CYDEV_CAN0_TX3_BASE, 0x4000a050
 3078              	.set CYDEV_CAN0_TX3_SIZE, 0x00000010
 3079              	.set CYDEV_CAN0_TX3_CMD, 0x4000a050
 3080              	.set CYDEV_CAN0_TX3_ID, 0x4000a054
 3081              	.set CYDEV_CAN0_TX3_DH, 0x4000a058
 3082              	.set CYDEV_CAN0_TX3_DL, 0x4000a05c
 3083              	.set CYDEV_CAN0_TX4_BASE, 0x4000a060
 3084              	.set CYDEV_CAN0_TX4_SIZE, 0x00000010
 3085              	.set CYDEV_CAN0_TX4_CMD, 0x4000a060
 3086              	.set CYDEV_CAN0_TX4_ID, 0x4000a064
 3087              	.set CYDEV_CAN0_TX4_DH, 0x4000a068
 3088              	.set CYDEV_CAN0_TX4_DL, 0x4000a06c
 3089              	.set CYDEV_CAN0_TX5_BASE, 0x4000a070
 3090              	.set CYDEV_CAN0_TX5_SIZE, 0x00000010
 3091              	.set CYDEV_CAN0_TX5_CMD, 0x4000a070
 3092              	.set CYDEV_CAN0_TX5_ID, 0x4000a074
 3093              	.set CYDEV_CAN0_TX5_DH, 0x4000a078
 3094              	.set CYDEV_CAN0_TX5_DL, 0x4000a07c
 3095              	.set CYDEV_CAN0_TX6_BASE, 0x4000a080
 3096              	.set CYDEV_CAN0_TX6_SIZE, 0x00000010
 3097              	.set CYDEV_CAN0_TX6_CMD, 0x4000a080
 3098              	.set CYDEV_CAN0_TX6_ID, 0x4000a084
 3099              	.set CYDEV_CAN0_TX6_DH, 0x4000a088
 3100              	.set CYDEV_CAN0_TX6_DL, 0x4000a08c
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 56


 3101              	.set CYDEV_CAN0_TX7_BASE, 0x4000a090
 3102              	.set CYDEV_CAN0_TX7_SIZE, 0x00000010
 3103              	.set CYDEV_CAN0_TX7_CMD, 0x4000a090
 3104              	.set CYDEV_CAN0_TX7_ID, 0x4000a094
 3105              	.set CYDEV_CAN0_TX7_DH, 0x4000a098
 3106              	.set CYDEV_CAN0_TX7_DL, 0x4000a09c
 3107              	.set CYDEV_CAN0_RX0_BASE, 0x4000a0a0
 3108              	.set CYDEV_CAN0_RX0_SIZE, 0x00000020
 3109              	.set CYDEV_CAN0_RX0_CMD, 0x4000a0a0
 3110              	.set CYDEV_CAN0_RX0_ID, 0x4000a0a4
 3111              	.set CYDEV_CAN0_RX0_DH, 0x4000a0a8
 3112              	.set CYDEV_CAN0_RX0_DL, 0x4000a0ac
 3113              	.set CYDEV_CAN0_RX0_AMR, 0x4000a0b0
 3114              	.set CYDEV_CAN0_RX0_ACR, 0x4000a0b4
 3115              	.set CYDEV_CAN0_RX0_AMRD, 0x4000a0b8
 3116              	.set CYDEV_CAN0_RX0_ACRD, 0x4000a0bc
 3117              	.set CYDEV_CAN0_RX1_BASE, 0x4000a0c0
 3118              	.set CYDEV_CAN0_RX1_SIZE, 0x00000020
 3119              	.set CYDEV_CAN0_RX1_CMD, 0x4000a0c0
 3120              	.set CYDEV_CAN0_RX1_ID, 0x4000a0c4
 3121              	.set CYDEV_CAN0_RX1_DH, 0x4000a0c8
 3122              	.set CYDEV_CAN0_RX1_DL, 0x4000a0cc
 3123              	.set CYDEV_CAN0_RX1_AMR, 0x4000a0d0
 3124              	.set CYDEV_CAN0_RX1_ACR, 0x4000a0d4
 3125              	.set CYDEV_CAN0_RX1_AMRD, 0x4000a0d8
 3126              	.set CYDEV_CAN0_RX1_ACRD, 0x4000a0dc
 3127              	.set CYDEV_CAN0_RX2_BASE, 0x4000a0e0
 3128              	.set CYDEV_CAN0_RX2_SIZE, 0x00000020
 3129              	.set CYDEV_CAN0_RX2_CMD, 0x4000a0e0
 3130              	.set CYDEV_CAN0_RX2_ID, 0x4000a0e4
 3131              	.set CYDEV_CAN0_RX2_DH, 0x4000a0e8
 3132              	.set CYDEV_CAN0_RX2_DL, 0x4000a0ec
 3133              	.set CYDEV_CAN0_RX2_AMR, 0x4000a0f0
 3134              	.set CYDEV_CAN0_RX2_ACR, 0x4000a0f4
 3135              	.set CYDEV_CAN0_RX2_AMRD, 0x4000a0f8
 3136              	.set CYDEV_CAN0_RX2_ACRD, 0x4000a0fc
 3137              	.set CYDEV_CAN0_RX3_BASE, 0x4000a100
 3138              	.set CYDEV_CAN0_RX3_SIZE, 0x00000020
 3139              	.set CYDEV_CAN0_RX3_CMD, 0x4000a100
 3140              	.set CYDEV_CAN0_RX3_ID, 0x4000a104
 3141              	.set CYDEV_CAN0_RX3_DH, 0x4000a108
 3142              	.set CYDEV_CAN0_RX3_DL, 0x4000a10c
 3143              	.set CYDEV_CAN0_RX3_AMR, 0x4000a110
 3144              	.set CYDEV_CAN0_RX3_ACR, 0x4000a114
 3145              	.set CYDEV_CAN0_RX3_AMRD, 0x4000a118
 3146              	.set CYDEV_CAN0_RX3_ACRD, 0x4000a11c
 3147              	.set CYDEV_CAN0_RX4_BASE, 0x4000a120
 3148              	.set CYDEV_CAN0_RX4_SIZE, 0x00000020
 3149              	.set CYDEV_CAN0_RX4_CMD, 0x4000a120
 3150              	.set CYDEV_CAN0_RX4_ID, 0x4000a124
 3151              	.set CYDEV_CAN0_RX4_DH, 0x4000a128
 3152              	.set CYDEV_CAN0_RX4_DL, 0x4000a12c
 3153              	.set CYDEV_CAN0_RX4_AMR, 0x4000a130
 3154              	.set CYDEV_CAN0_RX4_ACR, 0x4000a134
 3155              	.set CYDEV_CAN0_RX4_AMRD, 0x4000a138
 3156              	.set CYDEV_CAN0_RX4_ACRD, 0x4000a13c
 3157              	.set CYDEV_CAN0_RX5_BASE, 0x4000a140
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 57


 3158              	.set CYDEV_CAN0_RX5_SIZE, 0x00000020
 3159              	.set CYDEV_CAN0_RX5_CMD, 0x4000a140
 3160              	.set CYDEV_CAN0_RX5_ID, 0x4000a144
 3161              	.set CYDEV_CAN0_RX5_DH, 0x4000a148
 3162              	.set CYDEV_CAN0_RX5_DL, 0x4000a14c
 3163              	.set CYDEV_CAN0_RX5_AMR, 0x4000a150
 3164              	.set CYDEV_CAN0_RX5_ACR, 0x4000a154
 3165              	.set CYDEV_CAN0_RX5_AMRD, 0x4000a158
 3166              	.set CYDEV_CAN0_RX5_ACRD, 0x4000a15c
 3167              	.set CYDEV_CAN0_RX6_BASE, 0x4000a160
 3168              	.set CYDEV_CAN0_RX6_SIZE, 0x00000020
 3169              	.set CYDEV_CAN0_RX6_CMD, 0x4000a160
 3170              	.set CYDEV_CAN0_RX6_ID, 0x4000a164
 3171              	.set CYDEV_CAN0_RX6_DH, 0x4000a168
 3172              	.set CYDEV_CAN0_RX6_DL, 0x4000a16c
 3173              	.set CYDEV_CAN0_RX6_AMR, 0x4000a170
 3174              	.set CYDEV_CAN0_RX6_ACR, 0x4000a174
 3175              	.set CYDEV_CAN0_RX6_AMRD, 0x4000a178
 3176              	.set CYDEV_CAN0_RX6_ACRD, 0x4000a17c
 3177              	.set CYDEV_CAN0_RX7_BASE, 0x4000a180
 3178              	.set CYDEV_CAN0_RX7_SIZE, 0x00000020
 3179              	.set CYDEV_CAN0_RX7_CMD, 0x4000a180
 3180              	.set CYDEV_CAN0_RX7_ID, 0x4000a184
 3181              	.set CYDEV_CAN0_RX7_DH, 0x4000a188
 3182              	.set CYDEV_CAN0_RX7_DL, 0x4000a18c
 3183              	.set CYDEV_CAN0_RX7_AMR, 0x4000a190
 3184              	.set CYDEV_CAN0_RX7_ACR, 0x4000a194
 3185              	.set CYDEV_CAN0_RX7_AMRD, 0x4000a198
 3186              	.set CYDEV_CAN0_RX7_ACRD, 0x4000a19c
 3187              	.set CYDEV_CAN0_RX8_BASE, 0x4000a1a0
 3188              	.set CYDEV_CAN0_RX8_SIZE, 0x00000020
 3189              	.set CYDEV_CAN0_RX8_CMD, 0x4000a1a0
 3190              	.set CYDEV_CAN0_RX8_ID, 0x4000a1a4
 3191              	.set CYDEV_CAN0_RX8_DH, 0x4000a1a8
 3192              	.set CYDEV_CAN0_RX8_DL, 0x4000a1ac
 3193              	.set CYDEV_CAN0_RX8_AMR, 0x4000a1b0
 3194              	.set CYDEV_CAN0_RX8_ACR, 0x4000a1b4
 3195              	.set CYDEV_CAN0_RX8_AMRD, 0x4000a1b8
 3196              	.set CYDEV_CAN0_RX8_ACRD, 0x4000a1bc
 3197              	.set CYDEV_CAN0_RX9_BASE, 0x4000a1c0
 3198              	.set CYDEV_CAN0_RX9_SIZE, 0x00000020
 3199              	.set CYDEV_CAN0_RX9_CMD, 0x4000a1c0
 3200              	.set CYDEV_CAN0_RX9_ID, 0x4000a1c4
 3201              	.set CYDEV_CAN0_RX9_DH, 0x4000a1c8
 3202              	.set CYDEV_CAN0_RX9_DL, 0x4000a1cc
 3203              	.set CYDEV_CAN0_RX9_AMR, 0x4000a1d0
 3204              	.set CYDEV_CAN0_RX9_ACR, 0x4000a1d4
 3205              	.set CYDEV_CAN0_RX9_AMRD, 0x4000a1d8
 3206              	.set CYDEV_CAN0_RX9_ACRD, 0x4000a1dc
 3207              	.set CYDEV_CAN0_RX10_BASE, 0x4000a1e0
 3208              	.set CYDEV_CAN0_RX10_SIZE, 0x00000020
 3209              	.set CYDEV_CAN0_RX10_CMD, 0x4000a1e0
 3210              	.set CYDEV_CAN0_RX10_ID, 0x4000a1e4
 3211              	.set CYDEV_CAN0_RX10_DH, 0x4000a1e8
 3212              	.set CYDEV_CAN0_RX10_DL, 0x4000a1ec
 3213              	.set CYDEV_CAN0_RX10_AMR, 0x4000a1f0
 3214              	.set CYDEV_CAN0_RX10_ACR, 0x4000a1f4
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 58


 3215              	.set CYDEV_CAN0_RX10_AMRD, 0x4000a1f8
 3216              	.set CYDEV_CAN0_RX10_ACRD, 0x4000a1fc
 3217              	.set CYDEV_CAN0_RX11_BASE, 0x4000a200
 3218              	.set CYDEV_CAN0_RX11_SIZE, 0x00000020
 3219              	.set CYDEV_CAN0_RX11_CMD, 0x4000a200
 3220              	.set CYDEV_CAN0_RX11_ID, 0x4000a204
 3221              	.set CYDEV_CAN0_RX11_DH, 0x4000a208
 3222              	.set CYDEV_CAN0_RX11_DL, 0x4000a20c
 3223              	.set CYDEV_CAN0_RX11_AMR, 0x4000a210
 3224              	.set CYDEV_CAN0_RX11_ACR, 0x4000a214
 3225              	.set CYDEV_CAN0_RX11_AMRD, 0x4000a218
 3226              	.set CYDEV_CAN0_RX11_ACRD, 0x4000a21c
 3227              	.set CYDEV_CAN0_RX12_BASE, 0x4000a220
 3228              	.set CYDEV_CAN0_RX12_SIZE, 0x00000020
 3229              	.set CYDEV_CAN0_RX12_CMD, 0x4000a220
 3230              	.set CYDEV_CAN0_RX12_ID, 0x4000a224
 3231              	.set CYDEV_CAN0_RX12_DH, 0x4000a228
 3232              	.set CYDEV_CAN0_RX12_DL, 0x4000a22c
 3233              	.set CYDEV_CAN0_RX12_AMR, 0x4000a230
 3234              	.set CYDEV_CAN0_RX12_ACR, 0x4000a234
 3235              	.set CYDEV_CAN0_RX12_AMRD, 0x4000a238
 3236              	.set CYDEV_CAN0_RX12_ACRD, 0x4000a23c
 3237              	.set CYDEV_CAN0_RX13_BASE, 0x4000a240
 3238              	.set CYDEV_CAN0_RX13_SIZE, 0x00000020
 3239              	.set CYDEV_CAN0_RX13_CMD, 0x4000a240
 3240              	.set CYDEV_CAN0_RX13_ID, 0x4000a244
 3241              	.set CYDEV_CAN0_RX13_DH, 0x4000a248
 3242              	.set CYDEV_CAN0_RX13_DL, 0x4000a24c
 3243              	.set CYDEV_CAN0_RX13_AMR, 0x4000a250
 3244              	.set CYDEV_CAN0_RX13_ACR, 0x4000a254
 3245              	.set CYDEV_CAN0_RX13_AMRD, 0x4000a258
 3246              	.set CYDEV_CAN0_RX13_ACRD, 0x4000a25c
 3247              	.set CYDEV_CAN0_RX14_BASE, 0x4000a260
 3248              	.set CYDEV_CAN0_RX14_SIZE, 0x00000020
 3249              	.set CYDEV_CAN0_RX14_CMD, 0x4000a260
 3250              	.set CYDEV_CAN0_RX14_ID, 0x4000a264
 3251              	.set CYDEV_CAN0_RX14_DH, 0x4000a268
 3252              	.set CYDEV_CAN0_RX14_DL, 0x4000a26c
 3253              	.set CYDEV_CAN0_RX14_AMR, 0x4000a270
 3254              	.set CYDEV_CAN0_RX14_ACR, 0x4000a274
 3255              	.set CYDEV_CAN0_RX14_AMRD, 0x4000a278
 3256              	.set CYDEV_CAN0_RX14_ACRD, 0x4000a27c
 3257              	.set CYDEV_CAN0_RX15_BASE, 0x4000a280
 3258              	.set CYDEV_CAN0_RX15_SIZE, 0x00000020
 3259              	.set CYDEV_CAN0_RX15_CMD, 0x4000a280
 3260              	.set CYDEV_CAN0_RX15_ID, 0x4000a284
 3261              	.set CYDEV_CAN0_RX15_DH, 0x4000a288
 3262              	.set CYDEV_CAN0_RX15_DL, 0x4000a28c
 3263              	.set CYDEV_CAN0_RX15_AMR, 0x4000a290
 3264              	.set CYDEV_CAN0_RX15_ACR, 0x4000a294
 3265              	.set CYDEV_CAN0_RX15_AMRD, 0x4000a298
 3266              	.set CYDEV_CAN0_RX15_ACRD, 0x4000a29c
 3267              	.set CYDEV_DFB0_BASE, 0x4000c000
 3268              	.set CYDEV_DFB0_SIZE, 0x000007b5
 3269              	.set CYDEV_DFB0_DPA_SRAM_BASE, 0x4000c000
 3270              	.set CYDEV_DFB0_DPA_SRAM_SIZE, 0x00000200
 3271              	.set CYDEV_DFB0_DPA_SRAM_DATA_MBASE, 0x4000c000
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 59


 3272              	.set CYDEV_DFB0_DPA_SRAM_DATA_MSIZE, 0x00000200
 3273              	.set CYDEV_DFB0_DPB_SRAM_BASE, 0x4000c200
 3274              	.set CYDEV_DFB0_DPB_SRAM_SIZE, 0x00000200
 3275              	.set CYDEV_DFB0_DPB_SRAM_DATA_MBASE, 0x4000c200
 3276              	.set CYDEV_DFB0_DPB_SRAM_DATA_MSIZE, 0x00000200
 3277              	.set CYDEV_DFB0_CSA_SRAM_BASE, 0x4000c400
 3278              	.set CYDEV_DFB0_CSA_SRAM_SIZE, 0x00000100
 3279              	.set CYDEV_DFB0_CSA_SRAM_DATA_MBASE, 0x4000c400
 3280              	.set CYDEV_DFB0_CSA_SRAM_DATA_MSIZE, 0x00000100
 3281              	.set CYDEV_DFB0_CSB_SRAM_BASE, 0x4000c500
 3282              	.set CYDEV_DFB0_CSB_SRAM_SIZE, 0x00000100
 3283              	.set CYDEV_DFB0_CSB_SRAM_DATA_MBASE, 0x4000c500
 3284              	.set CYDEV_DFB0_CSB_SRAM_DATA_MSIZE, 0x00000100
 3285              	.set CYDEV_DFB0_FSM_SRAM_BASE, 0x4000c600
 3286              	.set CYDEV_DFB0_FSM_SRAM_SIZE, 0x00000100
 3287              	.set CYDEV_DFB0_FSM_SRAM_DATA_MBASE, 0x4000c600
 3288              	.set CYDEV_DFB0_FSM_SRAM_DATA_MSIZE, 0x00000100
 3289              	.set CYDEV_DFB0_ACU_SRAM_BASE, 0x4000c700
 3290              	.set CYDEV_DFB0_ACU_SRAM_SIZE, 0x00000040
 3291              	.set CYDEV_DFB0_ACU_SRAM_DATA_MBASE, 0x4000c700
 3292              	.set CYDEV_DFB0_ACU_SRAM_DATA_MSIZE, 0x00000040
 3293              	.set CYDEV_DFB0_CR, 0x4000c780
 3294              	.set CYDEV_DFB0_SR, 0x4000c784
 3295              	.set CYDEV_DFB0_RAM_EN, 0x4000c788
 3296              	.set CYDEV_DFB0_RAM_DIR, 0x4000c78c
 3297              	.set CYDEV_DFB0_SEMA, 0x4000c790
 3298              	.set CYDEV_DFB0_DSI_CTRL, 0x4000c794
 3299              	.set CYDEV_DFB0_INT_CTRL, 0x4000c798
 3300              	.set CYDEV_DFB0_DMA_CTRL, 0x4000c79c
 3301              	.set CYDEV_DFB0_STAGEA, 0x4000c7a0
 3302              	.set CYDEV_DFB0_STAGEAM, 0x4000c7a1
 3303              	.set CYDEV_DFB0_STAGEAH, 0x4000c7a2
 3304              	.set CYDEV_DFB0_STAGEB, 0x4000c7a4
 3305              	.set CYDEV_DFB0_STAGEBM, 0x4000c7a5
 3306              	.set CYDEV_DFB0_STAGEBH, 0x4000c7a6
 3307              	.set CYDEV_DFB0_HOLDA, 0x4000c7a8
 3308              	.set CYDEV_DFB0_HOLDAM, 0x4000c7a9
 3309              	.set CYDEV_DFB0_HOLDAH, 0x4000c7aa
 3310              	.set CYDEV_DFB0_HOLDAS, 0x4000c7ab
 3311              	.set CYDEV_DFB0_HOLDB, 0x4000c7ac
 3312              	.set CYDEV_DFB0_HOLDBM, 0x4000c7ad
 3313              	.set CYDEV_DFB0_HOLDBH, 0x4000c7ae
 3314              	.set CYDEV_DFB0_HOLDBS, 0x4000c7af
 3315              	.set CYDEV_DFB0_COHER, 0x4000c7b0
 3316              	.set CYDEV_DFB0_DALIGN, 0x4000c7b4
 3317              	.set CYDEV_UCFG_BASE, 0x40010000
 3318              	.set CYDEV_UCFG_SIZE, 0x00005040
 3319              	.set CYDEV_UCFG_B0_BASE, 0x40010000
 3320              	.set CYDEV_UCFG_B0_SIZE, 0x00000fef
 3321              	.set CYDEV_UCFG_B0_P0_BASE, 0x40010000
 3322              	.set CYDEV_UCFG_B0_P0_SIZE, 0x000001ef
 3323              	.set CYDEV_UCFG_B0_P0_U0_BASE, 0x40010000
 3324              	.set CYDEV_UCFG_B0_P0_U0_SIZE, 0x00000070
 3325              	.set CYDEV_UCFG_B0_P0_U0_PLD_IT0, 0x40010000
 3326              	.set CYDEV_UCFG_B0_P0_U0_PLD_IT1, 0x40010004
 3327              	.set CYDEV_UCFG_B0_P0_U0_PLD_IT2, 0x40010008
 3328              	.set CYDEV_UCFG_B0_P0_U0_PLD_IT3, 0x4001000c
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 60


 3329              	.set CYDEV_UCFG_B0_P0_U0_PLD_IT4, 0x40010010
 3330              	.set CYDEV_UCFG_B0_P0_U0_PLD_IT5, 0x40010014
 3331              	.set CYDEV_UCFG_B0_P0_U0_PLD_IT6, 0x40010018
 3332              	.set CYDEV_UCFG_B0_P0_U0_PLD_IT7, 0x4001001c
 3333              	.set CYDEV_UCFG_B0_P0_U0_PLD_IT8, 0x40010020
 3334              	.set CYDEV_UCFG_B0_P0_U0_PLD_IT9, 0x40010024
 3335              	.set CYDEV_UCFG_B0_P0_U0_PLD_IT10, 0x40010028
 3336              	.set CYDEV_UCFG_B0_P0_U0_PLD_IT11, 0x4001002c
 3337              	.set CYDEV_UCFG_B0_P0_U0_PLD_ORT0, 0x40010030
 3338              	.set CYDEV_UCFG_B0_P0_U0_PLD_ORT1, 0x40010032
 3339              	.set CYDEV_UCFG_B0_P0_U0_PLD_ORT2, 0x40010034
 3340              	.set CYDEV_UCFG_B0_P0_U0_PLD_ORT3, 0x40010036
 3341              	.set CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST, 0x40010038
 3342              	.set CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB, 0x4001003a
 3343              	.set CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET, 0x4001003c
 3344              	.set CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS, 0x4001003e
 3345              	.set CYDEV_UCFG_B0_P0_U0_CFG0, 0x40010040
 3346              	.set CYDEV_UCFG_B0_P0_U0_CFG1, 0x40010041
 3347              	.set CYDEV_UCFG_B0_P0_U0_CFG2, 0x40010042
 3348              	.set CYDEV_UCFG_B0_P0_U0_CFG3, 0x40010043
 3349              	.set CYDEV_UCFG_B0_P0_U0_CFG4, 0x40010044
 3350              	.set CYDEV_UCFG_B0_P0_U0_CFG5, 0x40010045
 3351              	.set CYDEV_UCFG_B0_P0_U0_CFG6, 0x40010046
 3352              	.set CYDEV_UCFG_B0_P0_U0_CFG7, 0x40010047
 3353              	.set CYDEV_UCFG_B0_P0_U0_CFG8, 0x40010048
 3354              	.set CYDEV_UCFG_B0_P0_U0_CFG9, 0x40010049
 3355              	.set CYDEV_UCFG_B0_P0_U0_CFG10, 0x4001004a
 3356              	.set CYDEV_UCFG_B0_P0_U0_CFG11, 0x4001004b
 3357              	.set CYDEV_UCFG_B0_P0_U0_CFG12, 0x4001004c
 3358              	.set CYDEV_UCFG_B0_P0_U0_CFG13, 0x4001004d
 3359              	.set CYDEV_UCFG_B0_P0_U0_CFG14, 0x4001004e
 3360              	.set CYDEV_UCFG_B0_P0_U0_CFG15, 0x4001004f
 3361              	.set CYDEV_UCFG_B0_P0_U0_CFG16, 0x40010050
 3362              	.set CYDEV_UCFG_B0_P0_U0_CFG17, 0x40010051
 3363              	.set CYDEV_UCFG_B0_P0_U0_CFG18, 0x40010052
 3364              	.set CYDEV_UCFG_B0_P0_U0_CFG19, 0x40010053
 3365              	.set CYDEV_UCFG_B0_P0_U0_CFG20, 0x40010054
 3366              	.set CYDEV_UCFG_B0_P0_U0_CFG21, 0x40010055
 3367              	.set CYDEV_UCFG_B0_P0_U0_CFG22, 0x40010056
 3368              	.set CYDEV_UCFG_B0_P0_U0_CFG23, 0x40010057
 3369              	.set CYDEV_UCFG_B0_P0_U0_CFG24, 0x40010058
 3370              	.set CYDEV_UCFG_B0_P0_U0_CFG25, 0x40010059
 3371              	.set CYDEV_UCFG_B0_P0_U0_CFG26, 0x4001005a
 3372              	.set CYDEV_UCFG_B0_P0_U0_CFG27, 0x4001005b
 3373              	.set CYDEV_UCFG_B0_P0_U0_CFG28, 0x4001005c
 3374              	.set CYDEV_UCFG_B0_P0_U0_CFG29, 0x4001005d
 3375              	.set CYDEV_UCFG_B0_P0_U0_CFG30, 0x4001005e
 3376              	.set CYDEV_UCFG_B0_P0_U0_CFG31, 0x4001005f
 3377              	.set CYDEV_UCFG_B0_P0_U0_DCFG0, 0x40010060
 3378              	.set CYDEV_UCFG_B0_P0_U0_DCFG1, 0x40010062
 3379              	.set CYDEV_UCFG_B0_P0_U0_DCFG2, 0x40010064
 3380              	.set CYDEV_UCFG_B0_P0_U0_DCFG3, 0x40010066
 3381              	.set CYDEV_UCFG_B0_P0_U0_DCFG4, 0x40010068
 3382              	.set CYDEV_UCFG_B0_P0_U0_DCFG5, 0x4001006a
 3383              	.set CYDEV_UCFG_B0_P0_U0_DCFG6, 0x4001006c
 3384              	.set CYDEV_UCFG_B0_P0_U0_DCFG7, 0x4001006e
 3385              	.set CYDEV_UCFG_B0_P0_U1_BASE, 0x40010080
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 61


 3386              	.set CYDEV_UCFG_B0_P0_U1_SIZE, 0x00000070
 3387              	.set CYDEV_UCFG_B0_P0_U1_PLD_IT0, 0x40010080
 3388              	.set CYDEV_UCFG_B0_P0_U1_PLD_IT1, 0x40010084
 3389              	.set CYDEV_UCFG_B0_P0_U1_PLD_IT2, 0x40010088
 3390              	.set CYDEV_UCFG_B0_P0_U1_PLD_IT3, 0x4001008c
 3391              	.set CYDEV_UCFG_B0_P0_U1_PLD_IT4, 0x40010090
 3392              	.set CYDEV_UCFG_B0_P0_U1_PLD_IT5, 0x40010094
 3393              	.set CYDEV_UCFG_B0_P0_U1_PLD_IT6, 0x40010098
 3394              	.set CYDEV_UCFG_B0_P0_U1_PLD_IT7, 0x4001009c
 3395              	.set CYDEV_UCFG_B0_P0_U1_PLD_IT8, 0x400100a0
 3396              	.set CYDEV_UCFG_B0_P0_U1_PLD_IT9, 0x400100a4
 3397              	.set CYDEV_UCFG_B0_P0_U1_PLD_IT10, 0x400100a8
 3398              	.set CYDEV_UCFG_B0_P0_U1_PLD_IT11, 0x400100ac
 3399              	.set CYDEV_UCFG_B0_P0_U1_PLD_ORT0, 0x400100b0
 3400              	.set CYDEV_UCFG_B0_P0_U1_PLD_ORT1, 0x400100b2
 3401              	.set CYDEV_UCFG_B0_P0_U1_PLD_ORT2, 0x400100b4
 3402              	.set CYDEV_UCFG_B0_P0_U1_PLD_ORT3, 0x400100b6
 3403              	.set CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST, 0x400100b8
 3404              	.set CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB, 0x400100ba
 3405              	.set CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET, 0x400100bc
 3406              	.set CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS, 0x400100be
 3407              	.set CYDEV_UCFG_B0_P0_U1_CFG0, 0x400100c0
 3408              	.set CYDEV_UCFG_B0_P0_U1_CFG1, 0x400100c1
 3409              	.set CYDEV_UCFG_B0_P0_U1_CFG2, 0x400100c2
 3410              	.set CYDEV_UCFG_B0_P0_U1_CFG3, 0x400100c3
 3411              	.set CYDEV_UCFG_B0_P0_U1_CFG4, 0x400100c4
 3412              	.set CYDEV_UCFG_B0_P0_U1_CFG5, 0x400100c5
 3413              	.set CYDEV_UCFG_B0_P0_U1_CFG6, 0x400100c6
 3414              	.set CYDEV_UCFG_B0_P0_U1_CFG7, 0x400100c7
 3415              	.set CYDEV_UCFG_B0_P0_U1_CFG8, 0x400100c8
 3416              	.set CYDEV_UCFG_B0_P0_U1_CFG9, 0x400100c9
 3417              	.set CYDEV_UCFG_B0_P0_U1_CFG10, 0x400100ca
 3418              	.set CYDEV_UCFG_B0_P0_U1_CFG11, 0x400100cb
 3419              	.set CYDEV_UCFG_B0_P0_U1_CFG12, 0x400100cc
 3420              	.set CYDEV_UCFG_B0_P0_U1_CFG13, 0x400100cd
 3421              	.set CYDEV_UCFG_B0_P0_U1_CFG14, 0x400100ce
 3422              	.set CYDEV_UCFG_B0_P0_U1_CFG15, 0x400100cf
 3423              	.set CYDEV_UCFG_B0_P0_U1_CFG16, 0x400100d0
 3424              	.set CYDEV_UCFG_B0_P0_U1_CFG17, 0x400100d1
 3425              	.set CYDEV_UCFG_B0_P0_U1_CFG18, 0x400100d2
 3426              	.set CYDEV_UCFG_B0_P0_U1_CFG19, 0x400100d3
 3427              	.set CYDEV_UCFG_B0_P0_U1_CFG20, 0x400100d4
 3428              	.set CYDEV_UCFG_B0_P0_U1_CFG21, 0x400100d5
 3429              	.set CYDEV_UCFG_B0_P0_U1_CFG22, 0x400100d6
 3430              	.set CYDEV_UCFG_B0_P0_U1_CFG23, 0x400100d7
 3431              	.set CYDEV_UCFG_B0_P0_U1_CFG24, 0x400100d8
 3432              	.set CYDEV_UCFG_B0_P0_U1_CFG25, 0x400100d9
 3433              	.set CYDEV_UCFG_B0_P0_U1_CFG26, 0x400100da
 3434              	.set CYDEV_UCFG_B0_P0_U1_CFG27, 0x400100db
 3435              	.set CYDEV_UCFG_B0_P0_U1_CFG28, 0x400100dc
 3436              	.set CYDEV_UCFG_B0_P0_U1_CFG29, 0x400100dd
 3437              	.set CYDEV_UCFG_B0_P0_U1_CFG30, 0x400100de
 3438              	.set CYDEV_UCFG_B0_P0_U1_CFG31, 0x400100df
 3439              	.set CYDEV_UCFG_B0_P0_U1_DCFG0, 0x400100e0
 3440              	.set CYDEV_UCFG_B0_P0_U1_DCFG1, 0x400100e2
 3441              	.set CYDEV_UCFG_B0_P0_U1_DCFG2, 0x400100e4
 3442              	.set CYDEV_UCFG_B0_P0_U1_DCFG3, 0x400100e6
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 62


 3443              	.set CYDEV_UCFG_B0_P0_U1_DCFG4, 0x400100e8
 3444              	.set CYDEV_UCFG_B0_P0_U1_DCFG5, 0x400100ea
 3445              	.set CYDEV_UCFG_B0_P0_U1_DCFG6, 0x400100ec
 3446              	.set CYDEV_UCFG_B0_P0_U1_DCFG7, 0x400100ee
 3447              	.set CYDEV_UCFG_B0_P0_ROUTE_BASE, 0x40010100
 3448              	.set CYDEV_UCFG_B0_P0_ROUTE_SIZE, 0x000000ef
 3449              	.set CYDEV_UCFG_B0_P1_BASE, 0x40010200
 3450              	.set CYDEV_UCFG_B0_P1_SIZE, 0x000001ef
 3451              	.set CYDEV_UCFG_B0_P1_U0_BASE, 0x40010200
 3452              	.set CYDEV_UCFG_B0_P1_U0_SIZE, 0x00000070
 3453              	.set CYDEV_UCFG_B0_P1_U0_PLD_IT0, 0x40010200
 3454              	.set CYDEV_UCFG_B0_P1_U0_PLD_IT1, 0x40010204
 3455              	.set CYDEV_UCFG_B0_P1_U0_PLD_IT2, 0x40010208
 3456              	.set CYDEV_UCFG_B0_P1_U0_PLD_IT3, 0x4001020c
 3457              	.set CYDEV_UCFG_B0_P1_U0_PLD_IT4, 0x40010210
 3458              	.set CYDEV_UCFG_B0_P1_U0_PLD_IT5, 0x40010214
 3459              	.set CYDEV_UCFG_B0_P1_U0_PLD_IT6, 0x40010218
 3460              	.set CYDEV_UCFG_B0_P1_U0_PLD_IT7, 0x4001021c
 3461              	.set CYDEV_UCFG_B0_P1_U0_PLD_IT8, 0x40010220
 3462              	.set CYDEV_UCFG_B0_P1_U0_PLD_IT9, 0x40010224
 3463              	.set CYDEV_UCFG_B0_P1_U0_PLD_IT10, 0x40010228
 3464              	.set CYDEV_UCFG_B0_P1_U0_PLD_IT11, 0x4001022c
 3465              	.set CYDEV_UCFG_B0_P1_U0_PLD_ORT0, 0x40010230
 3466              	.set CYDEV_UCFG_B0_P1_U0_PLD_ORT1, 0x40010232
 3467              	.set CYDEV_UCFG_B0_P1_U0_PLD_ORT2, 0x40010234
 3468              	.set CYDEV_UCFG_B0_P1_U0_PLD_ORT3, 0x40010236
 3469              	.set CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST, 0x40010238
 3470              	.set CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB, 0x4001023a
 3471              	.set CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET, 0x4001023c
 3472              	.set CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS, 0x4001023e
 3473              	.set CYDEV_UCFG_B0_P1_U0_CFG0, 0x40010240
 3474              	.set CYDEV_UCFG_B0_P1_U0_CFG1, 0x40010241
 3475              	.set CYDEV_UCFG_B0_P1_U0_CFG2, 0x40010242
 3476              	.set CYDEV_UCFG_B0_P1_U0_CFG3, 0x40010243
 3477              	.set CYDEV_UCFG_B0_P1_U0_CFG4, 0x40010244
 3478              	.set CYDEV_UCFG_B0_P1_U0_CFG5, 0x40010245
 3479              	.set CYDEV_UCFG_B0_P1_U0_CFG6, 0x40010246
 3480              	.set CYDEV_UCFG_B0_P1_U0_CFG7, 0x40010247
 3481              	.set CYDEV_UCFG_B0_P1_U0_CFG8, 0x40010248
 3482              	.set CYDEV_UCFG_B0_P1_U0_CFG9, 0x40010249
 3483              	.set CYDEV_UCFG_B0_P1_U0_CFG10, 0x4001024a
 3484              	.set CYDEV_UCFG_B0_P1_U0_CFG11, 0x4001024b
 3485              	.set CYDEV_UCFG_B0_P1_U0_CFG12, 0x4001024c
 3486              	.set CYDEV_UCFG_B0_P1_U0_CFG13, 0x4001024d
 3487              	.set CYDEV_UCFG_B0_P1_U0_CFG14, 0x4001024e
 3488              	.set CYDEV_UCFG_B0_P1_U0_CFG15, 0x4001024f
 3489              	.set CYDEV_UCFG_B0_P1_U0_CFG16, 0x40010250
 3490              	.set CYDEV_UCFG_B0_P1_U0_CFG17, 0x40010251
 3491              	.set CYDEV_UCFG_B0_P1_U0_CFG18, 0x40010252
 3492              	.set CYDEV_UCFG_B0_P1_U0_CFG19, 0x40010253
 3493              	.set CYDEV_UCFG_B0_P1_U0_CFG20, 0x40010254
 3494              	.set CYDEV_UCFG_B0_P1_U0_CFG21, 0x40010255
 3495              	.set CYDEV_UCFG_B0_P1_U0_CFG22, 0x40010256
 3496              	.set CYDEV_UCFG_B0_P1_U0_CFG23, 0x40010257
 3497              	.set CYDEV_UCFG_B0_P1_U0_CFG24, 0x40010258
 3498              	.set CYDEV_UCFG_B0_P1_U0_CFG25, 0x40010259
 3499              	.set CYDEV_UCFG_B0_P1_U0_CFG26, 0x4001025a
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 63


 3500              	.set CYDEV_UCFG_B0_P1_U0_CFG27, 0x4001025b
 3501              	.set CYDEV_UCFG_B0_P1_U0_CFG28, 0x4001025c
 3502              	.set CYDEV_UCFG_B0_P1_U0_CFG29, 0x4001025d
 3503              	.set CYDEV_UCFG_B0_P1_U0_CFG30, 0x4001025e
 3504              	.set CYDEV_UCFG_B0_P1_U0_CFG31, 0x4001025f
 3505              	.set CYDEV_UCFG_B0_P1_U0_DCFG0, 0x40010260
 3506              	.set CYDEV_UCFG_B0_P1_U0_DCFG1, 0x40010262
 3507              	.set CYDEV_UCFG_B0_P1_U0_DCFG2, 0x40010264
 3508              	.set CYDEV_UCFG_B0_P1_U0_DCFG3, 0x40010266
 3509              	.set CYDEV_UCFG_B0_P1_U0_DCFG4, 0x40010268
 3510              	.set CYDEV_UCFG_B0_P1_U0_DCFG5, 0x4001026a
 3511              	.set CYDEV_UCFG_B0_P1_U0_DCFG6, 0x4001026c
 3512              	.set CYDEV_UCFG_B0_P1_U0_DCFG7, 0x4001026e
 3513              	.set CYDEV_UCFG_B0_P1_U1_BASE, 0x40010280
 3514              	.set CYDEV_UCFG_B0_P1_U1_SIZE, 0x00000070
 3515              	.set CYDEV_UCFG_B0_P1_U1_PLD_IT0, 0x40010280
 3516              	.set CYDEV_UCFG_B0_P1_U1_PLD_IT1, 0x40010284
 3517              	.set CYDEV_UCFG_B0_P1_U1_PLD_IT2, 0x40010288
 3518              	.set CYDEV_UCFG_B0_P1_U1_PLD_IT3, 0x4001028c
 3519              	.set CYDEV_UCFG_B0_P1_U1_PLD_IT4, 0x40010290
 3520              	.set CYDEV_UCFG_B0_P1_U1_PLD_IT5, 0x40010294
 3521              	.set CYDEV_UCFG_B0_P1_U1_PLD_IT6, 0x40010298
 3522              	.set CYDEV_UCFG_B0_P1_U1_PLD_IT7, 0x4001029c
 3523              	.set CYDEV_UCFG_B0_P1_U1_PLD_IT8, 0x400102a0
 3524              	.set CYDEV_UCFG_B0_P1_U1_PLD_IT9, 0x400102a4
 3525              	.set CYDEV_UCFG_B0_P1_U1_PLD_IT10, 0x400102a8
 3526              	.set CYDEV_UCFG_B0_P1_U1_PLD_IT11, 0x400102ac
 3527              	.set CYDEV_UCFG_B0_P1_U1_PLD_ORT0, 0x400102b0
 3528              	.set CYDEV_UCFG_B0_P1_U1_PLD_ORT1, 0x400102b2
 3529              	.set CYDEV_UCFG_B0_P1_U1_PLD_ORT2, 0x400102b4
 3530              	.set CYDEV_UCFG_B0_P1_U1_PLD_ORT3, 0x400102b6
 3531              	.set CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST, 0x400102b8
 3532              	.set CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB, 0x400102ba
 3533              	.set CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET, 0x400102bc
 3534              	.set CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS, 0x400102be
 3535              	.set CYDEV_UCFG_B0_P1_U1_CFG0, 0x400102c0
 3536              	.set CYDEV_UCFG_B0_P1_U1_CFG1, 0x400102c1
 3537              	.set CYDEV_UCFG_B0_P1_U1_CFG2, 0x400102c2
 3538              	.set CYDEV_UCFG_B0_P1_U1_CFG3, 0x400102c3
 3539              	.set CYDEV_UCFG_B0_P1_U1_CFG4, 0x400102c4
 3540              	.set CYDEV_UCFG_B0_P1_U1_CFG5, 0x400102c5
 3541              	.set CYDEV_UCFG_B0_P1_U1_CFG6, 0x400102c6
 3542              	.set CYDEV_UCFG_B0_P1_U1_CFG7, 0x400102c7
 3543              	.set CYDEV_UCFG_B0_P1_U1_CFG8, 0x400102c8
 3544              	.set CYDEV_UCFG_B0_P1_U1_CFG9, 0x400102c9
 3545              	.set CYDEV_UCFG_B0_P1_U1_CFG10, 0x400102ca
 3546              	.set CYDEV_UCFG_B0_P1_U1_CFG11, 0x400102cb
 3547              	.set CYDEV_UCFG_B0_P1_U1_CFG12, 0x400102cc
 3548              	.set CYDEV_UCFG_B0_P1_U1_CFG13, 0x400102cd
 3549              	.set CYDEV_UCFG_B0_P1_U1_CFG14, 0x400102ce
 3550              	.set CYDEV_UCFG_B0_P1_U1_CFG15, 0x400102cf
 3551              	.set CYDEV_UCFG_B0_P1_U1_CFG16, 0x400102d0
 3552              	.set CYDEV_UCFG_B0_P1_U1_CFG17, 0x400102d1
 3553              	.set CYDEV_UCFG_B0_P1_U1_CFG18, 0x400102d2
 3554              	.set CYDEV_UCFG_B0_P1_U1_CFG19, 0x400102d3
 3555              	.set CYDEV_UCFG_B0_P1_U1_CFG20, 0x400102d4
 3556              	.set CYDEV_UCFG_B0_P1_U1_CFG21, 0x400102d5
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 64


 3557              	.set CYDEV_UCFG_B0_P1_U1_CFG22, 0x400102d6
 3558              	.set CYDEV_UCFG_B0_P1_U1_CFG23, 0x400102d7
 3559              	.set CYDEV_UCFG_B0_P1_U1_CFG24, 0x400102d8
 3560              	.set CYDEV_UCFG_B0_P1_U1_CFG25, 0x400102d9
 3561              	.set CYDEV_UCFG_B0_P1_U1_CFG26, 0x400102da
 3562              	.set CYDEV_UCFG_B0_P1_U1_CFG27, 0x400102db
 3563              	.set CYDEV_UCFG_B0_P1_U1_CFG28, 0x400102dc
 3564              	.set CYDEV_UCFG_B0_P1_U1_CFG29, 0x400102dd
 3565              	.set CYDEV_UCFG_B0_P1_U1_CFG30, 0x400102de
 3566              	.set CYDEV_UCFG_B0_P1_U1_CFG31, 0x400102df
 3567              	.set CYDEV_UCFG_B0_P1_U1_DCFG0, 0x400102e0
 3568              	.set CYDEV_UCFG_B0_P1_U1_DCFG1, 0x400102e2
 3569              	.set CYDEV_UCFG_B0_P1_U1_DCFG2, 0x400102e4
 3570              	.set CYDEV_UCFG_B0_P1_U1_DCFG3, 0x400102e6
 3571              	.set CYDEV_UCFG_B0_P1_U1_DCFG4, 0x400102e8
 3572              	.set CYDEV_UCFG_B0_P1_U1_DCFG5, 0x400102ea
 3573              	.set CYDEV_UCFG_B0_P1_U1_DCFG6, 0x400102ec
 3574              	.set CYDEV_UCFG_B0_P1_U1_DCFG7, 0x400102ee
 3575              	.set CYDEV_UCFG_B0_P1_ROUTE_BASE, 0x40010300
 3576              	.set CYDEV_UCFG_B0_P1_ROUTE_SIZE, 0x000000ef
 3577              	.set CYDEV_UCFG_B0_P2_BASE, 0x40010400
 3578              	.set CYDEV_UCFG_B0_P2_SIZE, 0x000001ef
 3579              	.set CYDEV_UCFG_B0_P2_U0_BASE, 0x40010400
 3580              	.set CYDEV_UCFG_B0_P2_U0_SIZE, 0x00000070
 3581              	.set CYDEV_UCFG_B0_P2_U0_PLD_IT0, 0x40010400
 3582              	.set CYDEV_UCFG_B0_P2_U0_PLD_IT1, 0x40010404
 3583              	.set CYDEV_UCFG_B0_P2_U0_PLD_IT2, 0x40010408
 3584              	.set CYDEV_UCFG_B0_P2_U0_PLD_IT3, 0x4001040c
 3585              	.set CYDEV_UCFG_B0_P2_U0_PLD_IT4, 0x40010410
 3586              	.set CYDEV_UCFG_B0_P2_U0_PLD_IT5, 0x40010414
 3587              	.set CYDEV_UCFG_B0_P2_U0_PLD_IT6, 0x40010418
 3588              	.set CYDEV_UCFG_B0_P2_U0_PLD_IT7, 0x4001041c
 3589              	.set CYDEV_UCFG_B0_P2_U0_PLD_IT8, 0x40010420
 3590              	.set CYDEV_UCFG_B0_P2_U0_PLD_IT9, 0x40010424
 3591              	.set CYDEV_UCFG_B0_P2_U0_PLD_IT10, 0x40010428
 3592              	.set CYDEV_UCFG_B0_P2_U0_PLD_IT11, 0x4001042c
 3593              	.set CYDEV_UCFG_B0_P2_U0_PLD_ORT0, 0x40010430
 3594              	.set CYDEV_UCFG_B0_P2_U0_PLD_ORT1, 0x40010432
 3595              	.set CYDEV_UCFG_B0_P2_U0_PLD_ORT2, 0x40010434
 3596              	.set CYDEV_UCFG_B0_P2_U0_PLD_ORT3, 0x40010436
 3597              	.set CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST, 0x40010438
 3598              	.set CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB, 0x4001043a
 3599              	.set CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET, 0x4001043c
 3600              	.set CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS, 0x4001043e
 3601              	.set CYDEV_UCFG_B0_P2_U0_CFG0, 0x40010440
 3602              	.set CYDEV_UCFG_B0_P2_U0_CFG1, 0x40010441
 3603              	.set CYDEV_UCFG_B0_P2_U0_CFG2, 0x40010442
 3604              	.set CYDEV_UCFG_B0_P2_U0_CFG3, 0x40010443
 3605              	.set CYDEV_UCFG_B0_P2_U0_CFG4, 0x40010444
 3606              	.set CYDEV_UCFG_B0_P2_U0_CFG5, 0x40010445
 3607              	.set CYDEV_UCFG_B0_P2_U0_CFG6, 0x40010446
 3608              	.set CYDEV_UCFG_B0_P2_U0_CFG7, 0x40010447
 3609              	.set CYDEV_UCFG_B0_P2_U0_CFG8, 0x40010448
 3610              	.set CYDEV_UCFG_B0_P2_U0_CFG9, 0x40010449
 3611              	.set CYDEV_UCFG_B0_P2_U0_CFG10, 0x4001044a
 3612              	.set CYDEV_UCFG_B0_P2_U0_CFG11, 0x4001044b
 3613              	.set CYDEV_UCFG_B0_P2_U0_CFG12, 0x4001044c
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 65


 3614              	.set CYDEV_UCFG_B0_P2_U0_CFG13, 0x4001044d
 3615              	.set CYDEV_UCFG_B0_P2_U0_CFG14, 0x4001044e
 3616              	.set CYDEV_UCFG_B0_P2_U0_CFG15, 0x4001044f
 3617              	.set CYDEV_UCFG_B0_P2_U0_CFG16, 0x40010450
 3618              	.set CYDEV_UCFG_B0_P2_U0_CFG17, 0x40010451
 3619              	.set CYDEV_UCFG_B0_P2_U0_CFG18, 0x40010452
 3620              	.set CYDEV_UCFG_B0_P2_U0_CFG19, 0x40010453
 3621              	.set CYDEV_UCFG_B0_P2_U0_CFG20, 0x40010454
 3622              	.set CYDEV_UCFG_B0_P2_U0_CFG21, 0x40010455
 3623              	.set CYDEV_UCFG_B0_P2_U0_CFG22, 0x40010456
 3624              	.set CYDEV_UCFG_B0_P2_U0_CFG23, 0x40010457
 3625              	.set CYDEV_UCFG_B0_P2_U0_CFG24, 0x40010458
 3626              	.set CYDEV_UCFG_B0_P2_U0_CFG25, 0x40010459
 3627              	.set CYDEV_UCFG_B0_P2_U0_CFG26, 0x4001045a
 3628              	.set CYDEV_UCFG_B0_P2_U0_CFG27, 0x4001045b
 3629              	.set CYDEV_UCFG_B0_P2_U0_CFG28, 0x4001045c
 3630              	.set CYDEV_UCFG_B0_P2_U0_CFG29, 0x4001045d
 3631              	.set CYDEV_UCFG_B0_P2_U0_CFG30, 0x4001045e
 3632              	.set CYDEV_UCFG_B0_P2_U0_CFG31, 0x4001045f
 3633              	.set CYDEV_UCFG_B0_P2_U0_DCFG0, 0x40010460
 3634              	.set CYDEV_UCFG_B0_P2_U0_DCFG1, 0x40010462
 3635              	.set CYDEV_UCFG_B0_P2_U0_DCFG2, 0x40010464
 3636              	.set CYDEV_UCFG_B0_P2_U0_DCFG3, 0x40010466
 3637              	.set CYDEV_UCFG_B0_P2_U0_DCFG4, 0x40010468
 3638              	.set CYDEV_UCFG_B0_P2_U0_DCFG5, 0x4001046a
 3639              	.set CYDEV_UCFG_B0_P2_U0_DCFG6, 0x4001046c
 3640              	.set CYDEV_UCFG_B0_P2_U0_DCFG7, 0x4001046e
 3641              	.set CYDEV_UCFG_B0_P2_U1_BASE, 0x40010480
 3642              	.set CYDEV_UCFG_B0_P2_U1_SIZE, 0x00000070
 3643              	.set CYDEV_UCFG_B0_P2_U1_PLD_IT0, 0x40010480
 3644              	.set CYDEV_UCFG_B0_P2_U1_PLD_IT1, 0x40010484
 3645              	.set CYDEV_UCFG_B0_P2_U1_PLD_IT2, 0x40010488
 3646              	.set CYDEV_UCFG_B0_P2_U1_PLD_IT3, 0x4001048c
 3647              	.set CYDEV_UCFG_B0_P2_U1_PLD_IT4, 0x40010490
 3648              	.set CYDEV_UCFG_B0_P2_U1_PLD_IT5, 0x40010494
 3649              	.set CYDEV_UCFG_B0_P2_U1_PLD_IT6, 0x40010498
 3650              	.set CYDEV_UCFG_B0_P2_U1_PLD_IT7, 0x4001049c
 3651              	.set CYDEV_UCFG_B0_P2_U1_PLD_IT8, 0x400104a0
 3652              	.set CYDEV_UCFG_B0_P2_U1_PLD_IT9, 0x400104a4
 3653              	.set CYDEV_UCFG_B0_P2_U1_PLD_IT10, 0x400104a8
 3654              	.set CYDEV_UCFG_B0_P2_U1_PLD_IT11, 0x400104ac
 3655              	.set CYDEV_UCFG_B0_P2_U1_PLD_ORT0, 0x400104b0
 3656              	.set CYDEV_UCFG_B0_P2_U1_PLD_ORT1, 0x400104b2
 3657              	.set CYDEV_UCFG_B0_P2_U1_PLD_ORT2, 0x400104b4
 3658              	.set CYDEV_UCFG_B0_P2_U1_PLD_ORT3, 0x400104b6
 3659              	.set CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST, 0x400104b8
 3660              	.set CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB, 0x400104ba
 3661              	.set CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET, 0x400104bc
 3662              	.set CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS, 0x400104be
 3663              	.set CYDEV_UCFG_B0_P2_U1_CFG0, 0x400104c0
 3664              	.set CYDEV_UCFG_B0_P2_U1_CFG1, 0x400104c1
 3665              	.set CYDEV_UCFG_B0_P2_U1_CFG2, 0x400104c2
 3666              	.set CYDEV_UCFG_B0_P2_U1_CFG3, 0x400104c3
 3667              	.set CYDEV_UCFG_B0_P2_U1_CFG4, 0x400104c4
 3668              	.set CYDEV_UCFG_B0_P2_U1_CFG5, 0x400104c5
 3669              	.set CYDEV_UCFG_B0_P2_U1_CFG6, 0x400104c6
 3670              	.set CYDEV_UCFG_B0_P2_U1_CFG7, 0x400104c7
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 66


 3671              	.set CYDEV_UCFG_B0_P2_U1_CFG8, 0x400104c8
 3672              	.set CYDEV_UCFG_B0_P2_U1_CFG9, 0x400104c9
 3673              	.set CYDEV_UCFG_B0_P2_U1_CFG10, 0x400104ca
 3674              	.set CYDEV_UCFG_B0_P2_U1_CFG11, 0x400104cb
 3675              	.set CYDEV_UCFG_B0_P2_U1_CFG12, 0x400104cc
 3676              	.set CYDEV_UCFG_B0_P2_U1_CFG13, 0x400104cd
 3677              	.set CYDEV_UCFG_B0_P2_U1_CFG14, 0x400104ce
 3678              	.set CYDEV_UCFG_B0_P2_U1_CFG15, 0x400104cf
 3679              	.set CYDEV_UCFG_B0_P2_U1_CFG16, 0x400104d0
 3680              	.set CYDEV_UCFG_B0_P2_U1_CFG17, 0x400104d1
 3681              	.set CYDEV_UCFG_B0_P2_U1_CFG18, 0x400104d2
 3682              	.set CYDEV_UCFG_B0_P2_U1_CFG19, 0x400104d3
 3683              	.set CYDEV_UCFG_B0_P2_U1_CFG20, 0x400104d4
 3684              	.set CYDEV_UCFG_B0_P2_U1_CFG21, 0x400104d5
 3685              	.set CYDEV_UCFG_B0_P2_U1_CFG22, 0x400104d6
 3686              	.set CYDEV_UCFG_B0_P2_U1_CFG23, 0x400104d7
 3687              	.set CYDEV_UCFG_B0_P2_U1_CFG24, 0x400104d8
 3688              	.set CYDEV_UCFG_B0_P2_U1_CFG25, 0x400104d9
 3689              	.set CYDEV_UCFG_B0_P2_U1_CFG26, 0x400104da
 3690              	.set CYDEV_UCFG_B0_P2_U1_CFG27, 0x400104db
 3691              	.set CYDEV_UCFG_B0_P2_U1_CFG28, 0x400104dc
 3692              	.set CYDEV_UCFG_B0_P2_U1_CFG29, 0x400104dd
 3693              	.set CYDEV_UCFG_B0_P2_U1_CFG30, 0x400104de
 3694              	.set CYDEV_UCFG_B0_P2_U1_CFG31, 0x400104df
 3695              	.set CYDEV_UCFG_B0_P2_U1_DCFG0, 0x400104e0
 3696              	.set CYDEV_UCFG_B0_P2_U1_DCFG1, 0x400104e2
 3697              	.set CYDEV_UCFG_B0_P2_U1_DCFG2, 0x400104e4
 3698              	.set CYDEV_UCFG_B0_P2_U1_DCFG3, 0x400104e6
 3699              	.set CYDEV_UCFG_B0_P2_U1_DCFG4, 0x400104e8
 3700              	.set CYDEV_UCFG_B0_P2_U1_DCFG5, 0x400104ea
 3701              	.set CYDEV_UCFG_B0_P2_U1_DCFG6, 0x400104ec
 3702              	.set CYDEV_UCFG_B0_P2_U1_DCFG7, 0x400104ee
 3703              	.set CYDEV_UCFG_B0_P2_ROUTE_BASE, 0x40010500
 3704              	.set CYDEV_UCFG_B0_P2_ROUTE_SIZE, 0x000000ef
 3705              	.set CYDEV_UCFG_B0_P3_BASE, 0x40010600
 3706              	.set CYDEV_UCFG_B0_P3_SIZE, 0x000001ef
 3707              	.set CYDEV_UCFG_B0_P3_U0_BASE, 0x40010600
 3708              	.set CYDEV_UCFG_B0_P3_U0_SIZE, 0x00000070
 3709              	.set CYDEV_UCFG_B0_P3_U0_PLD_IT0, 0x40010600
 3710              	.set CYDEV_UCFG_B0_P3_U0_PLD_IT1, 0x40010604
 3711              	.set CYDEV_UCFG_B0_P3_U0_PLD_IT2, 0x40010608
 3712              	.set CYDEV_UCFG_B0_P3_U0_PLD_IT3, 0x4001060c
 3713              	.set CYDEV_UCFG_B0_P3_U0_PLD_IT4, 0x40010610
 3714              	.set CYDEV_UCFG_B0_P3_U0_PLD_IT5, 0x40010614
 3715              	.set CYDEV_UCFG_B0_P3_U0_PLD_IT6, 0x40010618
 3716              	.set CYDEV_UCFG_B0_P3_U0_PLD_IT7, 0x4001061c
 3717              	.set CYDEV_UCFG_B0_P3_U0_PLD_IT8, 0x40010620
 3718              	.set CYDEV_UCFG_B0_P3_U0_PLD_IT9, 0x40010624
 3719              	.set CYDEV_UCFG_B0_P3_U0_PLD_IT10, 0x40010628
 3720              	.set CYDEV_UCFG_B0_P3_U0_PLD_IT11, 0x4001062c
 3721              	.set CYDEV_UCFG_B0_P3_U0_PLD_ORT0, 0x40010630
 3722              	.set CYDEV_UCFG_B0_P3_U0_PLD_ORT1, 0x40010632
 3723              	.set CYDEV_UCFG_B0_P3_U0_PLD_ORT2, 0x40010634
 3724              	.set CYDEV_UCFG_B0_P3_U0_PLD_ORT3, 0x40010636
 3725              	.set CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST, 0x40010638
 3726              	.set CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB, 0x4001063a
 3727              	.set CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET, 0x4001063c
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 67


 3728              	.set CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS, 0x4001063e
 3729              	.set CYDEV_UCFG_B0_P3_U0_CFG0, 0x40010640
 3730              	.set CYDEV_UCFG_B0_P3_U0_CFG1, 0x40010641
 3731              	.set CYDEV_UCFG_B0_P3_U0_CFG2, 0x40010642
 3732              	.set CYDEV_UCFG_B0_P3_U0_CFG3, 0x40010643
 3733              	.set CYDEV_UCFG_B0_P3_U0_CFG4, 0x40010644
 3734              	.set CYDEV_UCFG_B0_P3_U0_CFG5, 0x40010645
 3735              	.set CYDEV_UCFG_B0_P3_U0_CFG6, 0x40010646
 3736              	.set CYDEV_UCFG_B0_P3_U0_CFG7, 0x40010647
 3737              	.set CYDEV_UCFG_B0_P3_U0_CFG8, 0x40010648
 3738              	.set CYDEV_UCFG_B0_P3_U0_CFG9, 0x40010649
 3739              	.set CYDEV_UCFG_B0_P3_U0_CFG10, 0x4001064a
 3740              	.set CYDEV_UCFG_B0_P3_U0_CFG11, 0x4001064b
 3741              	.set CYDEV_UCFG_B0_P3_U0_CFG12, 0x4001064c
 3742              	.set CYDEV_UCFG_B0_P3_U0_CFG13, 0x4001064d
 3743              	.set CYDEV_UCFG_B0_P3_U0_CFG14, 0x4001064e
 3744              	.set CYDEV_UCFG_B0_P3_U0_CFG15, 0x4001064f
 3745              	.set CYDEV_UCFG_B0_P3_U0_CFG16, 0x40010650
 3746              	.set CYDEV_UCFG_B0_P3_U0_CFG17, 0x40010651
 3747              	.set CYDEV_UCFG_B0_P3_U0_CFG18, 0x40010652
 3748              	.set CYDEV_UCFG_B0_P3_U0_CFG19, 0x40010653
 3749              	.set CYDEV_UCFG_B0_P3_U0_CFG20, 0x40010654
 3750              	.set CYDEV_UCFG_B0_P3_U0_CFG21, 0x40010655
 3751              	.set CYDEV_UCFG_B0_P3_U0_CFG22, 0x40010656
 3752              	.set CYDEV_UCFG_B0_P3_U0_CFG23, 0x40010657
 3753              	.set CYDEV_UCFG_B0_P3_U0_CFG24, 0x40010658
 3754              	.set CYDEV_UCFG_B0_P3_U0_CFG25, 0x40010659
 3755              	.set CYDEV_UCFG_B0_P3_U0_CFG26, 0x4001065a
 3756              	.set CYDEV_UCFG_B0_P3_U0_CFG27, 0x4001065b
 3757              	.set CYDEV_UCFG_B0_P3_U0_CFG28, 0x4001065c
 3758              	.set CYDEV_UCFG_B0_P3_U0_CFG29, 0x4001065d
 3759              	.set CYDEV_UCFG_B0_P3_U0_CFG30, 0x4001065e
 3760              	.set CYDEV_UCFG_B0_P3_U0_CFG31, 0x4001065f
 3761              	.set CYDEV_UCFG_B0_P3_U0_DCFG0, 0x40010660
 3762              	.set CYDEV_UCFG_B0_P3_U0_DCFG1, 0x40010662
 3763              	.set CYDEV_UCFG_B0_P3_U0_DCFG2, 0x40010664
 3764              	.set CYDEV_UCFG_B0_P3_U0_DCFG3, 0x40010666
 3765              	.set CYDEV_UCFG_B0_P3_U0_DCFG4, 0x40010668
 3766              	.set CYDEV_UCFG_B0_P3_U0_DCFG5, 0x4001066a
 3767              	.set CYDEV_UCFG_B0_P3_U0_DCFG6, 0x4001066c
 3768              	.set CYDEV_UCFG_B0_P3_U0_DCFG7, 0x4001066e
 3769              	.set CYDEV_UCFG_B0_P3_U1_BASE, 0x40010680
 3770              	.set CYDEV_UCFG_B0_P3_U1_SIZE, 0x00000070
 3771              	.set CYDEV_UCFG_B0_P3_U1_PLD_IT0, 0x40010680
 3772              	.set CYDEV_UCFG_B0_P3_U1_PLD_IT1, 0x40010684
 3773              	.set CYDEV_UCFG_B0_P3_U1_PLD_IT2, 0x40010688
 3774              	.set CYDEV_UCFG_B0_P3_U1_PLD_IT3, 0x4001068c
 3775              	.set CYDEV_UCFG_B0_P3_U1_PLD_IT4, 0x40010690
 3776              	.set CYDEV_UCFG_B0_P3_U1_PLD_IT5, 0x40010694
 3777              	.set CYDEV_UCFG_B0_P3_U1_PLD_IT6, 0x40010698
 3778              	.set CYDEV_UCFG_B0_P3_U1_PLD_IT7, 0x4001069c
 3779              	.set CYDEV_UCFG_B0_P3_U1_PLD_IT8, 0x400106a0
 3780              	.set CYDEV_UCFG_B0_P3_U1_PLD_IT9, 0x400106a4
 3781              	.set CYDEV_UCFG_B0_P3_U1_PLD_IT10, 0x400106a8
 3782              	.set CYDEV_UCFG_B0_P3_U1_PLD_IT11, 0x400106ac
 3783              	.set CYDEV_UCFG_B0_P3_U1_PLD_ORT0, 0x400106b0
 3784              	.set CYDEV_UCFG_B0_P3_U1_PLD_ORT1, 0x400106b2
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 68


 3785              	.set CYDEV_UCFG_B0_P3_U1_PLD_ORT2, 0x400106b4
 3786              	.set CYDEV_UCFG_B0_P3_U1_PLD_ORT3, 0x400106b6
 3787              	.set CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST, 0x400106b8
 3788              	.set CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB, 0x400106ba
 3789              	.set CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET, 0x400106bc
 3790              	.set CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS, 0x400106be
 3791              	.set CYDEV_UCFG_B0_P3_U1_CFG0, 0x400106c0
 3792              	.set CYDEV_UCFG_B0_P3_U1_CFG1, 0x400106c1
 3793              	.set CYDEV_UCFG_B0_P3_U1_CFG2, 0x400106c2
 3794              	.set CYDEV_UCFG_B0_P3_U1_CFG3, 0x400106c3
 3795              	.set CYDEV_UCFG_B0_P3_U1_CFG4, 0x400106c4
 3796              	.set CYDEV_UCFG_B0_P3_U1_CFG5, 0x400106c5
 3797              	.set CYDEV_UCFG_B0_P3_U1_CFG6, 0x400106c6
 3798              	.set CYDEV_UCFG_B0_P3_U1_CFG7, 0x400106c7
 3799              	.set CYDEV_UCFG_B0_P3_U1_CFG8, 0x400106c8
 3800              	.set CYDEV_UCFG_B0_P3_U1_CFG9, 0x400106c9
 3801              	.set CYDEV_UCFG_B0_P3_U1_CFG10, 0x400106ca
 3802              	.set CYDEV_UCFG_B0_P3_U1_CFG11, 0x400106cb
 3803              	.set CYDEV_UCFG_B0_P3_U1_CFG12, 0x400106cc
 3804              	.set CYDEV_UCFG_B0_P3_U1_CFG13, 0x400106cd
 3805              	.set CYDEV_UCFG_B0_P3_U1_CFG14, 0x400106ce
 3806              	.set CYDEV_UCFG_B0_P3_U1_CFG15, 0x400106cf
 3807              	.set CYDEV_UCFG_B0_P3_U1_CFG16, 0x400106d0
 3808              	.set CYDEV_UCFG_B0_P3_U1_CFG17, 0x400106d1
 3809              	.set CYDEV_UCFG_B0_P3_U1_CFG18, 0x400106d2
 3810              	.set CYDEV_UCFG_B0_P3_U1_CFG19, 0x400106d3
 3811              	.set CYDEV_UCFG_B0_P3_U1_CFG20, 0x400106d4
 3812              	.set CYDEV_UCFG_B0_P3_U1_CFG21, 0x400106d5
 3813              	.set CYDEV_UCFG_B0_P3_U1_CFG22, 0x400106d6
 3814              	.set CYDEV_UCFG_B0_P3_U1_CFG23, 0x400106d7
 3815              	.set CYDEV_UCFG_B0_P3_U1_CFG24, 0x400106d8
 3816              	.set CYDEV_UCFG_B0_P3_U1_CFG25, 0x400106d9
 3817              	.set CYDEV_UCFG_B0_P3_U1_CFG26, 0x400106da
 3818              	.set CYDEV_UCFG_B0_P3_U1_CFG27, 0x400106db
 3819              	.set CYDEV_UCFG_B0_P3_U1_CFG28, 0x400106dc
 3820              	.set CYDEV_UCFG_B0_P3_U1_CFG29, 0x400106dd
 3821              	.set CYDEV_UCFG_B0_P3_U1_CFG30, 0x400106de
 3822              	.set CYDEV_UCFG_B0_P3_U1_CFG31, 0x400106df
 3823              	.set CYDEV_UCFG_B0_P3_U1_DCFG0, 0x400106e0
 3824              	.set CYDEV_UCFG_B0_P3_U1_DCFG1, 0x400106e2
 3825              	.set CYDEV_UCFG_B0_P3_U1_DCFG2, 0x400106e4
 3826              	.set CYDEV_UCFG_B0_P3_U1_DCFG3, 0x400106e6
 3827              	.set CYDEV_UCFG_B0_P3_U1_DCFG4, 0x400106e8
 3828              	.set CYDEV_UCFG_B0_P3_U1_DCFG5, 0x400106ea
 3829              	.set CYDEV_UCFG_B0_P3_U1_DCFG6, 0x400106ec
 3830              	.set CYDEV_UCFG_B0_P3_U1_DCFG7, 0x400106ee
 3831              	.set CYDEV_UCFG_B0_P3_ROUTE_BASE, 0x40010700
 3832              	.set CYDEV_UCFG_B0_P3_ROUTE_SIZE, 0x000000ef
 3833              	.set CYDEV_UCFG_B0_P4_BASE, 0x40010800
 3834              	.set CYDEV_UCFG_B0_P4_SIZE, 0x000001ef
 3835              	.set CYDEV_UCFG_B0_P4_U0_BASE, 0x40010800
 3836              	.set CYDEV_UCFG_B0_P4_U0_SIZE, 0x00000070
 3837              	.set CYDEV_UCFG_B0_P4_U0_PLD_IT0, 0x40010800
 3838              	.set CYDEV_UCFG_B0_P4_U0_PLD_IT1, 0x40010804
 3839              	.set CYDEV_UCFG_B0_P4_U0_PLD_IT2, 0x40010808
 3840              	.set CYDEV_UCFG_B0_P4_U0_PLD_IT3, 0x4001080c
 3841              	.set CYDEV_UCFG_B0_P4_U0_PLD_IT4, 0x40010810
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 69


 3842              	.set CYDEV_UCFG_B0_P4_U0_PLD_IT5, 0x40010814
 3843              	.set CYDEV_UCFG_B0_P4_U0_PLD_IT6, 0x40010818
 3844              	.set CYDEV_UCFG_B0_P4_U0_PLD_IT7, 0x4001081c
 3845              	.set CYDEV_UCFG_B0_P4_U0_PLD_IT8, 0x40010820
 3846              	.set CYDEV_UCFG_B0_P4_U0_PLD_IT9, 0x40010824
 3847              	.set CYDEV_UCFG_B0_P4_U0_PLD_IT10, 0x40010828
 3848              	.set CYDEV_UCFG_B0_P4_U0_PLD_IT11, 0x4001082c
 3849              	.set CYDEV_UCFG_B0_P4_U0_PLD_ORT0, 0x40010830
 3850              	.set CYDEV_UCFG_B0_P4_U0_PLD_ORT1, 0x40010832
 3851              	.set CYDEV_UCFG_B0_P4_U0_PLD_ORT2, 0x40010834
 3852              	.set CYDEV_UCFG_B0_P4_U0_PLD_ORT3, 0x40010836
 3853              	.set CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST, 0x40010838
 3854              	.set CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB, 0x4001083a
 3855              	.set CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET, 0x4001083c
 3856              	.set CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS, 0x4001083e
 3857              	.set CYDEV_UCFG_B0_P4_U0_CFG0, 0x40010840
 3858              	.set CYDEV_UCFG_B0_P4_U0_CFG1, 0x40010841
 3859              	.set CYDEV_UCFG_B0_P4_U0_CFG2, 0x40010842
 3860              	.set CYDEV_UCFG_B0_P4_U0_CFG3, 0x40010843
 3861              	.set CYDEV_UCFG_B0_P4_U0_CFG4, 0x40010844
 3862              	.set CYDEV_UCFG_B0_P4_U0_CFG5, 0x40010845
 3863              	.set CYDEV_UCFG_B0_P4_U0_CFG6, 0x40010846
 3864              	.set CYDEV_UCFG_B0_P4_U0_CFG7, 0x40010847
 3865              	.set CYDEV_UCFG_B0_P4_U0_CFG8, 0x40010848
 3866              	.set CYDEV_UCFG_B0_P4_U0_CFG9, 0x40010849
 3867              	.set CYDEV_UCFG_B0_P4_U0_CFG10, 0x4001084a
 3868              	.set CYDEV_UCFG_B0_P4_U0_CFG11, 0x4001084b
 3869              	.set CYDEV_UCFG_B0_P4_U0_CFG12, 0x4001084c
 3870              	.set CYDEV_UCFG_B0_P4_U0_CFG13, 0x4001084d
 3871              	.set CYDEV_UCFG_B0_P4_U0_CFG14, 0x4001084e
 3872              	.set CYDEV_UCFG_B0_P4_U0_CFG15, 0x4001084f
 3873              	.set CYDEV_UCFG_B0_P4_U0_CFG16, 0x40010850
 3874              	.set CYDEV_UCFG_B0_P4_U0_CFG17, 0x40010851
 3875              	.set CYDEV_UCFG_B0_P4_U0_CFG18, 0x40010852
 3876              	.set CYDEV_UCFG_B0_P4_U0_CFG19, 0x40010853
 3877              	.set CYDEV_UCFG_B0_P4_U0_CFG20, 0x40010854
 3878              	.set CYDEV_UCFG_B0_P4_U0_CFG21, 0x40010855
 3879              	.set CYDEV_UCFG_B0_P4_U0_CFG22, 0x40010856
 3880              	.set CYDEV_UCFG_B0_P4_U0_CFG23, 0x40010857
 3881              	.set CYDEV_UCFG_B0_P4_U0_CFG24, 0x40010858
 3882              	.set CYDEV_UCFG_B0_P4_U0_CFG25, 0x40010859
 3883              	.set CYDEV_UCFG_B0_P4_U0_CFG26, 0x4001085a
 3884              	.set CYDEV_UCFG_B0_P4_U0_CFG27, 0x4001085b
 3885              	.set CYDEV_UCFG_B0_P4_U0_CFG28, 0x4001085c
 3886              	.set CYDEV_UCFG_B0_P4_U0_CFG29, 0x4001085d
 3887              	.set CYDEV_UCFG_B0_P4_U0_CFG30, 0x4001085e
 3888              	.set CYDEV_UCFG_B0_P4_U0_CFG31, 0x4001085f
 3889              	.set CYDEV_UCFG_B0_P4_U0_DCFG0, 0x40010860
 3890              	.set CYDEV_UCFG_B0_P4_U0_DCFG1, 0x40010862
 3891              	.set CYDEV_UCFG_B0_P4_U0_DCFG2, 0x40010864
 3892              	.set CYDEV_UCFG_B0_P4_U0_DCFG3, 0x40010866
 3893              	.set CYDEV_UCFG_B0_P4_U0_DCFG4, 0x40010868
 3894              	.set CYDEV_UCFG_B0_P4_U0_DCFG5, 0x4001086a
 3895              	.set CYDEV_UCFG_B0_P4_U0_DCFG6, 0x4001086c
 3896              	.set CYDEV_UCFG_B0_P4_U0_DCFG7, 0x4001086e
 3897              	.set CYDEV_UCFG_B0_P4_U1_BASE, 0x40010880
 3898              	.set CYDEV_UCFG_B0_P4_U1_SIZE, 0x00000070
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 70


 3899              	.set CYDEV_UCFG_B0_P4_U1_PLD_IT0, 0x40010880
 3900              	.set CYDEV_UCFG_B0_P4_U1_PLD_IT1, 0x40010884
 3901              	.set CYDEV_UCFG_B0_P4_U1_PLD_IT2, 0x40010888
 3902              	.set CYDEV_UCFG_B0_P4_U1_PLD_IT3, 0x4001088c
 3903              	.set CYDEV_UCFG_B0_P4_U1_PLD_IT4, 0x40010890
 3904              	.set CYDEV_UCFG_B0_P4_U1_PLD_IT5, 0x40010894
 3905              	.set CYDEV_UCFG_B0_P4_U1_PLD_IT6, 0x40010898
 3906              	.set CYDEV_UCFG_B0_P4_U1_PLD_IT7, 0x4001089c
 3907              	.set CYDEV_UCFG_B0_P4_U1_PLD_IT8, 0x400108a0
 3908              	.set CYDEV_UCFG_B0_P4_U1_PLD_IT9, 0x400108a4
 3909              	.set CYDEV_UCFG_B0_P4_U1_PLD_IT10, 0x400108a8
 3910              	.set CYDEV_UCFG_B0_P4_U1_PLD_IT11, 0x400108ac
 3911              	.set CYDEV_UCFG_B0_P4_U1_PLD_ORT0, 0x400108b0
 3912              	.set CYDEV_UCFG_B0_P4_U1_PLD_ORT1, 0x400108b2
 3913              	.set CYDEV_UCFG_B0_P4_U1_PLD_ORT2, 0x400108b4
 3914              	.set CYDEV_UCFG_B0_P4_U1_PLD_ORT3, 0x400108b6
 3915              	.set CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST, 0x400108b8
 3916              	.set CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB, 0x400108ba
 3917              	.set CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET, 0x400108bc
 3918              	.set CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS, 0x400108be
 3919              	.set CYDEV_UCFG_B0_P4_U1_CFG0, 0x400108c0
 3920              	.set CYDEV_UCFG_B0_P4_U1_CFG1, 0x400108c1
 3921              	.set CYDEV_UCFG_B0_P4_U1_CFG2, 0x400108c2
 3922              	.set CYDEV_UCFG_B0_P4_U1_CFG3, 0x400108c3
 3923              	.set CYDEV_UCFG_B0_P4_U1_CFG4, 0x400108c4
 3924              	.set CYDEV_UCFG_B0_P4_U1_CFG5, 0x400108c5
 3925              	.set CYDEV_UCFG_B0_P4_U1_CFG6, 0x400108c6
 3926              	.set CYDEV_UCFG_B0_P4_U1_CFG7, 0x400108c7
 3927              	.set CYDEV_UCFG_B0_P4_U1_CFG8, 0x400108c8
 3928              	.set CYDEV_UCFG_B0_P4_U1_CFG9, 0x400108c9
 3929              	.set CYDEV_UCFG_B0_P4_U1_CFG10, 0x400108ca
 3930              	.set CYDEV_UCFG_B0_P4_U1_CFG11, 0x400108cb
 3931              	.set CYDEV_UCFG_B0_P4_U1_CFG12, 0x400108cc
 3932              	.set CYDEV_UCFG_B0_P4_U1_CFG13, 0x400108cd
 3933              	.set CYDEV_UCFG_B0_P4_U1_CFG14, 0x400108ce
 3934              	.set CYDEV_UCFG_B0_P4_U1_CFG15, 0x400108cf
 3935              	.set CYDEV_UCFG_B0_P4_U1_CFG16, 0x400108d0
 3936              	.set CYDEV_UCFG_B0_P4_U1_CFG17, 0x400108d1
 3937              	.set CYDEV_UCFG_B0_P4_U1_CFG18, 0x400108d2
 3938              	.set CYDEV_UCFG_B0_P4_U1_CFG19, 0x400108d3
 3939              	.set CYDEV_UCFG_B0_P4_U1_CFG20, 0x400108d4
 3940              	.set CYDEV_UCFG_B0_P4_U1_CFG21, 0x400108d5
 3941              	.set CYDEV_UCFG_B0_P4_U1_CFG22, 0x400108d6
 3942              	.set CYDEV_UCFG_B0_P4_U1_CFG23, 0x400108d7
 3943              	.set CYDEV_UCFG_B0_P4_U1_CFG24, 0x400108d8
 3944              	.set CYDEV_UCFG_B0_P4_U1_CFG25, 0x400108d9
 3945              	.set CYDEV_UCFG_B0_P4_U1_CFG26, 0x400108da
 3946              	.set CYDEV_UCFG_B0_P4_U1_CFG27, 0x400108db
 3947              	.set CYDEV_UCFG_B0_P4_U1_CFG28, 0x400108dc
 3948              	.set CYDEV_UCFG_B0_P4_U1_CFG29, 0x400108dd
 3949              	.set CYDEV_UCFG_B0_P4_U1_CFG30, 0x400108de
 3950              	.set CYDEV_UCFG_B0_P4_U1_CFG31, 0x400108df
 3951              	.set CYDEV_UCFG_B0_P4_U1_DCFG0, 0x400108e0
 3952              	.set CYDEV_UCFG_B0_P4_U1_DCFG1, 0x400108e2
 3953              	.set CYDEV_UCFG_B0_P4_U1_DCFG2, 0x400108e4
 3954              	.set CYDEV_UCFG_B0_P4_U1_DCFG3, 0x400108e6
 3955              	.set CYDEV_UCFG_B0_P4_U1_DCFG4, 0x400108e8
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 71


 3956              	.set CYDEV_UCFG_B0_P4_U1_DCFG5, 0x400108ea
 3957              	.set CYDEV_UCFG_B0_P4_U1_DCFG6, 0x400108ec
 3958              	.set CYDEV_UCFG_B0_P4_U1_DCFG7, 0x400108ee
 3959              	.set CYDEV_UCFG_B0_P4_ROUTE_BASE, 0x40010900
 3960              	.set CYDEV_UCFG_B0_P4_ROUTE_SIZE, 0x000000ef
 3961              	.set CYDEV_UCFG_B0_P5_BASE, 0x40010a00
 3962              	.set CYDEV_UCFG_B0_P5_SIZE, 0x000001ef
 3963              	.set CYDEV_UCFG_B0_P5_U0_BASE, 0x40010a00
 3964              	.set CYDEV_UCFG_B0_P5_U0_SIZE, 0x00000070
 3965              	.set CYDEV_UCFG_B0_P5_U0_PLD_IT0, 0x40010a00
 3966              	.set CYDEV_UCFG_B0_P5_U0_PLD_IT1, 0x40010a04
 3967              	.set CYDEV_UCFG_B0_P5_U0_PLD_IT2, 0x40010a08
 3968              	.set CYDEV_UCFG_B0_P5_U0_PLD_IT3, 0x40010a0c
 3969              	.set CYDEV_UCFG_B0_P5_U0_PLD_IT4, 0x40010a10
 3970              	.set CYDEV_UCFG_B0_P5_U0_PLD_IT5, 0x40010a14
 3971              	.set CYDEV_UCFG_B0_P5_U0_PLD_IT6, 0x40010a18
 3972              	.set CYDEV_UCFG_B0_P5_U0_PLD_IT7, 0x40010a1c
 3973              	.set CYDEV_UCFG_B0_P5_U0_PLD_IT8, 0x40010a20
 3974              	.set CYDEV_UCFG_B0_P5_U0_PLD_IT9, 0x40010a24
 3975              	.set CYDEV_UCFG_B0_P5_U0_PLD_IT10, 0x40010a28
 3976              	.set CYDEV_UCFG_B0_P5_U0_PLD_IT11, 0x40010a2c
 3977              	.set CYDEV_UCFG_B0_P5_U0_PLD_ORT0, 0x40010a30
 3978              	.set CYDEV_UCFG_B0_P5_U0_PLD_ORT1, 0x40010a32
 3979              	.set CYDEV_UCFG_B0_P5_U0_PLD_ORT2, 0x40010a34
 3980              	.set CYDEV_UCFG_B0_P5_U0_PLD_ORT3, 0x40010a36
 3981              	.set CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST, 0x40010a38
 3982              	.set CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB, 0x40010a3a
 3983              	.set CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET, 0x40010a3c
 3984              	.set CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS, 0x40010a3e
 3985              	.set CYDEV_UCFG_B0_P5_U0_CFG0, 0x40010a40
 3986              	.set CYDEV_UCFG_B0_P5_U0_CFG1, 0x40010a41
 3987              	.set CYDEV_UCFG_B0_P5_U0_CFG2, 0x40010a42
 3988              	.set CYDEV_UCFG_B0_P5_U0_CFG3, 0x40010a43
 3989              	.set CYDEV_UCFG_B0_P5_U0_CFG4, 0x40010a44
 3990              	.set CYDEV_UCFG_B0_P5_U0_CFG5, 0x40010a45
 3991              	.set CYDEV_UCFG_B0_P5_U0_CFG6, 0x40010a46
 3992              	.set CYDEV_UCFG_B0_P5_U0_CFG7, 0x40010a47
 3993              	.set CYDEV_UCFG_B0_P5_U0_CFG8, 0x40010a48
 3994              	.set CYDEV_UCFG_B0_P5_U0_CFG9, 0x40010a49
 3995              	.set CYDEV_UCFG_B0_P5_U0_CFG10, 0x40010a4a
 3996              	.set CYDEV_UCFG_B0_P5_U0_CFG11, 0x40010a4b
 3997              	.set CYDEV_UCFG_B0_P5_U0_CFG12, 0x40010a4c
 3998              	.set CYDEV_UCFG_B0_P5_U0_CFG13, 0x40010a4d
 3999              	.set CYDEV_UCFG_B0_P5_U0_CFG14, 0x40010a4e
 4000              	.set CYDEV_UCFG_B0_P5_U0_CFG15, 0x40010a4f
 4001              	.set CYDEV_UCFG_B0_P5_U0_CFG16, 0x40010a50
 4002              	.set CYDEV_UCFG_B0_P5_U0_CFG17, 0x40010a51
 4003              	.set CYDEV_UCFG_B0_P5_U0_CFG18, 0x40010a52
 4004              	.set CYDEV_UCFG_B0_P5_U0_CFG19, 0x40010a53
 4005              	.set CYDEV_UCFG_B0_P5_U0_CFG20, 0x40010a54
 4006              	.set CYDEV_UCFG_B0_P5_U0_CFG21, 0x40010a55
 4007              	.set CYDEV_UCFG_B0_P5_U0_CFG22, 0x40010a56
 4008              	.set CYDEV_UCFG_B0_P5_U0_CFG23, 0x40010a57
 4009              	.set CYDEV_UCFG_B0_P5_U0_CFG24, 0x40010a58
 4010              	.set CYDEV_UCFG_B0_P5_U0_CFG25, 0x40010a59
 4011              	.set CYDEV_UCFG_B0_P5_U0_CFG26, 0x40010a5a
 4012              	.set CYDEV_UCFG_B0_P5_U0_CFG27, 0x40010a5b
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 72


 4013              	.set CYDEV_UCFG_B0_P5_U0_CFG28, 0x40010a5c
 4014              	.set CYDEV_UCFG_B0_P5_U0_CFG29, 0x40010a5d
 4015              	.set CYDEV_UCFG_B0_P5_U0_CFG30, 0x40010a5e
 4016              	.set CYDEV_UCFG_B0_P5_U0_CFG31, 0x40010a5f
 4017              	.set CYDEV_UCFG_B0_P5_U0_DCFG0, 0x40010a60
 4018              	.set CYDEV_UCFG_B0_P5_U0_DCFG1, 0x40010a62
 4019              	.set CYDEV_UCFG_B0_P5_U0_DCFG2, 0x40010a64
 4020              	.set CYDEV_UCFG_B0_P5_U0_DCFG3, 0x40010a66
 4021              	.set CYDEV_UCFG_B0_P5_U0_DCFG4, 0x40010a68
 4022              	.set CYDEV_UCFG_B0_P5_U0_DCFG5, 0x40010a6a
 4023              	.set CYDEV_UCFG_B0_P5_U0_DCFG6, 0x40010a6c
 4024              	.set CYDEV_UCFG_B0_P5_U0_DCFG7, 0x40010a6e
 4025              	.set CYDEV_UCFG_B0_P5_U1_BASE, 0x40010a80
 4026              	.set CYDEV_UCFG_B0_P5_U1_SIZE, 0x00000070
 4027              	.set CYDEV_UCFG_B0_P5_U1_PLD_IT0, 0x40010a80
 4028              	.set CYDEV_UCFG_B0_P5_U1_PLD_IT1, 0x40010a84
 4029              	.set CYDEV_UCFG_B0_P5_U1_PLD_IT2, 0x40010a88
 4030              	.set CYDEV_UCFG_B0_P5_U1_PLD_IT3, 0x40010a8c
 4031              	.set CYDEV_UCFG_B0_P5_U1_PLD_IT4, 0x40010a90
 4032              	.set CYDEV_UCFG_B0_P5_U1_PLD_IT5, 0x40010a94
 4033              	.set CYDEV_UCFG_B0_P5_U1_PLD_IT6, 0x40010a98
 4034              	.set CYDEV_UCFG_B0_P5_U1_PLD_IT7, 0x40010a9c
 4035              	.set CYDEV_UCFG_B0_P5_U1_PLD_IT8, 0x40010aa0
 4036              	.set CYDEV_UCFG_B0_P5_U1_PLD_IT9, 0x40010aa4
 4037              	.set CYDEV_UCFG_B0_P5_U1_PLD_IT10, 0x40010aa8
 4038              	.set CYDEV_UCFG_B0_P5_U1_PLD_IT11, 0x40010aac
 4039              	.set CYDEV_UCFG_B0_P5_U1_PLD_ORT0, 0x40010ab0
 4040              	.set CYDEV_UCFG_B0_P5_U1_PLD_ORT1, 0x40010ab2
 4041              	.set CYDEV_UCFG_B0_P5_U1_PLD_ORT2, 0x40010ab4
 4042              	.set CYDEV_UCFG_B0_P5_U1_PLD_ORT3, 0x40010ab6
 4043              	.set CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST, 0x40010ab8
 4044              	.set CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB, 0x40010aba
 4045              	.set CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET, 0x40010abc
 4046              	.set CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS, 0x40010abe
 4047              	.set CYDEV_UCFG_B0_P5_U1_CFG0, 0x40010ac0
 4048              	.set CYDEV_UCFG_B0_P5_U1_CFG1, 0x40010ac1
 4049              	.set CYDEV_UCFG_B0_P5_U1_CFG2, 0x40010ac2
 4050              	.set CYDEV_UCFG_B0_P5_U1_CFG3, 0x40010ac3
 4051              	.set CYDEV_UCFG_B0_P5_U1_CFG4, 0x40010ac4
 4052              	.set CYDEV_UCFG_B0_P5_U1_CFG5, 0x40010ac5
 4053              	.set CYDEV_UCFG_B0_P5_U1_CFG6, 0x40010ac6
 4054              	.set CYDEV_UCFG_B0_P5_U1_CFG7, 0x40010ac7
 4055              	.set CYDEV_UCFG_B0_P5_U1_CFG8, 0x40010ac8
 4056              	.set CYDEV_UCFG_B0_P5_U1_CFG9, 0x40010ac9
 4057              	.set CYDEV_UCFG_B0_P5_U1_CFG10, 0x40010aca
 4058              	.set CYDEV_UCFG_B0_P5_U1_CFG11, 0x40010acb
 4059              	.set CYDEV_UCFG_B0_P5_U1_CFG12, 0x40010acc
 4060              	.set CYDEV_UCFG_B0_P5_U1_CFG13, 0x40010acd
 4061              	.set CYDEV_UCFG_B0_P5_U1_CFG14, 0x40010ace
 4062              	.set CYDEV_UCFG_B0_P5_U1_CFG15, 0x40010acf
 4063              	.set CYDEV_UCFG_B0_P5_U1_CFG16, 0x40010ad0
 4064              	.set CYDEV_UCFG_B0_P5_U1_CFG17, 0x40010ad1
 4065              	.set CYDEV_UCFG_B0_P5_U1_CFG18, 0x40010ad2
 4066              	.set CYDEV_UCFG_B0_P5_U1_CFG19, 0x40010ad3
 4067              	.set CYDEV_UCFG_B0_P5_U1_CFG20, 0x40010ad4
 4068              	.set CYDEV_UCFG_B0_P5_U1_CFG21, 0x40010ad5
 4069              	.set CYDEV_UCFG_B0_P5_U1_CFG22, 0x40010ad6
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 73


 4070              	.set CYDEV_UCFG_B0_P5_U1_CFG23, 0x40010ad7
 4071              	.set CYDEV_UCFG_B0_P5_U1_CFG24, 0x40010ad8
 4072              	.set CYDEV_UCFG_B0_P5_U1_CFG25, 0x40010ad9
 4073              	.set CYDEV_UCFG_B0_P5_U1_CFG26, 0x40010ada
 4074              	.set CYDEV_UCFG_B0_P5_U1_CFG27, 0x40010adb
 4075              	.set CYDEV_UCFG_B0_P5_U1_CFG28, 0x40010adc
 4076              	.set CYDEV_UCFG_B0_P5_U1_CFG29, 0x40010add
 4077              	.set CYDEV_UCFG_B0_P5_U1_CFG30, 0x40010ade
 4078              	.set CYDEV_UCFG_B0_P5_U1_CFG31, 0x40010adf
 4079              	.set CYDEV_UCFG_B0_P5_U1_DCFG0, 0x40010ae0
 4080              	.set CYDEV_UCFG_B0_P5_U1_DCFG1, 0x40010ae2
 4081              	.set CYDEV_UCFG_B0_P5_U1_DCFG2, 0x40010ae4
 4082              	.set CYDEV_UCFG_B0_P5_U1_DCFG3, 0x40010ae6
 4083              	.set CYDEV_UCFG_B0_P5_U1_DCFG4, 0x40010ae8
 4084              	.set CYDEV_UCFG_B0_P5_U1_DCFG5, 0x40010aea
 4085              	.set CYDEV_UCFG_B0_P5_U1_DCFG6, 0x40010aec
 4086              	.set CYDEV_UCFG_B0_P5_U1_DCFG7, 0x40010aee
 4087              	.set CYDEV_UCFG_B0_P5_ROUTE_BASE, 0x40010b00
 4088              	.set CYDEV_UCFG_B0_P5_ROUTE_SIZE, 0x000000ef
 4089              	.set CYDEV_UCFG_B0_P6_BASE, 0x40010c00
 4090              	.set CYDEV_UCFG_B0_P6_SIZE, 0x000001ef
 4091              	.set CYDEV_UCFG_B0_P6_U0_BASE, 0x40010c00
 4092              	.set CYDEV_UCFG_B0_P6_U0_SIZE, 0x00000070
 4093              	.set CYDEV_UCFG_B0_P6_U0_PLD_IT0, 0x40010c00
 4094              	.set CYDEV_UCFG_B0_P6_U0_PLD_IT1, 0x40010c04
 4095              	.set CYDEV_UCFG_B0_P6_U0_PLD_IT2, 0x40010c08
 4096              	.set CYDEV_UCFG_B0_P6_U0_PLD_IT3, 0x40010c0c
 4097              	.set CYDEV_UCFG_B0_P6_U0_PLD_IT4, 0x40010c10
 4098              	.set CYDEV_UCFG_B0_P6_U0_PLD_IT5, 0x40010c14
 4099              	.set CYDEV_UCFG_B0_P6_U0_PLD_IT6, 0x40010c18
 4100              	.set CYDEV_UCFG_B0_P6_U0_PLD_IT7, 0x40010c1c
 4101              	.set CYDEV_UCFG_B0_P6_U0_PLD_IT8, 0x40010c20
 4102              	.set CYDEV_UCFG_B0_P6_U0_PLD_IT9, 0x40010c24
 4103              	.set CYDEV_UCFG_B0_P6_U0_PLD_IT10, 0x40010c28
 4104              	.set CYDEV_UCFG_B0_P6_U0_PLD_IT11, 0x40010c2c
 4105              	.set CYDEV_UCFG_B0_P6_U0_PLD_ORT0, 0x40010c30
 4106              	.set CYDEV_UCFG_B0_P6_U0_PLD_ORT1, 0x40010c32
 4107              	.set CYDEV_UCFG_B0_P6_U0_PLD_ORT2, 0x40010c34
 4108              	.set CYDEV_UCFG_B0_P6_U0_PLD_ORT3, 0x40010c36
 4109              	.set CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST, 0x40010c38
 4110              	.set CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB, 0x40010c3a
 4111              	.set CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET, 0x40010c3c
 4112              	.set CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS, 0x40010c3e
 4113              	.set CYDEV_UCFG_B0_P6_U0_CFG0, 0x40010c40
 4114              	.set CYDEV_UCFG_B0_P6_U0_CFG1, 0x40010c41
 4115              	.set CYDEV_UCFG_B0_P6_U0_CFG2, 0x40010c42
 4116              	.set CYDEV_UCFG_B0_P6_U0_CFG3, 0x40010c43
 4117              	.set CYDEV_UCFG_B0_P6_U0_CFG4, 0x40010c44
 4118              	.set CYDEV_UCFG_B0_P6_U0_CFG5, 0x40010c45
 4119              	.set CYDEV_UCFG_B0_P6_U0_CFG6, 0x40010c46
 4120              	.set CYDEV_UCFG_B0_P6_U0_CFG7, 0x40010c47
 4121              	.set CYDEV_UCFG_B0_P6_U0_CFG8, 0x40010c48
 4122              	.set CYDEV_UCFG_B0_P6_U0_CFG9, 0x40010c49
 4123              	.set CYDEV_UCFG_B0_P6_U0_CFG10, 0x40010c4a
 4124              	.set CYDEV_UCFG_B0_P6_U0_CFG11, 0x40010c4b
 4125              	.set CYDEV_UCFG_B0_P6_U0_CFG12, 0x40010c4c
 4126              	.set CYDEV_UCFG_B0_P6_U0_CFG13, 0x40010c4d
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 74


 4127              	.set CYDEV_UCFG_B0_P6_U0_CFG14, 0x40010c4e
 4128              	.set CYDEV_UCFG_B0_P6_U0_CFG15, 0x40010c4f
 4129              	.set CYDEV_UCFG_B0_P6_U0_CFG16, 0x40010c50
 4130              	.set CYDEV_UCFG_B0_P6_U0_CFG17, 0x40010c51
 4131              	.set CYDEV_UCFG_B0_P6_U0_CFG18, 0x40010c52
 4132              	.set CYDEV_UCFG_B0_P6_U0_CFG19, 0x40010c53
 4133              	.set CYDEV_UCFG_B0_P6_U0_CFG20, 0x40010c54
 4134              	.set CYDEV_UCFG_B0_P6_U0_CFG21, 0x40010c55
 4135              	.set CYDEV_UCFG_B0_P6_U0_CFG22, 0x40010c56
 4136              	.set CYDEV_UCFG_B0_P6_U0_CFG23, 0x40010c57
 4137              	.set CYDEV_UCFG_B0_P6_U0_CFG24, 0x40010c58
 4138              	.set CYDEV_UCFG_B0_P6_U0_CFG25, 0x40010c59
 4139              	.set CYDEV_UCFG_B0_P6_U0_CFG26, 0x40010c5a
 4140              	.set CYDEV_UCFG_B0_P6_U0_CFG27, 0x40010c5b
 4141              	.set CYDEV_UCFG_B0_P6_U0_CFG28, 0x40010c5c
 4142              	.set CYDEV_UCFG_B0_P6_U0_CFG29, 0x40010c5d
 4143              	.set CYDEV_UCFG_B0_P6_U0_CFG30, 0x40010c5e
 4144              	.set CYDEV_UCFG_B0_P6_U0_CFG31, 0x40010c5f
 4145              	.set CYDEV_UCFG_B0_P6_U0_DCFG0, 0x40010c60
 4146              	.set CYDEV_UCFG_B0_P6_U0_DCFG1, 0x40010c62
 4147              	.set CYDEV_UCFG_B0_P6_U0_DCFG2, 0x40010c64
 4148              	.set CYDEV_UCFG_B0_P6_U0_DCFG3, 0x40010c66
 4149              	.set CYDEV_UCFG_B0_P6_U0_DCFG4, 0x40010c68
 4150              	.set CYDEV_UCFG_B0_P6_U0_DCFG5, 0x40010c6a
 4151              	.set CYDEV_UCFG_B0_P6_U0_DCFG6, 0x40010c6c
 4152              	.set CYDEV_UCFG_B0_P6_U0_DCFG7, 0x40010c6e
 4153              	.set CYDEV_UCFG_B0_P6_U1_BASE, 0x40010c80
 4154              	.set CYDEV_UCFG_B0_P6_U1_SIZE, 0x00000070
 4155              	.set CYDEV_UCFG_B0_P6_U1_PLD_IT0, 0x40010c80
 4156              	.set CYDEV_UCFG_B0_P6_U1_PLD_IT1, 0x40010c84
 4157              	.set CYDEV_UCFG_B0_P6_U1_PLD_IT2, 0x40010c88
 4158              	.set CYDEV_UCFG_B0_P6_U1_PLD_IT3, 0x40010c8c
 4159              	.set CYDEV_UCFG_B0_P6_U1_PLD_IT4, 0x40010c90
 4160              	.set CYDEV_UCFG_B0_P6_U1_PLD_IT5, 0x40010c94
 4161              	.set CYDEV_UCFG_B0_P6_U1_PLD_IT6, 0x40010c98
 4162              	.set CYDEV_UCFG_B0_P6_U1_PLD_IT7, 0x40010c9c
 4163              	.set CYDEV_UCFG_B0_P6_U1_PLD_IT8, 0x40010ca0
 4164              	.set CYDEV_UCFG_B0_P6_U1_PLD_IT9, 0x40010ca4
 4165              	.set CYDEV_UCFG_B0_P6_U1_PLD_IT10, 0x40010ca8
 4166              	.set CYDEV_UCFG_B0_P6_U1_PLD_IT11, 0x40010cac
 4167              	.set CYDEV_UCFG_B0_P6_U1_PLD_ORT0, 0x40010cb0
 4168              	.set CYDEV_UCFG_B0_P6_U1_PLD_ORT1, 0x40010cb2
 4169              	.set CYDEV_UCFG_B0_P6_U1_PLD_ORT2, 0x40010cb4
 4170              	.set CYDEV_UCFG_B0_P6_U1_PLD_ORT3, 0x40010cb6
 4171              	.set CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST, 0x40010cb8
 4172              	.set CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB, 0x40010cba
 4173              	.set CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET, 0x40010cbc
 4174              	.set CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS, 0x40010cbe
 4175              	.set CYDEV_UCFG_B0_P6_U1_CFG0, 0x40010cc0
 4176              	.set CYDEV_UCFG_B0_P6_U1_CFG1, 0x40010cc1
 4177              	.set CYDEV_UCFG_B0_P6_U1_CFG2, 0x40010cc2
 4178              	.set CYDEV_UCFG_B0_P6_U1_CFG3, 0x40010cc3
 4179              	.set CYDEV_UCFG_B0_P6_U1_CFG4, 0x40010cc4
 4180              	.set CYDEV_UCFG_B0_P6_U1_CFG5, 0x40010cc5
 4181              	.set CYDEV_UCFG_B0_P6_U1_CFG6, 0x40010cc6
 4182              	.set CYDEV_UCFG_B0_P6_U1_CFG7, 0x40010cc7
 4183              	.set CYDEV_UCFG_B0_P6_U1_CFG8, 0x40010cc8
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 75


 4184              	.set CYDEV_UCFG_B0_P6_U1_CFG9, 0x40010cc9
 4185              	.set CYDEV_UCFG_B0_P6_U1_CFG10, 0x40010cca
 4186              	.set CYDEV_UCFG_B0_P6_U1_CFG11, 0x40010ccb
 4187              	.set CYDEV_UCFG_B0_P6_U1_CFG12, 0x40010ccc
 4188              	.set CYDEV_UCFG_B0_P6_U1_CFG13, 0x40010ccd
 4189              	.set CYDEV_UCFG_B0_P6_U1_CFG14, 0x40010cce
 4190              	.set CYDEV_UCFG_B0_P6_U1_CFG15, 0x40010ccf
 4191              	.set CYDEV_UCFG_B0_P6_U1_CFG16, 0x40010cd0
 4192              	.set CYDEV_UCFG_B0_P6_U1_CFG17, 0x40010cd1
 4193              	.set CYDEV_UCFG_B0_P6_U1_CFG18, 0x40010cd2
 4194              	.set CYDEV_UCFG_B0_P6_U1_CFG19, 0x40010cd3
 4195              	.set CYDEV_UCFG_B0_P6_U1_CFG20, 0x40010cd4
 4196              	.set CYDEV_UCFG_B0_P6_U1_CFG21, 0x40010cd5
 4197              	.set CYDEV_UCFG_B0_P6_U1_CFG22, 0x40010cd6
 4198              	.set CYDEV_UCFG_B0_P6_U1_CFG23, 0x40010cd7
 4199              	.set CYDEV_UCFG_B0_P6_U1_CFG24, 0x40010cd8
 4200              	.set CYDEV_UCFG_B0_P6_U1_CFG25, 0x40010cd9
 4201              	.set CYDEV_UCFG_B0_P6_U1_CFG26, 0x40010cda
 4202              	.set CYDEV_UCFG_B0_P6_U1_CFG27, 0x40010cdb
 4203              	.set CYDEV_UCFG_B0_P6_U1_CFG28, 0x40010cdc
 4204              	.set CYDEV_UCFG_B0_P6_U1_CFG29, 0x40010cdd
 4205              	.set CYDEV_UCFG_B0_P6_U1_CFG30, 0x40010cde
 4206              	.set CYDEV_UCFG_B0_P6_U1_CFG31, 0x40010cdf
 4207              	.set CYDEV_UCFG_B0_P6_U1_DCFG0, 0x40010ce0
 4208              	.set CYDEV_UCFG_B0_P6_U1_DCFG1, 0x40010ce2
 4209              	.set CYDEV_UCFG_B0_P6_U1_DCFG2, 0x40010ce4
 4210              	.set CYDEV_UCFG_B0_P6_U1_DCFG3, 0x40010ce6
 4211              	.set CYDEV_UCFG_B0_P6_U1_DCFG4, 0x40010ce8
 4212              	.set CYDEV_UCFG_B0_P6_U1_DCFG5, 0x40010cea
 4213              	.set CYDEV_UCFG_B0_P6_U1_DCFG6, 0x40010cec
 4214              	.set CYDEV_UCFG_B0_P6_U1_DCFG7, 0x40010cee
 4215              	.set CYDEV_UCFG_B0_P6_ROUTE_BASE, 0x40010d00
 4216              	.set CYDEV_UCFG_B0_P6_ROUTE_SIZE, 0x000000ef
 4217              	.set CYDEV_UCFG_B0_P7_BASE, 0x40010e00
 4218              	.set CYDEV_UCFG_B0_P7_SIZE, 0x000001ef
 4219              	.set CYDEV_UCFG_B0_P7_U0_BASE, 0x40010e00
 4220              	.set CYDEV_UCFG_B0_P7_U0_SIZE, 0x00000070
 4221              	.set CYDEV_UCFG_B0_P7_U0_PLD_IT0, 0x40010e00
 4222              	.set CYDEV_UCFG_B0_P7_U0_PLD_IT1, 0x40010e04
 4223              	.set CYDEV_UCFG_B0_P7_U0_PLD_IT2, 0x40010e08
 4224              	.set CYDEV_UCFG_B0_P7_U0_PLD_IT3, 0x40010e0c
 4225              	.set CYDEV_UCFG_B0_P7_U0_PLD_IT4, 0x40010e10
 4226              	.set CYDEV_UCFG_B0_P7_U0_PLD_IT5, 0x40010e14
 4227              	.set CYDEV_UCFG_B0_P7_U0_PLD_IT6, 0x40010e18
 4228              	.set CYDEV_UCFG_B0_P7_U0_PLD_IT7, 0x40010e1c
 4229              	.set CYDEV_UCFG_B0_P7_U0_PLD_IT8, 0x40010e20
 4230              	.set CYDEV_UCFG_B0_P7_U0_PLD_IT9, 0x40010e24
 4231              	.set CYDEV_UCFG_B0_P7_U0_PLD_IT10, 0x40010e28
 4232              	.set CYDEV_UCFG_B0_P7_U0_PLD_IT11, 0x40010e2c
 4233              	.set CYDEV_UCFG_B0_P7_U0_PLD_ORT0, 0x40010e30
 4234              	.set CYDEV_UCFG_B0_P7_U0_PLD_ORT1, 0x40010e32
 4235              	.set CYDEV_UCFG_B0_P7_U0_PLD_ORT2, 0x40010e34
 4236              	.set CYDEV_UCFG_B0_P7_U0_PLD_ORT3, 0x40010e36
 4237              	.set CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST, 0x40010e38
 4238              	.set CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB, 0x40010e3a
 4239              	.set CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET, 0x40010e3c
 4240              	.set CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS, 0x40010e3e
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 76


 4241              	.set CYDEV_UCFG_B0_P7_U0_CFG0, 0x40010e40
 4242              	.set CYDEV_UCFG_B0_P7_U0_CFG1, 0x40010e41
 4243              	.set CYDEV_UCFG_B0_P7_U0_CFG2, 0x40010e42
 4244              	.set CYDEV_UCFG_B0_P7_U0_CFG3, 0x40010e43
 4245              	.set CYDEV_UCFG_B0_P7_U0_CFG4, 0x40010e44
 4246              	.set CYDEV_UCFG_B0_P7_U0_CFG5, 0x40010e45
 4247              	.set CYDEV_UCFG_B0_P7_U0_CFG6, 0x40010e46
 4248              	.set CYDEV_UCFG_B0_P7_U0_CFG7, 0x40010e47
 4249              	.set CYDEV_UCFG_B0_P7_U0_CFG8, 0x40010e48
 4250              	.set CYDEV_UCFG_B0_P7_U0_CFG9, 0x40010e49
 4251              	.set CYDEV_UCFG_B0_P7_U0_CFG10, 0x40010e4a
 4252              	.set CYDEV_UCFG_B0_P7_U0_CFG11, 0x40010e4b
 4253              	.set CYDEV_UCFG_B0_P7_U0_CFG12, 0x40010e4c
 4254              	.set CYDEV_UCFG_B0_P7_U0_CFG13, 0x40010e4d
 4255              	.set CYDEV_UCFG_B0_P7_U0_CFG14, 0x40010e4e
 4256              	.set CYDEV_UCFG_B0_P7_U0_CFG15, 0x40010e4f
 4257              	.set CYDEV_UCFG_B0_P7_U0_CFG16, 0x40010e50
 4258              	.set CYDEV_UCFG_B0_P7_U0_CFG17, 0x40010e51
 4259              	.set CYDEV_UCFG_B0_P7_U0_CFG18, 0x40010e52
 4260              	.set CYDEV_UCFG_B0_P7_U0_CFG19, 0x40010e53
 4261              	.set CYDEV_UCFG_B0_P7_U0_CFG20, 0x40010e54
 4262              	.set CYDEV_UCFG_B0_P7_U0_CFG21, 0x40010e55
 4263              	.set CYDEV_UCFG_B0_P7_U0_CFG22, 0x40010e56
 4264              	.set CYDEV_UCFG_B0_P7_U0_CFG23, 0x40010e57
 4265              	.set CYDEV_UCFG_B0_P7_U0_CFG24, 0x40010e58
 4266              	.set CYDEV_UCFG_B0_P7_U0_CFG25, 0x40010e59
 4267              	.set CYDEV_UCFG_B0_P7_U0_CFG26, 0x40010e5a
 4268              	.set CYDEV_UCFG_B0_P7_U0_CFG27, 0x40010e5b
 4269              	.set CYDEV_UCFG_B0_P7_U0_CFG28, 0x40010e5c
 4270              	.set CYDEV_UCFG_B0_P7_U0_CFG29, 0x40010e5d
 4271              	.set CYDEV_UCFG_B0_P7_U0_CFG30, 0x40010e5e
 4272              	.set CYDEV_UCFG_B0_P7_U0_CFG31, 0x40010e5f
 4273              	.set CYDEV_UCFG_B0_P7_U0_DCFG0, 0x40010e60
 4274              	.set CYDEV_UCFG_B0_P7_U0_DCFG1, 0x40010e62
 4275              	.set CYDEV_UCFG_B0_P7_U0_DCFG2, 0x40010e64
 4276              	.set CYDEV_UCFG_B0_P7_U0_DCFG3, 0x40010e66
 4277              	.set CYDEV_UCFG_B0_P7_U0_DCFG4, 0x40010e68
 4278              	.set CYDEV_UCFG_B0_P7_U0_DCFG5, 0x40010e6a
 4279              	.set CYDEV_UCFG_B0_P7_U0_DCFG6, 0x40010e6c
 4280              	.set CYDEV_UCFG_B0_P7_U0_DCFG7, 0x40010e6e
 4281              	.set CYDEV_UCFG_B0_P7_U1_BASE, 0x40010e80
 4282              	.set CYDEV_UCFG_B0_P7_U1_SIZE, 0x00000070
 4283              	.set CYDEV_UCFG_B0_P7_U1_PLD_IT0, 0x40010e80
 4284              	.set CYDEV_UCFG_B0_P7_U1_PLD_IT1, 0x40010e84
 4285              	.set CYDEV_UCFG_B0_P7_U1_PLD_IT2, 0x40010e88
 4286              	.set CYDEV_UCFG_B0_P7_U1_PLD_IT3, 0x40010e8c
 4287              	.set CYDEV_UCFG_B0_P7_U1_PLD_IT4, 0x40010e90
 4288              	.set CYDEV_UCFG_B0_P7_U1_PLD_IT5, 0x40010e94
 4289              	.set CYDEV_UCFG_B0_P7_U1_PLD_IT6, 0x40010e98
 4290              	.set CYDEV_UCFG_B0_P7_U1_PLD_IT7, 0x40010e9c
 4291              	.set CYDEV_UCFG_B0_P7_U1_PLD_IT8, 0x40010ea0
 4292              	.set CYDEV_UCFG_B0_P7_U1_PLD_IT9, 0x40010ea4
 4293              	.set CYDEV_UCFG_B0_P7_U1_PLD_IT10, 0x40010ea8
 4294              	.set CYDEV_UCFG_B0_P7_U1_PLD_IT11, 0x40010eac
 4295              	.set CYDEV_UCFG_B0_P7_U1_PLD_ORT0, 0x40010eb0
 4296              	.set CYDEV_UCFG_B0_P7_U1_PLD_ORT1, 0x40010eb2
 4297              	.set CYDEV_UCFG_B0_P7_U1_PLD_ORT2, 0x40010eb4
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 77


 4298              	.set CYDEV_UCFG_B0_P7_U1_PLD_ORT3, 0x40010eb6
 4299              	.set CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST, 0x40010eb8
 4300              	.set CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB, 0x40010eba
 4301              	.set CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET, 0x40010ebc
 4302              	.set CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS, 0x40010ebe
 4303              	.set CYDEV_UCFG_B0_P7_U1_CFG0, 0x40010ec0
 4304              	.set CYDEV_UCFG_B0_P7_U1_CFG1, 0x40010ec1
 4305              	.set CYDEV_UCFG_B0_P7_U1_CFG2, 0x40010ec2
 4306              	.set CYDEV_UCFG_B0_P7_U1_CFG3, 0x40010ec3
 4307              	.set CYDEV_UCFG_B0_P7_U1_CFG4, 0x40010ec4
 4308              	.set CYDEV_UCFG_B0_P7_U1_CFG5, 0x40010ec5
 4309              	.set CYDEV_UCFG_B0_P7_U1_CFG6, 0x40010ec6
 4310              	.set CYDEV_UCFG_B0_P7_U1_CFG7, 0x40010ec7
 4311              	.set CYDEV_UCFG_B0_P7_U1_CFG8, 0x40010ec8
 4312              	.set CYDEV_UCFG_B0_P7_U1_CFG9, 0x40010ec9
 4313              	.set CYDEV_UCFG_B0_P7_U1_CFG10, 0x40010eca
 4314              	.set CYDEV_UCFG_B0_P7_U1_CFG11, 0x40010ecb
 4315              	.set CYDEV_UCFG_B0_P7_U1_CFG12, 0x40010ecc
 4316              	.set CYDEV_UCFG_B0_P7_U1_CFG13, 0x40010ecd
 4317              	.set CYDEV_UCFG_B0_P7_U1_CFG14, 0x40010ece
 4318              	.set CYDEV_UCFG_B0_P7_U1_CFG15, 0x40010ecf
 4319              	.set CYDEV_UCFG_B0_P7_U1_CFG16, 0x40010ed0
 4320              	.set CYDEV_UCFG_B0_P7_U1_CFG17, 0x40010ed1
 4321              	.set CYDEV_UCFG_B0_P7_U1_CFG18, 0x40010ed2
 4322              	.set CYDEV_UCFG_B0_P7_U1_CFG19, 0x40010ed3
 4323              	.set CYDEV_UCFG_B0_P7_U1_CFG20, 0x40010ed4
 4324              	.set CYDEV_UCFG_B0_P7_U1_CFG21, 0x40010ed5
 4325              	.set CYDEV_UCFG_B0_P7_U1_CFG22, 0x40010ed6
 4326              	.set CYDEV_UCFG_B0_P7_U1_CFG23, 0x40010ed7
 4327              	.set CYDEV_UCFG_B0_P7_U1_CFG24, 0x40010ed8
 4328              	.set CYDEV_UCFG_B0_P7_U1_CFG25, 0x40010ed9
 4329              	.set CYDEV_UCFG_B0_P7_U1_CFG26, 0x40010eda
 4330              	.set CYDEV_UCFG_B0_P7_U1_CFG27, 0x40010edb
 4331              	.set CYDEV_UCFG_B0_P7_U1_CFG28, 0x40010edc
 4332              	.set CYDEV_UCFG_B0_P7_U1_CFG29, 0x40010edd
 4333              	.set CYDEV_UCFG_B0_P7_U1_CFG30, 0x40010ede
 4334              	.set CYDEV_UCFG_B0_P7_U1_CFG31, 0x40010edf
 4335              	.set CYDEV_UCFG_B0_P7_U1_DCFG0, 0x40010ee0
 4336              	.set CYDEV_UCFG_B0_P7_U1_DCFG1, 0x40010ee2
 4337              	.set CYDEV_UCFG_B0_P7_U1_DCFG2, 0x40010ee4
 4338              	.set CYDEV_UCFG_B0_P7_U1_DCFG3, 0x40010ee6
 4339              	.set CYDEV_UCFG_B0_P7_U1_DCFG4, 0x40010ee8
 4340              	.set CYDEV_UCFG_B0_P7_U1_DCFG5, 0x40010eea
 4341              	.set CYDEV_UCFG_B0_P7_U1_DCFG6, 0x40010eec
 4342              	.set CYDEV_UCFG_B0_P7_U1_DCFG7, 0x40010eee
 4343              	.set CYDEV_UCFG_B0_P7_ROUTE_BASE, 0x40010f00
 4344              	.set CYDEV_UCFG_B0_P7_ROUTE_SIZE, 0x000000ef
 4345              	.set CYDEV_UCFG_B1_BASE, 0x40011000
 4346              	.set CYDEV_UCFG_B1_SIZE, 0x00000fef
 4347              	.set CYDEV_UCFG_B1_P2_BASE, 0x40011400
 4348              	.set CYDEV_UCFG_B1_P2_SIZE, 0x000001ef
 4349              	.set CYDEV_UCFG_B1_P2_U0_BASE, 0x40011400
 4350              	.set CYDEV_UCFG_B1_P2_U0_SIZE, 0x00000070
 4351              	.set CYDEV_UCFG_B1_P2_U0_PLD_IT0, 0x40011400
 4352              	.set CYDEV_UCFG_B1_P2_U0_PLD_IT1, 0x40011404
 4353              	.set CYDEV_UCFG_B1_P2_U0_PLD_IT2, 0x40011408
 4354              	.set CYDEV_UCFG_B1_P2_U0_PLD_IT3, 0x4001140c
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 78


 4355              	.set CYDEV_UCFG_B1_P2_U0_PLD_IT4, 0x40011410
 4356              	.set CYDEV_UCFG_B1_P2_U0_PLD_IT5, 0x40011414
 4357              	.set CYDEV_UCFG_B1_P2_U0_PLD_IT6, 0x40011418
 4358              	.set CYDEV_UCFG_B1_P2_U0_PLD_IT7, 0x4001141c
 4359              	.set CYDEV_UCFG_B1_P2_U0_PLD_IT8, 0x40011420
 4360              	.set CYDEV_UCFG_B1_P2_U0_PLD_IT9, 0x40011424
 4361              	.set CYDEV_UCFG_B1_P2_U0_PLD_IT10, 0x40011428
 4362              	.set CYDEV_UCFG_B1_P2_U0_PLD_IT11, 0x4001142c
 4363              	.set CYDEV_UCFG_B1_P2_U0_PLD_ORT0, 0x40011430
 4364              	.set CYDEV_UCFG_B1_P2_U0_PLD_ORT1, 0x40011432
 4365              	.set CYDEV_UCFG_B1_P2_U0_PLD_ORT2, 0x40011434
 4366              	.set CYDEV_UCFG_B1_P2_U0_PLD_ORT3, 0x40011436
 4367              	.set CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST, 0x40011438
 4368              	.set CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB, 0x4001143a
 4369              	.set CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET, 0x4001143c
 4370              	.set CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS, 0x4001143e
 4371              	.set CYDEV_UCFG_B1_P2_U0_CFG0, 0x40011440
 4372              	.set CYDEV_UCFG_B1_P2_U0_CFG1, 0x40011441
 4373              	.set CYDEV_UCFG_B1_P2_U0_CFG2, 0x40011442
 4374              	.set CYDEV_UCFG_B1_P2_U0_CFG3, 0x40011443
 4375              	.set CYDEV_UCFG_B1_P2_U0_CFG4, 0x40011444
 4376              	.set CYDEV_UCFG_B1_P2_U0_CFG5, 0x40011445
 4377              	.set CYDEV_UCFG_B1_P2_U0_CFG6, 0x40011446
 4378              	.set CYDEV_UCFG_B1_P2_U0_CFG7, 0x40011447
 4379              	.set CYDEV_UCFG_B1_P2_U0_CFG8, 0x40011448
 4380              	.set CYDEV_UCFG_B1_P2_U0_CFG9, 0x40011449
 4381              	.set CYDEV_UCFG_B1_P2_U0_CFG10, 0x4001144a
 4382              	.set CYDEV_UCFG_B1_P2_U0_CFG11, 0x4001144b
 4383              	.set CYDEV_UCFG_B1_P2_U0_CFG12, 0x4001144c
 4384              	.set CYDEV_UCFG_B1_P2_U0_CFG13, 0x4001144d
 4385              	.set CYDEV_UCFG_B1_P2_U0_CFG14, 0x4001144e
 4386              	.set CYDEV_UCFG_B1_P2_U0_CFG15, 0x4001144f
 4387              	.set CYDEV_UCFG_B1_P2_U0_CFG16, 0x40011450
 4388              	.set CYDEV_UCFG_B1_P2_U0_CFG17, 0x40011451
 4389              	.set CYDEV_UCFG_B1_P2_U0_CFG18, 0x40011452
 4390              	.set CYDEV_UCFG_B1_P2_U0_CFG19, 0x40011453
 4391              	.set CYDEV_UCFG_B1_P2_U0_CFG20, 0x40011454
 4392              	.set CYDEV_UCFG_B1_P2_U0_CFG21, 0x40011455
 4393              	.set CYDEV_UCFG_B1_P2_U0_CFG22, 0x40011456
 4394              	.set CYDEV_UCFG_B1_P2_U0_CFG23, 0x40011457
 4395              	.set CYDEV_UCFG_B1_P2_U0_CFG24, 0x40011458
 4396              	.set CYDEV_UCFG_B1_P2_U0_CFG25, 0x40011459
 4397              	.set CYDEV_UCFG_B1_P2_U0_CFG26, 0x4001145a
 4398              	.set CYDEV_UCFG_B1_P2_U0_CFG27, 0x4001145b
 4399              	.set CYDEV_UCFG_B1_P2_U0_CFG28, 0x4001145c
 4400              	.set CYDEV_UCFG_B1_P2_U0_CFG29, 0x4001145d
 4401              	.set CYDEV_UCFG_B1_P2_U0_CFG30, 0x4001145e
 4402              	.set CYDEV_UCFG_B1_P2_U0_CFG31, 0x4001145f
 4403              	.set CYDEV_UCFG_B1_P2_U0_DCFG0, 0x40011460
 4404              	.set CYDEV_UCFG_B1_P2_U0_DCFG1, 0x40011462
 4405              	.set CYDEV_UCFG_B1_P2_U0_DCFG2, 0x40011464
 4406              	.set CYDEV_UCFG_B1_P2_U0_DCFG3, 0x40011466
 4407              	.set CYDEV_UCFG_B1_P2_U0_DCFG4, 0x40011468
 4408              	.set CYDEV_UCFG_B1_P2_U0_DCFG5, 0x4001146a
 4409              	.set CYDEV_UCFG_B1_P2_U0_DCFG6, 0x4001146c
 4410              	.set CYDEV_UCFG_B1_P2_U0_DCFG7, 0x4001146e
 4411              	.set CYDEV_UCFG_B1_P2_U1_BASE, 0x40011480
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 79


 4412              	.set CYDEV_UCFG_B1_P2_U1_SIZE, 0x00000070
 4413              	.set CYDEV_UCFG_B1_P2_U1_PLD_IT0, 0x40011480
 4414              	.set CYDEV_UCFG_B1_P2_U1_PLD_IT1, 0x40011484
 4415              	.set CYDEV_UCFG_B1_P2_U1_PLD_IT2, 0x40011488
 4416              	.set CYDEV_UCFG_B1_P2_U1_PLD_IT3, 0x4001148c
 4417              	.set CYDEV_UCFG_B1_P2_U1_PLD_IT4, 0x40011490
 4418              	.set CYDEV_UCFG_B1_P2_U1_PLD_IT5, 0x40011494
 4419              	.set CYDEV_UCFG_B1_P2_U1_PLD_IT6, 0x40011498
 4420              	.set CYDEV_UCFG_B1_P2_U1_PLD_IT7, 0x4001149c
 4421              	.set CYDEV_UCFG_B1_P2_U1_PLD_IT8, 0x400114a0
 4422              	.set CYDEV_UCFG_B1_P2_U1_PLD_IT9, 0x400114a4
 4423              	.set CYDEV_UCFG_B1_P2_U1_PLD_IT10, 0x400114a8
 4424              	.set CYDEV_UCFG_B1_P2_U1_PLD_IT11, 0x400114ac
 4425              	.set CYDEV_UCFG_B1_P2_U1_PLD_ORT0, 0x400114b0
 4426              	.set CYDEV_UCFG_B1_P2_U1_PLD_ORT1, 0x400114b2
 4427              	.set CYDEV_UCFG_B1_P2_U1_PLD_ORT2, 0x400114b4
 4428              	.set CYDEV_UCFG_B1_P2_U1_PLD_ORT3, 0x400114b6
 4429              	.set CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST, 0x400114b8
 4430              	.set CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB, 0x400114ba
 4431              	.set CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET, 0x400114bc
 4432              	.set CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS, 0x400114be
 4433              	.set CYDEV_UCFG_B1_P2_U1_CFG0, 0x400114c0
 4434              	.set CYDEV_UCFG_B1_P2_U1_CFG1, 0x400114c1
 4435              	.set CYDEV_UCFG_B1_P2_U1_CFG2, 0x400114c2
 4436              	.set CYDEV_UCFG_B1_P2_U1_CFG3, 0x400114c3
 4437              	.set CYDEV_UCFG_B1_P2_U1_CFG4, 0x400114c4
 4438              	.set CYDEV_UCFG_B1_P2_U1_CFG5, 0x400114c5
 4439              	.set CYDEV_UCFG_B1_P2_U1_CFG6, 0x400114c6
 4440              	.set CYDEV_UCFG_B1_P2_U1_CFG7, 0x400114c7
 4441              	.set CYDEV_UCFG_B1_P2_U1_CFG8, 0x400114c8
 4442              	.set CYDEV_UCFG_B1_P2_U1_CFG9, 0x400114c9
 4443              	.set CYDEV_UCFG_B1_P2_U1_CFG10, 0x400114ca
 4444              	.set CYDEV_UCFG_B1_P2_U1_CFG11, 0x400114cb
 4445              	.set CYDEV_UCFG_B1_P2_U1_CFG12, 0x400114cc
 4446              	.set CYDEV_UCFG_B1_P2_U1_CFG13, 0x400114cd
 4447              	.set CYDEV_UCFG_B1_P2_U1_CFG14, 0x400114ce
 4448              	.set CYDEV_UCFG_B1_P2_U1_CFG15, 0x400114cf
 4449              	.set CYDEV_UCFG_B1_P2_U1_CFG16, 0x400114d0
 4450              	.set CYDEV_UCFG_B1_P2_U1_CFG17, 0x400114d1
 4451              	.set CYDEV_UCFG_B1_P2_U1_CFG18, 0x400114d2
 4452              	.set CYDEV_UCFG_B1_P2_U1_CFG19, 0x400114d3
 4453              	.set CYDEV_UCFG_B1_P2_U1_CFG20, 0x400114d4
 4454              	.set CYDEV_UCFG_B1_P2_U1_CFG21, 0x400114d5
 4455              	.set CYDEV_UCFG_B1_P2_U1_CFG22, 0x400114d6
 4456              	.set CYDEV_UCFG_B1_P2_U1_CFG23, 0x400114d7
 4457              	.set CYDEV_UCFG_B1_P2_U1_CFG24, 0x400114d8
 4458              	.set CYDEV_UCFG_B1_P2_U1_CFG25, 0x400114d9
 4459              	.set CYDEV_UCFG_B1_P2_U1_CFG26, 0x400114da
 4460              	.set CYDEV_UCFG_B1_P2_U1_CFG27, 0x400114db
 4461              	.set CYDEV_UCFG_B1_P2_U1_CFG28, 0x400114dc
 4462              	.set CYDEV_UCFG_B1_P2_U1_CFG29, 0x400114dd
 4463              	.set CYDEV_UCFG_B1_P2_U1_CFG30, 0x400114de
 4464              	.set CYDEV_UCFG_B1_P2_U1_CFG31, 0x400114df
 4465              	.set CYDEV_UCFG_B1_P2_U1_DCFG0, 0x400114e0
 4466              	.set CYDEV_UCFG_B1_P2_U1_DCFG1, 0x400114e2
 4467              	.set CYDEV_UCFG_B1_P2_U1_DCFG2, 0x400114e4
 4468              	.set CYDEV_UCFG_B1_P2_U1_DCFG3, 0x400114e6
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 80


 4469              	.set CYDEV_UCFG_B1_P2_U1_DCFG4, 0x400114e8
 4470              	.set CYDEV_UCFG_B1_P2_U1_DCFG5, 0x400114ea
 4471              	.set CYDEV_UCFG_B1_P2_U1_DCFG6, 0x400114ec
 4472              	.set CYDEV_UCFG_B1_P2_U1_DCFG7, 0x400114ee
 4473              	.set CYDEV_UCFG_B1_P2_ROUTE_BASE, 0x40011500
 4474              	.set CYDEV_UCFG_B1_P2_ROUTE_SIZE, 0x000000ef
 4475              	.set CYDEV_UCFG_B1_P3_BASE, 0x40011600
 4476              	.set CYDEV_UCFG_B1_P3_SIZE, 0x000001ef
 4477              	.set CYDEV_UCFG_B1_P3_U0_BASE, 0x40011600
 4478              	.set CYDEV_UCFG_B1_P3_U0_SIZE, 0x00000070
 4479              	.set CYDEV_UCFG_B1_P3_U0_PLD_IT0, 0x40011600
 4480              	.set CYDEV_UCFG_B1_P3_U0_PLD_IT1, 0x40011604
 4481              	.set CYDEV_UCFG_B1_P3_U0_PLD_IT2, 0x40011608
 4482              	.set CYDEV_UCFG_B1_P3_U0_PLD_IT3, 0x4001160c
 4483              	.set CYDEV_UCFG_B1_P3_U0_PLD_IT4, 0x40011610
 4484              	.set CYDEV_UCFG_B1_P3_U0_PLD_IT5, 0x40011614
 4485              	.set CYDEV_UCFG_B1_P3_U0_PLD_IT6, 0x40011618
 4486              	.set CYDEV_UCFG_B1_P3_U0_PLD_IT7, 0x4001161c
 4487              	.set CYDEV_UCFG_B1_P3_U0_PLD_IT8, 0x40011620
 4488              	.set CYDEV_UCFG_B1_P3_U0_PLD_IT9, 0x40011624
 4489              	.set CYDEV_UCFG_B1_P3_U0_PLD_IT10, 0x40011628
 4490              	.set CYDEV_UCFG_B1_P3_U0_PLD_IT11, 0x4001162c
 4491              	.set CYDEV_UCFG_B1_P3_U0_PLD_ORT0, 0x40011630
 4492              	.set CYDEV_UCFG_B1_P3_U0_PLD_ORT1, 0x40011632
 4493              	.set CYDEV_UCFG_B1_P3_U0_PLD_ORT2, 0x40011634
 4494              	.set CYDEV_UCFG_B1_P3_U0_PLD_ORT3, 0x40011636
 4495              	.set CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST, 0x40011638
 4496              	.set CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB, 0x4001163a
 4497              	.set CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET, 0x4001163c
 4498              	.set CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS, 0x4001163e
 4499              	.set CYDEV_UCFG_B1_P3_U0_CFG0, 0x40011640
 4500              	.set CYDEV_UCFG_B1_P3_U0_CFG1, 0x40011641
 4501              	.set CYDEV_UCFG_B1_P3_U0_CFG2, 0x40011642
 4502              	.set CYDEV_UCFG_B1_P3_U0_CFG3, 0x40011643
 4503              	.set CYDEV_UCFG_B1_P3_U0_CFG4, 0x40011644
 4504              	.set CYDEV_UCFG_B1_P3_U0_CFG5, 0x40011645
 4505              	.set CYDEV_UCFG_B1_P3_U0_CFG6, 0x40011646
 4506              	.set CYDEV_UCFG_B1_P3_U0_CFG7, 0x40011647
 4507              	.set CYDEV_UCFG_B1_P3_U0_CFG8, 0x40011648
 4508              	.set CYDEV_UCFG_B1_P3_U0_CFG9, 0x40011649
 4509              	.set CYDEV_UCFG_B1_P3_U0_CFG10, 0x4001164a
 4510              	.set CYDEV_UCFG_B1_P3_U0_CFG11, 0x4001164b
 4511              	.set CYDEV_UCFG_B1_P3_U0_CFG12, 0x4001164c
 4512              	.set CYDEV_UCFG_B1_P3_U0_CFG13, 0x4001164d
 4513              	.set CYDEV_UCFG_B1_P3_U0_CFG14, 0x4001164e
 4514              	.set CYDEV_UCFG_B1_P3_U0_CFG15, 0x4001164f
 4515              	.set CYDEV_UCFG_B1_P3_U0_CFG16, 0x40011650
 4516              	.set CYDEV_UCFG_B1_P3_U0_CFG17, 0x40011651
 4517              	.set CYDEV_UCFG_B1_P3_U0_CFG18, 0x40011652
 4518              	.set CYDEV_UCFG_B1_P3_U0_CFG19, 0x40011653
 4519              	.set CYDEV_UCFG_B1_P3_U0_CFG20, 0x40011654
 4520              	.set CYDEV_UCFG_B1_P3_U0_CFG21, 0x40011655
 4521              	.set CYDEV_UCFG_B1_P3_U0_CFG22, 0x40011656
 4522              	.set CYDEV_UCFG_B1_P3_U0_CFG23, 0x40011657
 4523              	.set CYDEV_UCFG_B1_P3_U0_CFG24, 0x40011658
 4524              	.set CYDEV_UCFG_B1_P3_U0_CFG25, 0x40011659
 4525              	.set CYDEV_UCFG_B1_P3_U0_CFG26, 0x4001165a
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 81


 4526              	.set CYDEV_UCFG_B1_P3_U0_CFG27, 0x4001165b
 4527              	.set CYDEV_UCFG_B1_P3_U0_CFG28, 0x4001165c
 4528              	.set CYDEV_UCFG_B1_P3_U0_CFG29, 0x4001165d
 4529              	.set CYDEV_UCFG_B1_P3_U0_CFG30, 0x4001165e
 4530              	.set CYDEV_UCFG_B1_P3_U0_CFG31, 0x4001165f
 4531              	.set CYDEV_UCFG_B1_P3_U0_DCFG0, 0x40011660
 4532              	.set CYDEV_UCFG_B1_P3_U0_DCFG1, 0x40011662
 4533              	.set CYDEV_UCFG_B1_P3_U0_DCFG2, 0x40011664
 4534              	.set CYDEV_UCFG_B1_P3_U0_DCFG3, 0x40011666
 4535              	.set CYDEV_UCFG_B1_P3_U0_DCFG4, 0x40011668
 4536              	.set CYDEV_UCFG_B1_P3_U0_DCFG5, 0x4001166a
 4537              	.set CYDEV_UCFG_B1_P3_U0_DCFG6, 0x4001166c
 4538              	.set CYDEV_UCFG_B1_P3_U0_DCFG7, 0x4001166e
 4539              	.set CYDEV_UCFG_B1_P3_U1_BASE, 0x40011680
 4540              	.set CYDEV_UCFG_B1_P3_U1_SIZE, 0x00000070
 4541              	.set CYDEV_UCFG_B1_P3_U1_PLD_IT0, 0x40011680
 4542              	.set CYDEV_UCFG_B1_P3_U1_PLD_IT1, 0x40011684
 4543              	.set CYDEV_UCFG_B1_P3_U1_PLD_IT2, 0x40011688
 4544              	.set CYDEV_UCFG_B1_P3_U1_PLD_IT3, 0x4001168c
 4545              	.set CYDEV_UCFG_B1_P3_U1_PLD_IT4, 0x40011690
 4546              	.set CYDEV_UCFG_B1_P3_U1_PLD_IT5, 0x40011694
 4547              	.set CYDEV_UCFG_B1_P3_U1_PLD_IT6, 0x40011698
 4548              	.set CYDEV_UCFG_B1_P3_U1_PLD_IT7, 0x4001169c
 4549              	.set CYDEV_UCFG_B1_P3_U1_PLD_IT8, 0x400116a0
 4550              	.set CYDEV_UCFG_B1_P3_U1_PLD_IT9, 0x400116a4
 4551              	.set CYDEV_UCFG_B1_P3_U1_PLD_IT10, 0x400116a8
 4552              	.set CYDEV_UCFG_B1_P3_U1_PLD_IT11, 0x400116ac
 4553              	.set CYDEV_UCFG_B1_P3_U1_PLD_ORT0, 0x400116b0
 4554              	.set CYDEV_UCFG_B1_P3_U1_PLD_ORT1, 0x400116b2
 4555              	.set CYDEV_UCFG_B1_P3_U1_PLD_ORT2, 0x400116b4
 4556              	.set CYDEV_UCFG_B1_P3_U1_PLD_ORT3, 0x400116b6
 4557              	.set CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST, 0x400116b8
 4558              	.set CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB, 0x400116ba
 4559              	.set CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET, 0x400116bc
 4560              	.set CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS, 0x400116be
 4561              	.set CYDEV_UCFG_B1_P3_U1_CFG0, 0x400116c0
 4562              	.set CYDEV_UCFG_B1_P3_U1_CFG1, 0x400116c1
 4563              	.set CYDEV_UCFG_B1_P3_U1_CFG2, 0x400116c2
 4564              	.set CYDEV_UCFG_B1_P3_U1_CFG3, 0x400116c3
 4565              	.set CYDEV_UCFG_B1_P3_U1_CFG4, 0x400116c4
 4566              	.set CYDEV_UCFG_B1_P3_U1_CFG5, 0x400116c5
 4567              	.set CYDEV_UCFG_B1_P3_U1_CFG6, 0x400116c6
 4568              	.set CYDEV_UCFG_B1_P3_U1_CFG7, 0x400116c7
 4569              	.set CYDEV_UCFG_B1_P3_U1_CFG8, 0x400116c8
 4570              	.set CYDEV_UCFG_B1_P3_U1_CFG9, 0x400116c9
 4571              	.set CYDEV_UCFG_B1_P3_U1_CFG10, 0x400116ca
 4572              	.set CYDEV_UCFG_B1_P3_U1_CFG11, 0x400116cb
 4573              	.set CYDEV_UCFG_B1_P3_U1_CFG12, 0x400116cc
 4574              	.set CYDEV_UCFG_B1_P3_U1_CFG13, 0x400116cd
 4575              	.set CYDEV_UCFG_B1_P3_U1_CFG14, 0x400116ce
 4576              	.set CYDEV_UCFG_B1_P3_U1_CFG15, 0x400116cf
 4577              	.set CYDEV_UCFG_B1_P3_U1_CFG16, 0x400116d0
 4578              	.set CYDEV_UCFG_B1_P3_U1_CFG17, 0x400116d1
 4579              	.set CYDEV_UCFG_B1_P3_U1_CFG18, 0x400116d2
 4580              	.set CYDEV_UCFG_B1_P3_U1_CFG19, 0x400116d3
 4581              	.set CYDEV_UCFG_B1_P3_U1_CFG20, 0x400116d4
 4582              	.set CYDEV_UCFG_B1_P3_U1_CFG21, 0x400116d5
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 82


 4583              	.set CYDEV_UCFG_B1_P3_U1_CFG22, 0x400116d6
 4584              	.set CYDEV_UCFG_B1_P3_U1_CFG23, 0x400116d7
 4585              	.set CYDEV_UCFG_B1_P3_U1_CFG24, 0x400116d8
 4586              	.set CYDEV_UCFG_B1_P3_U1_CFG25, 0x400116d9
 4587              	.set CYDEV_UCFG_B1_P3_U1_CFG26, 0x400116da
 4588              	.set CYDEV_UCFG_B1_P3_U1_CFG27, 0x400116db
 4589              	.set CYDEV_UCFG_B1_P3_U1_CFG28, 0x400116dc
 4590              	.set CYDEV_UCFG_B1_P3_U1_CFG29, 0x400116dd
 4591              	.set CYDEV_UCFG_B1_P3_U1_CFG30, 0x400116de
 4592              	.set CYDEV_UCFG_B1_P3_U1_CFG31, 0x400116df
 4593              	.set CYDEV_UCFG_B1_P3_U1_DCFG0, 0x400116e0
 4594              	.set CYDEV_UCFG_B1_P3_U1_DCFG1, 0x400116e2
 4595              	.set CYDEV_UCFG_B1_P3_U1_DCFG2, 0x400116e4
 4596              	.set CYDEV_UCFG_B1_P3_U1_DCFG3, 0x400116e6
 4597              	.set CYDEV_UCFG_B1_P3_U1_DCFG4, 0x400116e8
 4598              	.set CYDEV_UCFG_B1_P3_U1_DCFG5, 0x400116ea
 4599              	.set CYDEV_UCFG_B1_P3_U1_DCFG6, 0x400116ec
 4600              	.set CYDEV_UCFG_B1_P3_U1_DCFG7, 0x400116ee
 4601              	.set CYDEV_UCFG_B1_P3_ROUTE_BASE, 0x40011700
 4602              	.set CYDEV_UCFG_B1_P3_ROUTE_SIZE, 0x000000ef
 4603              	.set CYDEV_UCFG_B1_P4_BASE, 0x40011800
 4604              	.set CYDEV_UCFG_B1_P4_SIZE, 0x000001ef
 4605              	.set CYDEV_UCFG_B1_P4_U0_BASE, 0x40011800
 4606              	.set CYDEV_UCFG_B1_P4_U0_SIZE, 0x00000070
 4607              	.set CYDEV_UCFG_B1_P4_U0_PLD_IT0, 0x40011800
 4608              	.set CYDEV_UCFG_B1_P4_U0_PLD_IT1, 0x40011804
 4609              	.set CYDEV_UCFG_B1_P4_U0_PLD_IT2, 0x40011808
 4610              	.set CYDEV_UCFG_B1_P4_U0_PLD_IT3, 0x4001180c
 4611              	.set CYDEV_UCFG_B1_P4_U0_PLD_IT4, 0x40011810
 4612              	.set CYDEV_UCFG_B1_P4_U0_PLD_IT5, 0x40011814
 4613              	.set CYDEV_UCFG_B1_P4_U0_PLD_IT6, 0x40011818
 4614              	.set CYDEV_UCFG_B1_P4_U0_PLD_IT7, 0x4001181c
 4615              	.set CYDEV_UCFG_B1_P4_U0_PLD_IT8, 0x40011820
 4616              	.set CYDEV_UCFG_B1_P4_U0_PLD_IT9, 0x40011824
 4617              	.set CYDEV_UCFG_B1_P4_U0_PLD_IT10, 0x40011828
 4618              	.set CYDEV_UCFG_B1_P4_U0_PLD_IT11, 0x4001182c
 4619              	.set CYDEV_UCFG_B1_P4_U0_PLD_ORT0, 0x40011830
 4620              	.set CYDEV_UCFG_B1_P4_U0_PLD_ORT1, 0x40011832
 4621              	.set CYDEV_UCFG_B1_P4_U0_PLD_ORT2, 0x40011834
 4622              	.set CYDEV_UCFG_B1_P4_U0_PLD_ORT3, 0x40011836
 4623              	.set CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST, 0x40011838
 4624              	.set CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB, 0x4001183a
 4625              	.set CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET, 0x4001183c
 4626              	.set CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS, 0x4001183e
 4627              	.set CYDEV_UCFG_B1_P4_U0_CFG0, 0x40011840
 4628              	.set CYDEV_UCFG_B1_P4_U0_CFG1, 0x40011841
 4629              	.set CYDEV_UCFG_B1_P4_U0_CFG2, 0x40011842
 4630              	.set CYDEV_UCFG_B1_P4_U0_CFG3, 0x40011843
 4631              	.set CYDEV_UCFG_B1_P4_U0_CFG4, 0x40011844
 4632              	.set CYDEV_UCFG_B1_P4_U0_CFG5, 0x40011845
 4633              	.set CYDEV_UCFG_B1_P4_U0_CFG6, 0x40011846
 4634              	.set CYDEV_UCFG_B1_P4_U0_CFG7, 0x40011847
 4635              	.set CYDEV_UCFG_B1_P4_U0_CFG8, 0x40011848
 4636              	.set CYDEV_UCFG_B1_P4_U0_CFG9, 0x40011849
 4637              	.set CYDEV_UCFG_B1_P4_U0_CFG10, 0x4001184a
 4638              	.set CYDEV_UCFG_B1_P4_U0_CFG11, 0x4001184b
 4639              	.set CYDEV_UCFG_B1_P4_U0_CFG12, 0x4001184c
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 83


 4640              	.set CYDEV_UCFG_B1_P4_U0_CFG13, 0x4001184d
 4641              	.set CYDEV_UCFG_B1_P4_U0_CFG14, 0x4001184e
 4642              	.set CYDEV_UCFG_B1_P4_U0_CFG15, 0x4001184f
 4643              	.set CYDEV_UCFG_B1_P4_U0_CFG16, 0x40011850
 4644              	.set CYDEV_UCFG_B1_P4_U0_CFG17, 0x40011851
 4645              	.set CYDEV_UCFG_B1_P4_U0_CFG18, 0x40011852
 4646              	.set CYDEV_UCFG_B1_P4_U0_CFG19, 0x40011853
 4647              	.set CYDEV_UCFG_B1_P4_U0_CFG20, 0x40011854
 4648              	.set CYDEV_UCFG_B1_P4_U0_CFG21, 0x40011855
 4649              	.set CYDEV_UCFG_B1_P4_U0_CFG22, 0x40011856
 4650              	.set CYDEV_UCFG_B1_P4_U0_CFG23, 0x40011857
 4651              	.set CYDEV_UCFG_B1_P4_U0_CFG24, 0x40011858
 4652              	.set CYDEV_UCFG_B1_P4_U0_CFG25, 0x40011859
 4653              	.set CYDEV_UCFG_B1_P4_U0_CFG26, 0x4001185a
 4654              	.set CYDEV_UCFG_B1_P4_U0_CFG27, 0x4001185b
 4655              	.set CYDEV_UCFG_B1_P4_U0_CFG28, 0x4001185c
 4656              	.set CYDEV_UCFG_B1_P4_U0_CFG29, 0x4001185d
 4657              	.set CYDEV_UCFG_B1_P4_U0_CFG30, 0x4001185e
 4658              	.set CYDEV_UCFG_B1_P4_U0_CFG31, 0x4001185f
 4659              	.set CYDEV_UCFG_B1_P4_U0_DCFG0, 0x40011860
 4660              	.set CYDEV_UCFG_B1_P4_U0_DCFG1, 0x40011862
 4661              	.set CYDEV_UCFG_B1_P4_U0_DCFG2, 0x40011864
 4662              	.set CYDEV_UCFG_B1_P4_U0_DCFG3, 0x40011866
 4663              	.set CYDEV_UCFG_B1_P4_U0_DCFG4, 0x40011868
 4664              	.set CYDEV_UCFG_B1_P4_U0_DCFG5, 0x4001186a
 4665              	.set CYDEV_UCFG_B1_P4_U0_DCFG6, 0x4001186c
 4666              	.set CYDEV_UCFG_B1_P4_U0_DCFG7, 0x4001186e
 4667              	.set CYDEV_UCFG_B1_P4_U1_BASE, 0x40011880
 4668              	.set CYDEV_UCFG_B1_P4_U1_SIZE, 0x00000070
 4669              	.set CYDEV_UCFG_B1_P4_U1_PLD_IT0, 0x40011880
 4670              	.set CYDEV_UCFG_B1_P4_U1_PLD_IT1, 0x40011884
 4671              	.set CYDEV_UCFG_B1_P4_U1_PLD_IT2, 0x40011888
 4672              	.set CYDEV_UCFG_B1_P4_U1_PLD_IT3, 0x4001188c
 4673              	.set CYDEV_UCFG_B1_P4_U1_PLD_IT4, 0x40011890
 4674              	.set CYDEV_UCFG_B1_P4_U1_PLD_IT5, 0x40011894
 4675              	.set CYDEV_UCFG_B1_P4_U1_PLD_IT6, 0x40011898
 4676              	.set CYDEV_UCFG_B1_P4_U1_PLD_IT7, 0x4001189c
 4677              	.set CYDEV_UCFG_B1_P4_U1_PLD_IT8, 0x400118a0
 4678              	.set CYDEV_UCFG_B1_P4_U1_PLD_IT9, 0x400118a4
 4679              	.set CYDEV_UCFG_B1_P4_U1_PLD_IT10, 0x400118a8
 4680              	.set CYDEV_UCFG_B1_P4_U1_PLD_IT11, 0x400118ac
 4681              	.set CYDEV_UCFG_B1_P4_U1_PLD_ORT0, 0x400118b0
 4682              	.set CYDEV_UCFG_B1_P4_U1_PLD_ORT1, 0x400118b2
 4683              	.set CYDEV_UCFG_B1_P4_U1_PLD_ORT2, 0x400118b4
 4684              	.set CYDEV_UCFG_B1_P4_U1_PLD_ORT3, 0x400118b6
 4685              	.set CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST, 0x400118b8
 4686              	.set CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB, 0x400118ba
 4687              	.set CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET, 0x400118bc
 4688              	.set CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS, 0x400118be
 4689              	.set CYDEV_UCFG_B1_P4_U1_CFG0, 0x400118c0
 4690              	.set CYDEV_UCFG_B1_P4_U1_CFG1, 0x400118c1
 4691              	.set CYDEV_UCFG_B1_P4_U1_CFG2, 0x400118c2
 4692              	.set CYDEV_UCFG_B1_P4_U1_CFG3, 0x400118c3
 4693              	.set CYDEV_UCFG_B1_P4_U1_CFG4, 0x400118c4
 4694              	.set CYDEV_UCFG_B1_P4_U1_CFG5, 0x400118c5
 4695              	.set CYDEV_UCFG_B1_P4_U1_CFG6, 0x400118c6
 4696              	.set CYDEV_UCFG_B1_P4_U1_CFG7, 0x400118c7
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 84


 4697              	.set CYDEV_UCFG_B1_P4_U1_CFG8, 0x400118c8
 4698              	.set CYDEV_UCFG_B1_P4_U1_CFG9, 0x400118c9
 4699              	.set CYDEV_UCFG_B1_P4_U1_CFG10, 0x400118ca
 4700              	.set CYDEV_UCFG_B1_P4_U1_CFG11, 0x400118cb
 4701              	.set CYDEV_UCFG_B1_P4_U1_CFG12, 0x400118cc
 4702              	.set CYDEV_UCFG_B1_P4_U1_CFG13, 0x400118cd
 4703              	.set CYDEV_UCFG_B1_P4_U1_CFG14, 0x400118ce
 4704              	.set CYDEV_UCFG_B1_P4_U1_CFG15, 0x400118cf
 4705              	.set CYDEV_UCFG_B1_P4_U1_CFG16, 0x400118d0
 4706              	.set CYDEV_UCFG_B1_P4_U1_CFG17, 0x400118d1
 4707              	.set CYDEV_UCFG_B1_P4_U1_CFG18, 0x400118d2
 4708              	.set CYDEV_UCFG_B1_P4_U1_CFG19, 0x400118d3
 4709              	.set CYDEV_UCFG_B1_P4_U1_CFG20, 0x400118d4
 4710              	.set CYDEV_UCFG_B1_P4_U1_CFG21, 0x400118d5
 4711              	.set CYDEV_UCFG_B1_P4_U1_CFG22, 0x400118d6
 4712              	.set CYDEV_UCFG_B1_P4_U1_CFG23, 0x400118d7
 4713              	.set CYDEV_UCFG_B1_P4_U1_CFG24, 0x400118d8
 4714              	.set CYDEV_UCFG_B1_P4_U1_CFG25, 0x400118d9
 4715              	.set CYDEV_UCFG_B1_P4_U1_CFG26, 0x400118da
 4716              	.set CYDEV_UCFG_B1_P4_U1_CFG27, 0x400118db
 4717              	.set CYDEV_UCFG_B1_P4_U1_CFG28, 0x400118dc
 4718              	.set CYDEV_UCFG_B1_P4_U1_CFG29, 0x400118dd
 4719              	.set CYDEV_UCFG_B1_P4_U1_CFG30, 0x400118de
 4720              	.set CYDEV_UCFG_B1_P4_U1_CFG31, 0x400118df
 4721              	.set CYDEV_UCFG_B1_P4_U1_DCFG0, 0x400118e0
 4722              	.set CYDEV_UCFG_B1_P4_U1_DCFG1, 0x400118e2
 4723              	.set CYDEV_UCFG_B1_P4_U1_DCFG2, 0x400118e4
 4724              	.set CYDEV_UCFG_B1_P4_U1_DCFG3, 0x400118e6
 4725              	.set CYDEV_UCFG_B1_P4_U1_DCFG4, 0x400118e8
 4726              	.set CYDEV_UCFG_B1_P4_U1_DCFG5, 0x400118ea
 4727              	.set CYDEV_UCFG_B1_P4_U1_DCFG6, 0x400118ec
 4728              	.set CYDEV_UCFG_B1_P4_U1_DCFG7, 0x400118ee
 4729              	.set CYDEV_UCFG_B1_P4_ROUTE_BASE, 0x40011900
 4730              	.set CYDEV_UCFG_B1_P4_ROUTE_SIZE, 0x000000ef
 4731              	.set CYDEV_UCFG_B1_P5_BASE, 0x40011a00
 4732              	.set CYDEV_UCFG_B1_P5_SIZE, 0x000001ef
 4733              	.set CYDEV_UCFG_B1_P5_U0_BASE, 0x40011a00
 4734              	.set CYDEV_UCFG_B1_P5_U0_SIZE, 0x00000070
 4735              	.set CYDEV_UCFG_B1_P5_U0_PLD_IT0, 0x40011a00
 4736              	.set CYDEV_UCFG_B1_P5_U0_PLD_IT1, 0x40011a04
 4737              	.set CYDEV_UCFG_B1_P5_U0_PLD_IT2, 0x40011a08
 4738              	.set CYDEV_UCFG_B1_P5_U0_PLD_IT3, 0x40011a0c
 4739              	.set CYDEV_UCFG_B1_P5_U0_PLD_IT4, 0x40011a10
 4740              	.set CYDEV_UCFG_B1_P5_U0_PLD_IT5, 0x40011a14
 4741              	.set CYDEV_UCFG_B1_P5_U0_PLD_IT6, 0x40011a18
 4742              	.set CYDEV_UCFG_B1_P5_U0_PLD_IT7, 0x40011a1c
 4743              	.set CYDEV_UCFG_B1_P5_U0_PLD_IT8, 0x40011a20
 4744              	.set CYDEV_UCFG_B1_P5_U0_PLD_IT9, 0x40011a24
 4745              	.set CYDEV_UCFG_B1_P5_U0_PLD_IT10, 0x40011a28
 4746              	.set CYDEV_UCFG_B1_P5_U0_PLD_IT11, 0x40011a2c
 4747              	.set CYDEV_UCFG_B1_P5_U0_PLD_ORT0, 0x40011a30
 4748              	.set CYDEV_UCFG_B1_P5_U0_PLD_ORT1, 0x40011a32
 4749              	.set CYDEV_UCFG_B1_P5_U0_PLD_ORT2, 0x40011a34
 4750              	.set CYDEV_UCFG_B1_P5_U0_PLD_ORT3, 0x40011a36
 4751              	.set CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST, 0x40011a38
 4752              	.set CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB, 0x40011a3a
 4753              	.set CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET, 0x40011a3c
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 85


 4754              	.set CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS, 0x40011a3e
 4755              	.set CYDEV_UCFG_B1_P5_U0_CFG0, 0x40011a40
 4756              	.set CYDEV_UCFG_B1_P5_U0_CFG1, 0x40011a41
 4757              	.set CYDEV_UCFG_B1_P5_U0_CFG2, 0x40011a42
 4758              	.set CYDEV_UCFG_B1_P5_U0_CFG3, 0x40011a43
 4759              	.set CYDEV_UCFG_B1_P5_U0_CFG4, 0x40011a44
 4760              	.set CYDEV_UCFG_B1_P5_U0_CFG5, 0x40011a45
 4761              	.set CYDEV_UCFG_B1_P5_U0_CFG6, 0x40011a46
 4762              	.set CYDEV_UCFG_B1_P5_U0_CFG7, 0x40011a47
 4763              	.set CYDEV_UCFG_B1_P5_U0_CFG8, 0x40011a48
 4764              	.set CYDEV_UCFG_B1_P5_U0_CFG9, 0x40011a49
 4765              	.set CYDEV_UCFG_B1_P5_U0_CFG10, 0x40011a4a
 4766              	.set CYDEV_UCFG_B1_P5_U0_CFG11, 0x40011a4b
 4767              	.set CYDEV_UCFG_B1_P5_U0_CFG12, 0x40011a4c
 4768              	.set CYDEV_UCFG_B1_P5_U0_CFG13, 0x40011a4d
 4769              	.set CYDEV_UCFG_B1_P5_U0_CFG14, 0x40011a4e
 4770              	.set CYDEV_UCFG_B1_P5_U0_CFG15, 0x40011a4f
 4771              	.set CYDEV_UCFG_B1_P5_U0_CFG16, 0x40011a50
 4772              	.set CYDEV_UCFG_B1_P5_U0_CFG17, 0x40011a51
 4773              	.set CYDEV_UCFG_B1_P5_U0_CFG18, 0x40011a52
 4774              	.set CYDEV_UCFG_B1_P5_U0_CFG19, 0x40011a53
 4775              	.set CYDEV_UCFG_B1_P5_U0_CFG20, 0x40011a54
 4776              	.set CYDEV_UCFG_B1_P5_U0_CFG21, 0x40011a55
 4777              	.set CYDEV_UCFG_B1_P5_U0_CFG22, 0x40011a56
 4778              	.set CYDEV_UCFG_B1_P5_U0_CFG23, 0x40011a57
 4779              	.set CYDEV_UCFG_B1_P5_U0_CFG24, 0x40011a58
 4780              	.set CYDEV_UCFG_B1_P5_U0_CFG25, 0x40011a59
 4781              	.set CYDEV_UCFG_B1_P5_U0_CFG26, 0x40011a5a
 4782              	.set CYDEV_UCFG_B1_P5_U0_CFG27, 0x40011a5b
 4783              	.set CYDEV_UCFG_B1_P5_U0_CFG28, 0x40011a5c
 4784              	.set CYDEV_UCFG_B1_P5_U0_CFG29, 0x40011a5d
 4785              	.set CYDEV_UCFG_B1_P5_U0_CFG30, 0x40011a5e
 4786              	.set CYDEV_UCFG_B1_P5_U0_CFG31, 0x40011a5f
 4787              	.set CYDEV_UCFG_B1_P5_U0_DCFG0, 0x40011a60
 4788              	.set CYDEV_UCFG_B1_P5_U0_DCFG1, 0x40011a62
 4789              	.set CYDEV_UCFG_B1_P5_U0_DCFG2, 0x40011a64
 4790              	.set CYDEV_UCFG_B1_P5_U0_DCFG3, 0x40011a66
 4791              	.set CYDEV_UCFG_B1_P5_U0_DCFG4, 0x40011a68
 4792              	.set CYDEV_UCFG_B1_P5_U0_DCFG5, 0x40011a6a
 4793              	.set CYDEV_UCFG_B1_P5_U0_DCFG6, 0x40011a6c
 4794              	.set CYDEV_UCFG_B1_P5_U0_DCFG7, 0x40011a6e
 4795              	.set CYDEV_UCFG_B1_P5_U1_BASE, 0x40011a80
 4796              	.set CYDEV_UCFG_B1_P5_U1_SIZE, 0x00000070
 4797              	.set CYDEV_UCFG_B1_P5_U1_PLD_IT0, 0x40011a80
 4798              	.set CYDEV_UCFG_B1_P5_U1_PLD_IT1, 0x40011a84
 4799              	.set CYDEV_UCFG_B1_P5_U1_PLD_IT2, 0x40011a88
 4800              	.set CYDEV_UCFG_B1_P5_U1_PLD_IT3, 0x40011a8c
 4801              	.set CYDEV_UCFG_B1_P5_U1_PLD_IT4, 0x40011a90
 4802              	.set CYDEV_UCFG_B1_P5_U1_PLD_IT5, 0x40011a94
 4803              	.set CYDEV_UCFG_B1_P5_U1_PLD_IT6, 0x40011a98
 4804              	.set CYDEV_UCFG_B1_P5_U1_PLD_IT7, 0x40011a9c
 4805              	.set CYDEV_UCFG_B1_P5_U1_PLD_IT8, 0x40011aa0
 4806              	.set CYDEV_UCFG_B1_P5_U1_PLD_IT9, 0x40011aa4
 4807              	.set CYDEV_UCFG_B1_P5_U1_PLD_IT10, 0x40011aa8
 4808              	.set CYDEV_UCFG_B1_P5_U1_PLD_IT11, 0x40011aac
 4809              	.set CYDEV_UCFG_B1_P5_U1_PLD_ORT0, 0x40011ab0
 4810              	.set CYDEV_UCFG_B1_P5_U1_PLD_ORT1, 0x40011ab2
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 86


 4811              	.set CYDEV_UCFG_B1_P5_U1_PLD_ORT2, 0x40011ab4
 4812              	.set CYDEV_UCFG_B1_P5_U1_PLD_ORT3, 0x40011ab6
 4813              	.set CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST, 0x40011ab8
 4814              	.set CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB, 0x40011aba
 4815              	.set CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET, 0x40011abc
 4816              	.set CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS, 0x40011abe
 4817              	.set CYDEV_UCFG_B1_P5_U1_CFG0, 0x40011ac0
 4818              	.set CYDEV_UCFG_B1_P5_U1_CFG1, 0x40011ac1
 4819              	.set CYDEV_UCFG_B1_P5_U1_CFG2, 0x40011ac2
 4820              	.set CYDEV_UCFG_B1_P5_U1_CFG3, 0x40011ac3
 4821              	.set CYDEV_UCFG_B1_P5_U1_CFG4, 0x40011ac4
 4822              	.set CYDEV_UCFG_B1_P5_U1_CFG5, 0x40011ac5
 4823              	.set CYDEV_UCFG_B1_P5_U1_CFG6, 0x40011ac6
 4824              	.set CYDEV_UCFG_B1_P5_U1_CFG7, 0x40011ac7
 4825              	.set CYDEV_UCFG_B1_P5_U1_CFG8, 0x40011ac8
 4826              	.set CYDEV_UCFG_B1_P5_U1_CFG9, 0x40011ac9
 4827              	.set CYDEV_UCFG_B1_P5_U1_CFG10, 0x40011aca
 4828              	.set CYDEV_UCFG_B1_P5_U1_CFG11, 0x40011acb
 4829              	.set CYDEV_UCFG_B1_P5_U1_CFG12, 0x40011acc
 4830              	.set CYDEV_UCFG_B1_P5_U1_CFG13, 0x40011acd
 4831              	.set CYDEV_UCFG_B1_P5_U1_CFG14, 0x40011ace
 4832              	.set CYDEV_UCFG_B1_P5_U1_CFG15, 0x40011acf
 4833              	.set CYDEV_UCFG_B1_P5_U1_CFG16, 0x40011ad0
 4834              	.set CYDEV_UCFG_B1_P5_U1_CFG17, 0x40011ad1
 4835              	.set CYDEV_UCFG_B1_P5_U1_CFG18, 0x40011ad2
 4836              	.set CYDEV_UCFG_B1_P5_U1_CFG19, 0x40011ad3
 4837              	.set CYDEV_UCFG_B1_P5_U1_CFG20, 0x40011ad4
 4838              	.set CYDEV_UCFG_B1_P5_U1_CFG21, 0x40011ad5
 4839              	.set CYDEV_UCFG_B1_P5_U1_CFG22, 0x40011ad6
 4840              	.set CYDEV_UCFG_B1_P5_U1_CFG23, 0x40011ad7
 4841              	.set CYDEV_UCFG_B1_P5_U1_CFG24, 0x40011ad8
 4842              	.set CYDEV_UCFG_B1_P5_U1_CFG25, 0x40011ad9
 4843              	.set CYDEV_UCFG_B1_P5_U1_CFG26, 0x40011ada
 4844              	.set CYDEV_UCFG_B1_P5_U1_CFG27, 0x40011adb
 4845              	.set CYDEV_UCFG_B1_P5_U1_CFG28, 0x40011adc
 4846              	.set CYDEV_UCFG_B1_P5_U1_CFG29, 0x40011add
 4847              	.set CYDEV_UCFG_B1_P5_U1_CFG30, 0x40011ade
 4848              	.set CYDEV_UCFG_B1_P5_U1_CFG31, 0x40011adf
 4849              	.set CYDEV_UCFG_B1_P5_U1_DCFG0, 0x40011ae0
 4850              	.set CYDEV_UCFG_B1_P5_U1_DCFG1, 0x40011ae2
 4851              	.set CYDEV_UCFG_B1_P5_U1_DCFG2, 0x40011ae4
 4852              	.set CYDEV_UCFG_B1_P5_U1_DCFG3, 0x40011ae6
 4853              	.set CYDEV_UCFG_B1_P5_U1_DCFG4, 0x40011ae8
 4854              	.set CYDEV_UCFG_B1_P5_U1_DCFG5, 0x40011aea
 4855              	.set CYDEV_UCFG_B1_P5_U1_DCFG6, 0x40011aec
 4856              	.set CYDEV_UCFG_B1_P5_U1_DCFG7, 0x40011aee
 4857              	.set CYDEV_UCFG_B1_P5_ROUTE_BASE, 0x40011b00
 4858              	.set CYDEV_UCFG_B1_P5_ROUTE_SIZE, 0x000000ef
 4859              	.set CYDEV_UCFG_DSI0_BASE, 0x40014000
 4860              	.set CYDEV_UCFG_DSI0_SIZE, 0x000000ef
 4861              	.set CYDEV_UCFG_DSI1_BASE, 0x40014100
 4862              	.set CYDEV_UCFG_DSI1_SIZE, 0x000000ef
 4863              	.set CYDEV_UCFG_DSI2_BASE, 0x40014200
 4864              	.set CYDEV_UCFG_DSI2_SIZE, 0x000000ef
 4865              	.set CYDEV_UCFG_DSI3_BASE, 0x40014300
 4866              	.set CYDEV_UCFG_DSI3_SIZE, 0x000000ef
 4867              	.set CYDEV_UCFG_DSI4_BASE, 0x40014400
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 87


 4868              	.set CYDEV_UCFG_DSI4_SIZE, 0x000000ef
 4869              	.set CYDEV_UCFG_DSI5_BASE, 0x40014500
 4870              	.set CYDEV_UCFG_DSI5_SIZE, 0x000000ef
 4871              	.set CYDEV_UCFG_DSI6_BASE, 0x40014600
 4872              	.set CYDEV_UCFG_DSI6_SIZE, 0x000000ef
 4873              	.set CYDEV_UCFG_DSI7_BASE, 0x40014700
 4874              	.set CYDEV_UCFG_DSI7_SIZE, 0x000000ef
 4875              	.set CYDEV_UCFG_DSI8_BASE, 0x40014800
 4876              	.set CYDEV_UCFG_DSI8_SIZE, 0x000000ef
 4877              	.set CYDEV_UCFG_DSI9_BASE, 0x40014900
 4878              	.set CYDEV_UCFG_DSI9_SIZE, 0x000000ef
 4879              	.set CYDEV_UCFG_DSI12_BASE, 0x40014c00
 4880              	.set CYDEV_UCFG_DSI12_SIZE, 0x000000ef
 4881              	.set CYDEV_UCFG_DSI13_BASE, 0x40014d00
 4882              	.set CYDEV_UCFG_DSI13_SIZE, 0x000000ef
 4883              	.set CYDEV_UCFG_BCTL0_BASE, 0x40015000
 4884              	.set CYDEV_UCFG_BCTL0_SIZE, 0x00000010
 4885              	.set CYDEV_UCFG_BCTL0_MDCLK_EN, 0x40015000
 4886              	.set CYDEV_UCFG_BCTL0_MBCLK_EN, 0x40015001
 4887              	.set CYDEV_UCFG_BCTL0_WAIT_CFG, 0x40015002
 4888              	.set CYDEV_UCFG_BCTL0_BANK_CTL, 0x40015003
 4889              	.set CYDEV_UCFG_BCTL0_UDB_TEST_3, 0x40015007
 4890              	.set CYDEV_UCFG_BCTL0_DCLK_EN0, 0x40015008
 4891              	.set CYDEV_UCFG_BCTL0_BCLK_EN0, 0x40015009
 4892              	.set CYDEV_UCFG_BCTL0_DCLK_EN1, 0x4001500a
 4893              	.set CYDEV_UCFG_BCTL0_BCLK_EN1, 0x4001500b
 4894              	.set CYDEV_UCFG_BCTL0_DCLK_EN2, 0x4001500c
 4895              	.set CYDEV_UCFG_BCTL0_BCLK_EN2, 0x4001500d
 4896              	.set CYDEV_UCFG_BCTL0_DCLK_EN3, 0x4001500e
 4897              	.set CYDEV_UCFG_BCTL0_BCLK_EN3, 0x4001500f
 4898              	.set CYDEV_UCFG_BCTL1_BASE, 0x40015010
 4899              	.set CYDEV_UCFG_BCTL1_SIZE, 0x00000010
 4900              	.set CYDEV_UCFG_BCTL1_MDCLK_EN, 0x40015010
 4901              	.set CYDEV_UCFG_BCTL1_MBCLK_EN, 0x40015011
 4902              	.set CYDEV_UCFG_BCTL1_WAIT_CFG, 0x40015012
 4903              	.set CYDEV_UCFG_BCTL1_BANK_CTL, 0x40015013
 4904              	.set CYDEV_UCFG_BCTL1_UDB_TEST_3, 0x40015017
 4905              	.set CYDEV_UCFG_BCTL1_DCLK_EN0, 0x40015018
 4906              	.set CYDEV_UCFG_BCTL1_BCLK_EN0, 0x40015019
 4907              	.set CYDEV_UCFG_BCTL1_DCLK_EN1, 0x4001501a
 4908              	.set CYDEV_UCFG_BCTL1_BCLK_EN1, 0x4001501b
 4909              	.set CYDEV_UCFG_BCTL1_DCLK_EN2, 0x4001501c
 4910              	.set CYDEV_UCFG_BCTL1_BCLK_EN2, 0x4001501d
 4911              	.set CYDEV_UCFG_BCTL1_DCLK_EN3, 0x4001501e
 4912              	.set CYDEV_UCFG_BCTL1_BCLK_EN3, 0x4001501f
 4913              	.set CYDEV_IDMUX_BASE, 0x40015100
 4914              	.set CYDEV_IDMUX_SIZE, 0x00000016
 4915              	.set CYDEV_IDMUX_IRQ_CTL0, 0x40015100
 4916              	.set CYDEV_IDMUX_IRQ_CTL1, 0x40015101
 4917              	.set CYDEV_IDMUX_IRQ_CTL2, 0x40015102
 4918              	.set CYDEV_IDMUX_IRQ_CTL3, 0x40015103
 4919              	.set CYDEV_IDMUX_IRQ_CTL4, 0x40015104
 4920              	.set CYDEV_IDMUX_IRQ_CTL5, 0x40015105
 4921              	.set CYDEV_IDMUX_IRQ_CTL6, 0x40015106
 4922              	.set CYDEV_IDMUX_IRQ_CTL7, 0x40015107
 4923              	.set CYDEV_IDMUX_DRQ_CTL0, 0x40015110
 4924              	.set CYDEV_IDMUX_DRQ_CTL1, 0x40015111
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 88


 4925              	.set CYDEV_IDMUX_DRQ_CTL2, 0x40015112
 4926              	.set CYDEV_IDMUX_DRQ_CTL3, 0x40015113
 4927              	.set CYDEV_IDMUX_DRQ_CTL4, 0x40015114
 4928              	.set CYDEV_IDMUX_DRQ_CTL5, 0x40015115
 4929              	.set CYDEV_CACHERAM_BASE, 0x40030000
 4930              	.set CYDEV_CACHERAM_SIZE, 0x00000400
 4931              	.set CYDEV_CACHERAM_DATA_MBASE, 0x40030000
 4932              	.set CYDEV_CACHERAM_DATA_MSIZE, 0x00000400
 4933              	.set CYDEV_SFR_BASE, 0x40050100
 4934              	.set CYDEV_SFR_SIZE, 0x000000fb
 4935              	.set CYDEV_SFR_GPIO0, 0x40050180
 4936              	.set CYDEV_SFR_GPIRD0, 0x40050189
 4937              	.set CYDEV_SFR_GPIO0_SEL, 0x4005018a
 4938              	.set CYDEV_SFR_GPIO1, 0x40050190
 4939              	.set CYDEV_SFR_GPIRD1, 0x40050191
 4940              	.set CYDEV_SFR_GPIO2, 0x40050198
 4941              	.set CYDEV_SFR_GPIRD2, 0x40050199
 4942              	.set CYDEV_SFR_GPIO2_SEL, 0x4005019a
 4943              	.set CYDEV_SFR_GPIO1_SEL, 0x400501a2
 4944              	.set CYDEV_SFR_GPIO3, 0x400501b0
 4945              	.set CYDEV_SFR_GPIRD3, 0x400501b1
 4946              	.set CYDEV_SFR_GPIO3_SEL, 0x400501b2
 4947              	.set CYDEV_SFR_GPIO4, 0x400501c0
 4948              	.set CYDEV_SFR_GPIRD4, 0x400501c1
 4949              	.set CYDEV_SFR_GPIO4_SEL, 0x400501c2
 4950              	.set CYDEV_SFR_GPIO5, 0x400501c8
 4951              	.set CYDEV_SFR_GPIRD5, 0x400501c9
 4952              	.set CYDEV_SFR_GPIO5_SEL, 0x400501ca
 4953              	.set CYDEV_SFR_GPIO6, 0x400501d8
 4954              	.set CYDEV_SFR_GPIRD6, 0x400501d9
 4955              	.set CYDEV_SFR_GPIO6_SEL, 0x400501da
 4956              	.set CYDEV_SFR_GPIO12, 0x400501e8
 4957              	.set CYDEV_SFR_GPIRD12, 0x400501e9
 4958              	.set CYDEV_SFR_GPIO12_SEL, 0x400501f2
 4959              	.set CYDEV_SFR_GPIO15, 0x400501f8
 4960              	.set CYDEV_SFR_GPIRD15, 0x400501f9
 4961              	.set CYDEV_SFR_GPIO15_SEL, 0x400501fa
 4962              	.set CYDEV_P3BA_BASE, 0x40050300
 4963              	.set CYDEV_P3BA_SIZE, 0x0000002b
 4964              	.set CYDEV_P3BA_Y_START, 0x40050300
 4965              	.set CYDEV_P3BA_YROLL, 0x40050301
 4966              	.set CYDEV_P3BA_YCFG, 0x40050302
 4967              	.set CYDEV_P3BA_X_START1, 0x40050303
 4968              	.set CYDEV_P3BA_X_START2, 0x40050304
 4969              	.set CYDEV_P3BA_XROLL1, 0x40050305
 4970              	.set CYDEV_P3BA_XROLL2, 0x40050306
 4971              	.set CYDEV_P3BA_XINC, 0x40050307
 4972              	.set CYDEV_P3BA_XCFG, 0x40050308
 4973              	.set CYDEV_P3BA_OFFSETADDR1, 0x40050309
 4974              	.set CYDEV_P3BA_OFFSETADDR2, 0x4005030a
 4975              	.set CYDEV_P3BA_OFFSETADDR3, 0x4005030b
 4976              	.set CYDEV_P3BA_ABSADDR1, 0x4005030c
 4977              	.set CYDEV_P3BA_ABSADDR2, 0x4005030d
 4978              	.set CYDEV_P3BA_ABSADDR3, 0x4005030e
 4979              	.set CYDEV_P3BA_ABSADDR4, 0x4005030f
 4980              	.set CYDEV_P3BA_DATCFG1, 0x40050310
 4981              	.set CYDEV_P3BA_DATCFG2, 0x40050311
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 89


 4982              	.set CYDEV_P3BA_CMP_RSLT1, 0x40050314
 4983              	.set CYDEV_P3BA_CMP_RSLT2, 0x40050315
 4984              	.set CYDEV_P3BA_CMP_RSLT3, 0x40050316
 4985              	.set CYDEV_P3BA_CMP_RSLT4, 0x40050317
 4986              	.set CYDEV_P3BA_DATA_REG1, 0x40050318
 4987              	.set CYDEV_P3BA_DATA_REG2, 0x40050319
 4988              	.set CYDEV_P3BA_DATA_REG3, 0x4005031a
 4989              	.set CYDEV_P3BA_DATA_REG4, 0x4005031b
 4990              	.set CYDEV_P3BA_EXP_DATA1, 0x4005031c
 4991              	.set CYDEV_P3BA_EXP_DATA2, 0x4005031d
 4992              	.set CYDEV_P3BA_EXP_DATA3, 0x4005031e
 4993              	.set CYDEV_P3BA_EXP_DATA4, 0x4005031f
 4994              	.set CYDEV_P3BA_MSTR_HRDATA1, 0x40050320
 4995              	.set CYDEV_P3BA_MSTR_HRDATA2, 0x40050321
 4996              	.set CYDEV_P3BA_MSTR_HRDATA3, 0x40050322
 4997              	.set CYDEV_P3BA_MSTR_HRDATA4, 0x40050323
 4998              	.set CYDEV_P3BA_BIST_EN, 0x40050324
 4999              	.set CYDEV_P3BA_PHUB_MASTER_SSR, 0x40050325
 5000              	.set CYDEV_P3BA_SEQCFG1, 0x40050326
 5001              	.set CYDEV_P3BA_SEQCFG2, 0x40050327
 5002              	.set CYDEV_P3BA_Y_CURR, 0x40050328
 5003              	.set CYDEV_P3BA_X_CURR1, 0x40050329
 5004              	.set CYDEV_P3BA_X_CURR2, 0x4005032a
 5005              	.set CYDEV_PANTHER_BASE, 0x40080000
 5006              	.set CYDEV_PANTHER_SIZE, 0x00000020
 5007              	.set CYDEV_PANTHER_STCALIB_CFG, 0x40080000
 5008              	.set CYDEV_PANTHER_WAITPIPE, 0x40080004
 5009              	.set CYDEV_PANTHER_TRACE_CFG, 0x40080008
 5010              	.set CYDEV_PANTHER_DBG_CFG, 0x4008000c
 5011              	.set CYDEV_PANTHER_CM3_LCKRST_STAT, 0x40080018
 5012              	.set CYDEV_PANTHER_DEVICE_ID, 0x4008001c
 5013              	.set CYDEV_FLSECC_BASE, 0x48000000
 5014              	.set CYDEV_FLSECC_SIZE, 0x00008000
 5015              	.set CYDEV_FLSECC_DATA_MBASE, 0x48000000
 5016              	.set CYDEV_FLSECC_DATA_MSIZE, 0x00008000
 5017              	.set CYDEV_FLSHID_BASE, 0x49000000
 5018              	.set CYDEV_FLSHID_SIZE, 0x00000200
 5019              	.set CYDEV_FLSHID_RSVD_MBASE, 0x49000000
 5020              	.set CYDEV_FLSHID_RSVD_MSIZE, 0x00000080
 5021              	.set CYDEV_FLSHID_CUST_MDATA_MBASE, 0x49000080
 5022              	.set CYDEV_FLSHID_CUST_MDATA_MSIZE, 0x00000080
 5023              	.set CYDEV_FLSHID_CUST_TABLES_BASE, 0x49000100
 5024              	.set CYDEV_FLSHID_CUST_TABLES_SIZE, 0x00000040
 5025              	.set CYDEV_FLSHID_CUST_TABLES_Y_LOC, 0x49000100
 5026              	.set CYDEV_FLSHID_CUST_TABLES_X_LOC, 0x49000101
 5027              	.set CYDEV_FLSHID_CUST_TABLES_WAFER_NUM, 0x49000102
 5028              	.set CYDEV_FLSHID_CUST_TABLES_LOT_LSB, 0x49000103
 5029              	.set CYDEV_FLSHID_CUST_TABLES_LOT_MSB, 0x49000104
 5030              	.set CYDEV_FLSHID_CUST_TABLES_WRK_WK, 0x49000105
 5031              	.set CYDEV_FLSHID_CUST_TABLES_FAB_YR, 0x49000106
 5032              	.set CYDEV_FLSHID_CUST_TABLES_MINOR, 0x49000107
 5033              	.set CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ, 0x49000108
 5034              	.set CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ, 0x49000109
 5035              	.set CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ, 0x4900010a
 5036              	.set CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ, 0x4900010b
 5037              	.set CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ, 0x4900010c
 5038              	.set CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ, 0x4900010d
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 90


 5039              	.set CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ, 0x4900010e
 5040              	.set CYDEV_FLSHID_CUST_TABLES_IMO_USB, 0x4900010f
 5041              	.set CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS, 0x49000110
 5042              	.set CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS, 0x49000111
 5043              	.set CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS, 0x49000112
 5044              	.set CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS, 0x49000113
 5045              	.set CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS, 0x49000114
 5046              	.set CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS, 0x49000115
 5047              	.set CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS, 0x49000116
 5048              	.set CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS, 0x49000117
 5049              	.set CYDEV_FLSHID_CUST_TABLES_DEC_M1, 0x49000118
 5050              	.set CYDEV_FLSHID_CUST_TABLES_DEC_M2, 0x49000119
 5051              	.set CYDEV_FLSHID_CUST_TABLES_DEC_M3, 0x4900011a
 5052              	.set CYDEV_FLSHID_CUST_TABLES_DEC_M4, 0x4900011b
 5053              	.set CYDEV_FLSHID_CUST_TABLES_DEC_M5, 0x4900011c
 5054              	.set CYDEV_FLSHID_CUST_TABLES_DEC_M6, 0x4900011d
 5055              	.set CYDEV_FLSHID_CUST_TABLES_DEC_M7, 0x4900011e
 5056              	.set CYDEV_FLSHID_CUST_TABLES_DEC_M8, 0x4900011f
 5057              	.set CYDEV_FLSHID_CUST_TABLES_DAC0_M1, 0x49000120
 5058              	.set CYDEV_FLSHID_CUST_TABLES_DAC0_M2, 0x49000121
 5059              	.set CYDEV_FLSHID_CUST_TABLES_DAC0_M3, 0x49000122
 5060              	.set CYDEV_FLSHID_CUST_TABLES_DAC0_M4, 0x49000123
 5061              	.set CYDEV_FLSHID_CUST_TABLES_DAC0_M5, 0x49000124
 5062              	.set CYDEV_FLSHID_CUST_TABLES_DAC0_M6, 0x49000125
 5063              	.set CYDEV_FLSHID_CUST_TABLES_DAC0_M7, 0x49000126
 5064              	.set CYDEV_FLSHID_CUST_TABLES_DAC0_M8, 0x49000127
 5065              	.set CYDEV_FLSHID_CUST_TABLES_DAC2_M1, 0x49000128
 5066              	.set CYDEV_FLSHID_CUST_TABLES_DAC2_M2, 0x49000129
 5067              	.set CYDEV_FLSHID_CUST_TABLES_DAC2_M3, 0x4900012a
 5068              	.set CYDEV_FLSHID_CUST_TABLES_DAC2_M4, 0x4900012b
 5069              	.set CYDEV_FLSHID_CUST_TABLES_DAC2_M5, 0x4900012c
 5070              	.set CYDEV_FLSHID_CUST_TABLES_DAC2_M6, 0x4900012d
 5071              	.set CYDEV_FLSHID_CUST_TABLES_DAC2_M7, 0x4900012e
 5072              	.set CYDEV_FLSHID_CUST_TABLES_DAC2_M8, 0x4900012f
 5073              	.set CYDEV_FLSHID_CUST_TABLES_DAC1_M1, 0x49000130
 5074              	.set CYDEV_FLSHID_CUST_TABLES_DAC1_M2, 0x49000131
 5075              	.set CYDEV_FLSHID_CUST_TABLES_DAC1_M3, 0x49000132
 5076              	.set CYDEV_FLSHID_CUST_TABLES_DAC1_M4, 0x49000133
 5077              	.set CYDEV_FLSHID_CUST_TABLES_DAC1_M5, 0x49000134
 5078              	.set CYDEV_FLSHID_CUST_TABLES_DAC1_M6, 0x49000135
 5079              	.set CYDEV_FLSHID_CUST_TABLES_DAC1_M7, 0x49000136
 5080              	.set CYDEV_FLSHID_CUST_TABLES_DAC1_M8, 0x49000137
 5081              	.set CYDEV_FLSHID_CUST_TABLES_DAC3_M1, 0x49000138
 5082              	.set CYDEV_FLSHID_CUST_TABLES_DAC3_M2, 0x49000139
 5083              	.set CYDEV_FLSHID_CUST_TABLES_DAC3_M3, 0x4900013a
 5084              	.set CYDEV_FLSHID_CUST_TABLES_DAC3_M4, 0x4900013b
 5085              	.set CYDEV_FLSHID_CUST_TABLES_DAC3_M5, 0x4900013c
 5086              	.set CYDEV_FLSHID_CUST_TABLES_DAC3_M6, 0x4900013d
 5087              	.set CYDEV_FLSHID_CUST_TABLES_DAC3_M7, 0x4900013e
 5088              	.set CYDEV_FLSHID_CUST_TABLES_DAC3_M8, 0x4900013f
 5089              	.set CYDEV_FLSHID_MFG_CFG_BASE, 0x49000180
 5090              	.set CYDEV_FLSHID_MFG_CFG_SIZE, 0x00000080
 5091              	.set CYDEV_FLSHID_MFG_CFG_IMO_TR1, 0x49000188
 5092              	.set CYDEV_FLSHID_MFG_CFG_CMP0_TR0, 0x490001ac
 5093              	.set CYDEV_FLSHID_MFG_CFG_CMP1_TR0, 0x490001ae
 5094              	.set CYDEV_FLSHID_MFG_CFG_CMP2_TR0, 0x490001b0
 5095              	.set CYDEV_FLSHID_MFG_CFG_CMP3_TR0, 0x490001b2
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 91


 5096              	.set CYDEV_FLSHID_MFG_CFG_CMP0_TR1, 0x490001b4
 5097              	.set CYDEV_FLSHID_MFG_CFG_CMP1_TR1, 0x490001b6
 5098              	.set CYDEV_FLSHID_MFG_CFG_CMP2_TR1, 0x490001b8
 5099              	.set CYDEV_FLSHID_MFG_CFG_CMP3_TR1, 0x490001ba
 5100              	.set CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM, 0x490001ce
 5101              	.set CYDEV_EXTMEM_BASE, 0x60000000
 5102              	.set CYDEV_EXTMEM_SIZE, 0x00800000
 5103              	.set CYDEV_EXTMEM_DATA_MBASE, 0x60000000
 5104              	.set CYDEV_EXTMEM_DATA_MSIZE, 0x00800000
 5105              	.set CYDEV_ITM_BASE, 0xe0000000
 5106              	.set CYDEV_ITM_SIZE, 0x00001000
 5107              	.set CYDEV_ITM_TRACE_EN, 0xe0000e00
 5108              	.set CYDEV_ITM_TRACE_PRIVILEGE, 0xe0000e40
 5109              	.set CYDEV_ITM_TRACE_CTRL, 0xe0000e80
 5110              	.set CYDEV_ITM_LOCK_ACCESS, 0xe0000fb0
 5111              	.set CYDEV_ITM_LOCK_STATUS, 0xe0000fb4
 5112              	.set CYDEV_ITM_PID4, 0xe0000fd0
 5113              	.set CYDEV_ITM_PID5, 0xe0000fd4
 5114              	.set CYDEV_ITM_PID6, 0xe0000fd8
 5115              	.set CYDEV_ITM_PID7, 0xe0000fdc
 5116              	.set CYDEV_ITM_PID0, 0xe0000fe0
 5117              	.set CYDEV_ITM_PID1, 0xe0000fe4
 5118              	.set CYDEV_ITM_PID2, 0xe0000fe8
 5119              	.set CYDEV_ITM_PID3, 0xe0000fec
 5120              	.set CYDEV_ITM_CID0, 0xe0000ff0
 5121              	.set CYDEV_ITM_CID1, 0xe0000ff4
 5122              	.set CYDEV_ITM_CID2, 0xe0000ff8
 5123              	.set CYDEV_ITM_CID3, 0xe0000ffc
 5124              	.set CYDEV_DWT_BASE, 0xe0001000
 5125              	.set CYDEV_DWT_SIZE, 0x0000005c
 5126              	.set CYDEV_DWT_CTRL, 0xe0001000
 5127              	.set CYDEV_DWT_CYCLE_COUNT, 0xe0001004
 5128              	.set CYDEV_DWT_CPI_COUNT, 0xe0001008
 5129              	.set CYDEV_DWT_EXC_OVHD_COUNT, 0xe000100c
 5130              	.set CYDEV_DWT_SLEEP_COUNT, 0xe0001010
 5131              	.set CYDEV_DWT_LSU_COUNT, 0xe0001014
 5132              	.set CYDEV_DWT_FOLD_COUNT, 0xe0001018
 5133              	.set CYDEV_DWT_PC_SAMPLE, 0xe000101c
 5134              	.set CYDEV_DWT_COMP_0, 0xe0001020
 5135              	.set CYDEV_DWT_MASK_0, 0xe0001024
 5136              	.set CYDEV_DWT_FUNCTION_0, 0xe0001028
 5137              	.set CYDEV_DWT_COMP_1, 0xe0001030
 5138              	.set CYDEV_DWT_MASK_1, 0xe0001034
 5139              	.set CYDEV_DWT_FUNCTION_1, 0xe0001038
 5140              	.set CYDEV_DWT_COMP_2, 0xe0001040
 5141              	.set CYDEV_DWT_MASK_2, 0xe0001044
 5142              	.set CYDEV_DWT_FUNCTION_2, 0xe0001048
 5143              	.set CYDEV_DWT_COMP_3, 0xe0001050
 5144              	.set CYDEV_DWT_MASK_3, 0xe0001054
 5145              	.set CYDEV_DWT_FUNCTION_3, 0xe0001058
 5146              	.set CYDEV_FPB_BASE, 0xe0002000
 5147              	.set CYDEV_FPB_SIZE, 0x00001000
 5148              	.set CYDEV_FPB_CTRL, 0xe0002000
 5149              	.set CYDEV_FPB_REMAP, 0xe0002004
 5150              	.set CYDEV_FPB_FP_COMP_0, 0xe0002008
 5151              	.set CYDEV_FPB_FP_COMP_1, 0xe000200c
 5152              	.set CYDEV_FPB_FP_COMP_2, 0xe0002010
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 92


 5153              	.set CYDEV_FPB_FP_COMP_3, 0xe0002014
 5154              	.set CYDEV_FPB_FP_COMP_4, 0xe0002018
 5155              	.set CYDEV_FPB_FP_COMP_5, 0xe000201c
 5156              	.set CYDEV_FPB_FP_COMP_6, 0xe0002020
 5157              	.set CYDEV_FPB_FP_COMP_7, 0xe0002024
 5158              	.set CYDEV_FPB_PID4, 0xe0002fd0
 5159              	.set CYDEV_FPB_PID5, 0xe0002fd4
 5160              	.set CYDEV_FPB_PID6, 0xe0002fd8
 5161              	.set CYDEV_FPB_PID7, 0xe0002fdc
 5162              	.set CYDEV_FPB_PID0, 0xe0002fe0
 5163              	.set CYDEV_FPB_PID1, 0xe0002fe4
 5164              	.set CYDEV_FPB_PID2, 0xe0002fe8
 5165              	.set CYDEV_FPB_PID3, 0xe0002fec
 5166              	.set CYDEV_FPB_CID0, 0xe0002ff0
 5167              	.set CYDEV_FPB_CID1, 0xe0002ff4
 5168              	.set CYDEV_FPB_CID2, 0xe0002ff8
 5169              	.set CYDEV_FPB_CID3, 0xe0002ffc
 5170              	.set CYDEV_NVIC_BASE, 0xe000e000
 5171              	.set CYDEV_NVIC_SIZE, 0x00000d3c
 5172              	.set CYDEV_NVIC_INT_CTL_TYPE, 0xe000e004
 5173              	.set CYDEV_NVIC_SYSTICK_CTL, 0xe000e010
 5174              	.set CYDEV_NVIC_SYSTICK_RELOAD, 0xe000e014
 5175              	.set CYDEV_NVIC_SYSTICK_CURRENT, 0xe000e018
 5176              	.set CYDEV_NVIC_SYSTICK_CAL, 0xe000e01c
 5177              	.set CYDEV_NVIC_SETENA0, 0xe000e100
 5178              	.set CYDEV_NVIC_CLRENA0, 0xe000e180
 5179              	.set CYDEV_NVIC_SETPEND0, 0xe000e200
 5180              	.set CYDEV_NVIC_CLRPEND0, 0xe000e280
 5181              	.set CYDEV_NVIC_ACTIVE0, 0xe000e300
 5182              	.set CYDEV_NVIC_PRI_0, 0xe000e400
 5183              	.set CYDEV_NVIC_PRI_1, 0xe000e401
 5184              	.set CYDEV_NVIC_PRI_2, 0xe000e402
 5185              	.set CYDEV_NVIC_PRI_3, 0xe000e403
 5186              	.set CYDEV_NVIC_PRI_4, 0xe000e404
 5187              	.set CYDEV_NVIC_PRI_5, 0xe000e405
 5188              	.set CYDEV_NVIC_PRI_6, 0xe000e406
 5189              	.set CYDEV_NVIC_PRI_7, 0xe000e407
 5190              	.set CYDEV_NVIC_PRI_8, 0xe000e408
 5191              	.set CYDEV_NVIC_PRI_9, 0xe000e409
 5192              	.set CYDEV_NVIC_PRI_10, 0xe000e40a
 5193              	.set CYDEV_NVIC_PRI_11, 0xe000e40b
 5194              	.set CYDEV_NVIC_PRI_12, 0xe000e40c
 5195              	.set CYDEV_NVIC_PRI_13, 0xe000e40d
 5196              	.set CYDEV_NVIC_PRI_14, 0xe000e40e
 5197              	.set CYDEV_NVIC_PRI_15, 0xe000e40f
 5198              	.set CYDEV_NVIC_PRI_16, 0xe000e410
 5199              	.set CYDEV_NVIC_PRI_17, 0xe000e411
 5200              	.set CYDEV_NVIC_PRI_18, 0xe000e412
 5201              	.set CYDEV_NVIC_PRI_19, 0xe000e413
 5202              	.set CYDEV_NVIC_PRI_20, 0xe000e414
 5203              	.set CYDEV_NVIC_PRI_21, 0xe000e415
 5204              	.set CYDEV_NVIC_PRI_22, 0xe000e416
 5205              	.set CYDEV_NVIC_PRI_23, 0xe000e417
 5206              	.set CYDEV_NVIC_PRI_24, 0xe000e418
 5207              	.set CYDEV_NVIC_PRI_25, 0xe000e419
 5208              	.set CYDEV_NVIC_PRI_26, 0xe000e41a
 5209              	.set CYDEV_NVIC_PRI_27, 0xe000e41b
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 93


 5210              	.set CYDEV_NVIC_PRI_28, 0xe000e41c
 5211              	.set CYDEV_NVIC_PRI_29, 0xe000e41d
 5212              	.set CYDEV_NVIC_PRI_30, 0xe000e41e
 5213              	.set CYDEV_NVIC_PRI_31, 0xe000e41f
 5214              	.set CYDEV_NVIC_CPUID_BASE, 0xe000ed00
 5215              	.set CYDEV_NVIC_INTR_CTRL_STATE, 0xe000ed04
 5216              	.set CYDEV_NVIC_VECT_OFFSET, 0xe000ed08
 5217              	.set CYDEV_NVIC_APPLN_INTR, 0xe000ed0c
 5218              	.set CYDEV_NVIC_SYSTEM_CONTROL, 0xe000ed10
 5219              	.set CYDEV_NVIC_CFG_CONTROL, 0xe000ed14
 5220              	.set CYDEV_NVIC_SYS_PRIO_HANDLER_4_7, 0xe000ed18
 5221              	.set CYDEV_NVIC_SYS_PRIO_HANDLER_8_11, 0xe000ed1c
 5222              	.set CYDEV_NVIC_SYS_PRIO_HANDLER_12_15, 0xe000ed20
 5223              	.set CYDEV_NVIC_SYS_HANDLER_CSR, 0xe000ed24
 5224              	.set CYDEV_NVIC_MEMMAN_FAULT_STATUS, 0xe000ed28
 5225              	.set CYDEV_NVIC_BUS_FAULT_STATUS, 0xe000ed29
 5226              	.set CYDEV_NVIC_USAGE_FAULT_STATUS, 0xe000ed2a
 5227              	.set CYDEV_NVIC_HARD_FAULT_STATUS, 0xe000ed2c
 5228              	.set CYDEV_NVIC_DEBUG_FAULT_STATUS, 0xe000ed30
 5229              	.set CYDEV_NVIC_MEMMAN_FAULT_ADD, 0xe000ed34
 5230              	.set CYDEV_NVIC_BUS_FAULT_ADD, 0xe000ed38
 5231              	.set CYDEV_CORE_DBG_BASE, 0xe000edf0
 5232              	.set CYDEV_CORE_DBG_SIZE, 0x00000010
 5233              	.set CYDEV_CORE_DBG_DBG_HLT_CS, 0xe000edf0
 5234              	.set CYDEV_CORE_DBG_DBG_REG_SEL, 0xe000edf4
 5235              	.set CYDEV_CORE_DBG_DBG_REG_DATA, 0xe000edf8
 5236              	.set CYDEV_CORE_DBG_EXC_MON_CTL, 0xe000edfc
 5237              	.set CYDEV_TPIU_BASE, 0xe0040000
 5238              	.set CYDEV_TPIU_SIZE, 0x00001000
 5239              	.set CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ, 0xe0040000
 5240              	.set CYDEV_TPIU_CURRENT_SYNC_PRT_SZ, 0xe0040004
 5241              	.set CYDEV_TPIU_ASYNC_CLK_PRESCALER, 0xe0040010
 5242              	.set CYDEV_TPIU_PROTOCOL, 0xe00400f0
 5243              	.set CYDEV_TPIU_FORM_FLUSH_STAT, 0xe0040300
 5244              	.set CYDEV_TPIU_FORM_FLUSH_CTRL, 0xe0040304
 5245              	.set CYDEV_TPIU_TRIGGER, 0xe0040ee8
 5246              	.set CYDEV_TPIU_ITETMDATA, 0xe0040eec
 5247              	.set CYDEV_TPIU_ITATBCTR2, 0xe0040ef0
 5248              	.set CYDEV_TPIU_ITATBCTR0, 0xe0040ef8
 5249              	.set CYDEV_TPIU_ITITMDATA, 0xe0040efc
 5250              	.set CYDEV_TPIU_ITCTRL, 0xe0040f00
 5251              	.set CYDEV_TPIU_DEVID, 0xe0040fc8
 5252              	.set CYDEV_TPIU_DEVTYPE, 0xe0040fcc
 5253              	.set CYDEV_TPIU_PID4, 0xe0040fd0
 5254              	.set CYDEV_TPIU_PID5, 0xe0040fd4
 5255              	.set CYDEV_TPIU_PID6, 0xe0040fd8
 5256              	.set CYDEV_TPIU_PID7, 0xe0040fdc
 5257              	.set CYDEV_TPIU_PID0, 0xe0040fe0
 5258              	.set CYDEV_TPIU_PID1, 0xe0040fe4
 5259              	.set CYDEV_TPIU_PID2, 0xe0040fe8
 5260              	.set CYDEV_TPIU_PID3, 0xe0040fec
 5261              	.set CYDEV_TPIU_CID0, 0xe0040ff0
 5262              	.set CYDEV_TPIU_CID1, 0xe0040ff4
 5263              	.set CYDEV_TPIU_CID2, 0xe0040ff8
 5264              	.set CYDEV_TPIU_CID3, 0xe0040ffc
 5265              	.set CYDEV_ETM_BASE, 0xe0041000
 5266              	.set CYDEV_ETM_SIZE, 0x00001000
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 94


 5267              	.set CYDEV_ETM_CTL, 0xe0041000
 5268              	.set CYDEV_ETM_CFG_CODE, 0xe0041004
 5269              	.set CYDEV_ETM_TRIG_EVENT, 0xe0041008
 5270              	.set CYDEV_ETM_STATUS, 0xe0041010
 5271              	.set CYDEV_ETM_SYS_CFG, 0xe0041014
 5272              	.set CYDEV_ETM_TRACE_ENB_EVENT, 0xe0041020
 5273              	.set CYDEV_ETM_TRACE_EN_CTRL1, 0xe0041024
 5274              	.set CYDEV_ETM_FIFOFULL_LEVEL, 0xe004102c
 5275              	.set CYDEV_ETM_SYNC_FREQ, 0xe00411e0
 5276              	.set CYDEV_ETM_ETM_ID, 0xe00411e4
 5277              	.set CYDEV_ETM_CFG_CODE_EXT, 0xe00411e8
 5278              	.set CYDEV_ETM_TR_SS_EMBICE_CTRL, 0xe00411f0
 5279              	.set CYDEV_ETM_CS_TRACE_ID, 0xe0041200
 5280              	.set CYDEV_ETM_OS_LOCK_ACCESS, 0xe0041300
 5281              	.set CYDEV_ETM_OS_LOCK_STATUS, 0xe0041304
 5282              	.set CYDEV_ETM_PDSR, 0xe0041314
 5283              	.set CYDEV_ETM_ITMISCIN, 0xe0041ee0
 5284              	.set CYDEV_ETM_ITTRIGOUT, 0xe0041ee8
 5285              	.set CYDEV_ETM_ITATBCTR2, 0xe0041ef0
 5286              	.set CYDEV_ETM_ITATBCTR0, 0xe0041ef8
 5287              	.set CYDEV_ETM_INT_MODE_CTRL, 0xe0041f00
 5288              	.set CYDEV_ETM_CLM_TAG_SET, 0xe0041fa0
 5289              	.set CYDEV_ETM_CLM_TAG_CLR, 0xe0041fa4
 5290              	.set CYDEV_ETM_LOCK_ACCESS, 0xe0041fb0
 5291              	.set CYDEV_ETM_LOCK_STATUS, 0xe0041fb4
 5292              	.set CYDEV_ETM_AUTH_STATUS, 0xe0041fb8
 5293              	.set CYDEV_ETM_DEV_TYPE, 0xe0041fcc
 5294              	.set CYDEV_ETM_PID4, 0xe0041fd0
 5295              	.set CYDEV_ETM_PID5, 0xe0041fd4
 5296              	.set CYDEV_ETM_PID6, 0xe0041fd8
 5297              	.set CYDEV_ETM_PID7, 0xe0041fdc
 5298              	.set CYDEV_ETM_PID0, 0xe0041fe0
 5299              	.set CYDEV_ETM_PID1, 0xe0041fe4
 5300              	.set CYDEV_ETM_PID2, 0xe0041fe8
 5301              	.set CYDEV_ETM_PID3, 0xe0041fec
 5302              	.set CYDEV_ETM_CID0, 0xe0041ff0
 5303              	.set CYDEV_ETM_CID1, 0xe0041ff4
 5304              	.set CYDEV_ETM_CID2, 0xe0041ff8
 5305              	.set CYDEV_ETM_CID3, 0xe0041ffc
 5306              	.set CYDEV_ROM_TABLE_BASE, 0xe00ff000
 5307              	.set CYDEV_ROM_TABLE_SIZE, 0x00001000
 5308              	.set CYDEV_ROM_TABLE_NVIC, 0xe00ff000
 5309              	.set CYDEV_ROM_TABLE_DWT, 0xe00ff004
 5310              	.set CYDEV_ROM_TABLE_FPB, 0xe00ff008
 5311              	.set CYDEV_ROM_TABLE_ITM, 0xe00ff00c
 5312              	.set CYDEV_ROM_TABLE_TPIU, 0xe00ff010
 5313              	.set CYDEV_ROM_TABLE_ETM, 0xe00ff014
 5314              	.set CYDEV_ROM_TABLE_END, 0xe00ff018
 5315              	.set CYDEV_ROM_TABLE_MEMTYPE, 0xe00fffcc
 5316              	.set CYDEV_ROM_TABLE_PID4, 0xe00fffd0
 5317              	.set CYDEV_ROM_TABLE_PID5, 0xe00fffd4
 5318              	.set CYDEV_ROM_TABLE_PID6, 0xe00fffd8
 5319              	.set CYDEV_ROM_TABLE_PID7, 0xe00fffdc
 5320              	.set CYDEV_ROM_TABLE_PID0, 0xe00fffe0
 5321              	.set CYDEV_ROM_TABLE_PID1, 0xe00fffe4
 5322              	.set CYDEV_ROM_TABLE_PID2, 0xe00fffe8
 5323              	.set CYDEV_ROM_TABLE_PID3, 0xe00fffec
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 95


 5324              	.set CYDEV_ROM_TABLE_CID0, 0xe00ffff0
 5325              	.set CYDEV_ROM_TABLE_CID1, 0xe00ffff4
 5326              	.set CYDEV_ROM_TABLE_CID2, 0xe00ffff8
 5327              	.set CYDEV_ROM_TABLE_CID3, 0xe00ffffc
 5328              	.set CYDEV_FLS_SIZE, CYDEV_FLASH_SIZE
 5329              	.set CYDEV_ECC_BASE, CYDEV_FLSECC_BASE
 5330              	.set CYDEV_FLS_SECTOR_SIZE, 0x00010000
 5331              	.set CYDEV_FLS_ROW_SIZE, 0x00000100
 5332              	.set CYDEV_ECC_SECTOR_SIZE, 0x00002000
 5333              	.set CYDEV_ECC_ROW_SIZE, 0x00000020
 5334              	.set CYDEV_EEPROM_SECTOR_SIZE, 0x00000400
 5335              	.set CYDEV_EEPROM_ROW_SIZE, 0x00000010
 5336              	.set CYDEV_PERIPH_BASE, CYDEV_CLKDIST_BASE
 5337              	.set CYCLK_LD_DISABLE, 0x00000004
 5338              	.set CYCLK_LD_SYNC_EN, 0x00000002
 5339              	.set CYCLK_LD_LOAD, 0x00000001
 5340              	.set CYCLK_PIPE, 0x00000080
 5341              	.set CYCLK_SSS, 0x00000040
 5342              	.set CYCLK_EARLY, 0x00000020
 5343              	.set CYCLK_DUTY, 0x00000010
 5344              	.set CYCLK_SYNC, 0x00000008
 5345              	.set CYCLK_SRC_SEL_CLK_SYNC_D, 0
 5346              	.set CYCLK_SRC_SEL_SYNC_DIG, 0
 5347              	.set CYCLK_SRC_SEL_IMO, 1
 5348              	.set CYCLK_SRC_SEL_XTAL_MHZ, 2
 5349              	.set CYCLK_SRC_SEL_XTALM, 2
 5350              	.set CYCLK_SRC_SEL_ILO, 3
 5351              	.set CYCLK_SRC_SEL_PLL, 4
 5352              	.set CYCLK_SRC_SEL_XTAL_KHZ, 5
 5353              	.set CYCLK_SRC_SEL_XTALK, 5
 5354              	.set CYCLK_SRC_SEL_DSI_G, 6
 5355              	.set CYCLK_SRC_SEL_DSI_D, 7
 5356              	.set CYCLK_SRC_SEL_CLK_SYNC_A, 0
 5357              	.set CYCLK_SRC_SEL_DSI_A, 7
  20              	.include "cydevicegnu_trm.inc"
   1              	/*******************************************************************************
   2              	* File Name: cydevicegnu_trm.inc
   3              	* 
   4              	* PSoC Creator  4.3
   5              	*
   6              	* Description:
   7              	* This file provides all of the address values for the entire PSoC device.
   8              	* This file is automatically generated by PSoC Creator.
   9              	*
  10              	********************************************************************************
  11              	* Copyright (c) 2007-2019 Cypress Semiconductor.  All rights reserved.
  12              	* You may use this file only in accordance with the license, terms, conditions, 
  13              	* disclaimers, and limitations in the end user license agreement accompanying 
  14              	* the software package with which this file was provided.
  15              	********************************************************************************/
  16              	
  17              	.set CYDEV_FLASH_BASE, 0x00000000
  18              	.set CYDEV_FLASH_SIZE, 0x00040000
  19              	.set CYREG_FLASH_DATA_MBASE, 0x00000000
  20              	.set CYREG_FLASH_DATA_MSIZE, 0x00040000
  21              	.set CYDEV_SRAM_BASE, 0x1fff8000
  22              	.set CYDEV_SRAM_SIZE, 0x00010000
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 96


  23              	.set CYREG_SRAM_CODE64K_MBASE, 0x1fff8000
  24              	.set CYREG_SRAM_CODE64K_MSIZE, 0x00004000
  25              	.set CYREG_SRAM_CODE32K_MBASE, 0x1fffc000
  26              	.set CYREG_SRAM_CODE32K_MSIZE, 0x00002000
  27              	.set CYREG_SRAM_CODE16K_MBASE, 0x1fffe000
  28              	.set CYREG_SRAM_CODE16K_MSIZE, 0x00001000
  29              	.set CYREG_SRAM_CODE_MBASE, 0x1fff8000
  30              	.set CYREG_SRAM_CODE_MSIZE, 0x00008000
  31              	.set CYREG_SRAM_DATA_MBASE, 0x20000000
  32              	.set CYREG_SRAM_DATA_MSIZE, 0x00008000
  33              	.set CYREG_SRAM_DATA16K_MBASE, 0x20001000
  34              	.set CYREG_SRAM_DATA16K_MSIZE, 0x00001000
  35              	.set CYREG_SRAM_DATA32K_MBASE, 0x20002000
  36              	.set CYREG_SRAM_DATA32K_MSIZE, 0x00002000
  37              	.set CYREG_SRAM_DATA64K_MBASE, 0x20004000
  38              	.set CYREG_SRAM_DATA64K_MSIZE, 0x00004000
  39              	.set CYDEV_DMA_BASE, 0x20008000
  40              	.set CYDEV_DMA_SIZE, 0x00008000
  41              	.set CYREG_DMA_SRAM64K_MBASE, 0x20008000
  42              	.set CYREG_DMA_SRAM64K_MSIZE, 0x00004000
  43              	.set CYREG_DMA_SRAM32K_MBASE, 0x2000c000
  44              	.set CYREG_DMA_SRAM32K_MSIZE, 0x00002000
  45              	.set CYREG_DMA_SRAM16K_MBASE, 0x2000e000
  46              	.set CYREG_DMA_SRAM16K_MSIZE, 0x00001000
  47              	.set CYREG_DMA_SRAM_MBASE, 0x2000f000
  48              	.set CYREG_DMA_SRAM_MSIZE, 0x00001000
  49              	.set CYDEV_CLKDIST_BASE, 0x40004000
  50              	.set CYDEV_CLKDIST_SIZE, 0x00000110
  51              	.set CYREG_CLKDIST_CR, 0x40004000
  52              	.set CYREG_CLKDIST_LD, 0x40004001
  53              	.set CYREG_CLKDIST_WRK0, 0x40004002
  54              	.set CYREG_CLKDIST_WRK1, 0x40004003
  55              	.set CYREG_CLKDIST_MSTR0, 0x40004004
  56              	.set CYREG_CLKDIST_MSTR1, 0x40004005
  57              	.set CYREG_CLKDIST_BCFG0, 0x40004006
  58              	.set CYREG_CLKDIST_BCFG1, 0x40004007
  59              	.set CYREG_CLKDIST_BCFG2, 0x40004008
  60              	.set CYREG_CLKDIST_UCFG, 0x40004009
  61              	.set CYREG_CLKDIST_DLY0, 0x4000400a
  62              	.set CYREG_CLKDIST_DLY1, 0x4000400b
  63              	.set CYREG_CLKDIST_DMASK, 0x40004010
  64              	.set CYREG_CLKDIST_AMASK, 0x40004014
  65              	.set CYDEV_CLKDIST_DCFG0_BASE, 0x40004080
  66              	.set CYDEV_CLKDIST_DCFG0_SIZE, 0x00000003
  67              	.set CYREG_CLKDIST_DCFG0_CFG0, 0x40004080
  68              	.set CYREG_CLKDIST_DCFG0_CFG1, 0x40004081
  69              	.set CYREG_CLKDIST_DCFG0_CFG2, 0x40004082
  70              	.set CYDEV_CLKDIST_DCFG1_BASE, 0x40004084
  71              	.set CYDEV_CLKDIST_DCFG1_SIZE, 0x00000003
  72              	.set CYREG_CLKDIST_DCFG1_CFG0, 0x40004084
  73              	.set CYREG_CLKDIST_DCFG1_CFG1, 0x40004085
  74              	.set CYREG_CLKDIST_DCFG1_CFG2, 0x40004086
  75              	.set CYDEV_CLKDIST_DCFG2_BASE, 0x40004088
  76              	.set CYDEV_CLKDIST_DCFG2_SIZE, 0x00000003
  77              	.set CYREG_CLKDIST_DCFG2_CFG0, 0x40004088
  78              	.set CYREG_CLKDIST_DCFG2_CFG1, 0x40004089
  79              	.set CYREG_CLKDIST_DCFG2_CFG2, 0x4000408a
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 97


  80              	.set CYDEV_CLKDIST_DCFG3_BASE, 0x4000408c
  81              	.set CYDEV_CLKDIST_DCFG3_SIZE, 0x00000003
  82              	.set CYREG_CLKDIST_DCFG3_CFG0, 0x4000408c
  83              	.set CYREG_CLKDIST_DCFG3_CFG1, 0x4000408d
  84              	.set CYREG_CLKDIST_DCFG3_CFG2, 0x4000408e
  85              	.set CYDEV_CLKDIST_DCFG4_BASE, 0x40004090
  86              	.set CYDEV_CLKDIST_DCFG4_SIZE, 0x00000003
  87              	.set CYREG_CLKDIST_DCFG4_CFG0, 0x40004090
  88              	.set CYREG_CLKDIST_DCFG4_CFG1, 0x40004091
  89              	.set CYREG_CLKDIST_DCFG4_CFG2, 0x40004092
  90              	.set CYDEV_CLKDIST_DCFG5_BASE, 0x40004094
  91              	.set CYDEV_CLKDIST_DCFG5_SIZE, 0x00000003
  92              	.set CYREG_CLKDIST_DCFG5_CFG0, 0x40004094
  93              	.set CYREG_CLKDIST_DCFG5_CFG1, 0x40004095
  94              	.set CYREG_CLKDIST_DCFG5_CFG2, 0x40004096
  95              	.set CYDEV_CLKDIST_DCFG6_BASE, 0x40004098
  96              	.set CYDEV_CLKDIST_DCFG6_SIZE, 0x00000003
  97              	.set CYREG_CLKDIST_DCFG6_CFG0, 0x40004098
  98              	.set CYREG_CLKDIST_DCFG6_CFG1, 0x40004099
  99              	.set CYREG_CLKDIST_DCFG6_CFG2, 0x4000409a
 100              	.set CYDEV_CLKDIST_DCFG7_BASE, 0x4000409c
 101              	.set CYDEV_CLKDIST_DCFG7_SIZE, 0x00000003
 102              	.set CYREG_CLKDIST_DCFG7_CFG0, 0x4000409c
 103              	.set CYREG_CLKDIST_DCFG7_CFG1, 0x4000409d
 104              	.set CYREG_CLKDIST_DCFG7_CFG2, 0x4000409e
 105              	.set CYDEV_CLKDIST_ACFG0_BASE, 0x40004100
 106              	.set CYDEV_CLKDIST_ACFG0_SIZE, 0x00000004
 107              	.set CYREG_CLKDIST_ACFG0_CFG0, 0x40004100
 108              	.set CYREG_CLKDIST_ACFG0_CFG1, 0x40004101
 109              	.set CYREG_CLKDIST_ACFG0_CFG2, 0x40004102
 110              	.set CYREG_CLKDIST_ACFG0_CFG3, 0x40004103
 111              	.set CYDEV_CLKDIST_ACFG1_BASE, 0x40004104
 112              	.set CYDEV_CLKDIST_ACFG1_SIZE, 0x00000004
 113              	.set CYREG_CLKDIST_ACFG1_CFG0, 0x40004104
 114              	.set CYREG_CLKDIST_ACFG1_CFG1, 0x40004105
 115              	.set CYREG_CLKDIST_ACFG1_CFG2, 0x40004106
 116              	.set CYREG_CLKDIST_ACFG1_CFG3, 0x40004107
 117              	.set CYDEV_CLKDIST_ACFG2_BASE, 0x40004108
 118              	.set CYDEV_CLKDIST_ACFG2_SIZE, 0x00000004
 119              	.set CYREG_CLKDIST_ACFG2_CFG0, 0x40004108
 120              	.set CYREG_CLKDIST_ACFG2_CFG1, 0x40004109
 121              	.set CYREG_CLKDIST_ACFG2_CFG2, 0x4000410a
 122              	.set CYREG_CLKDIST_ACFG2_CFG3, 0x4000410b
 123              	.set CYDEV_CLKDIST_ACFG3_BASE, 0x4000410c
 124              	.set CYDEV_CLKDIST_ACFG3_SIZE, 0x00000004
 125              	.set CYREG_CLKDIST_ACFG3_CFG0, 0x4000410c
 126              	.set CYREG_CLKDIST_ACFG3_CFG1, 0x4000410d
 127              	.set CYREG_CLKDIST_ACFG3_CFG2, 0x4000410e
 128              	.set CYREG_CLKDIST_ACFG3_CFG3, 0x4000410f
 129              	.set CYDEV_FASTCLK_BASE, 0x40004200
 130              	.set CYDEV_FASTCLK_SIZE, 0x00000026
 131              	.set CYDEV_FASTCLK_IMO_BASE, 0x40004200
 132              	.set CYDEV_FASTCLK_IMO_SIZE, 0x00000001
 133              	.set CYREG_FASTCLK_IMO_CR, 0x40004200
 134              	.set CYDEV_FASTCLK_XMHZ_BASE, 0x40004210
 135              	.set CYDEV_FASTCLK_XMHZ_SIZE, 0x00000004
 136              	.set CYREG_FASTCLK_XMHZ_CSR, 0x40004210
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 98


 137              	.set CYREG_FASTCLK_XMHZ_CFG0, 0x40004212
 138              	.set CYREG_FASTCLK_XMHZ_CFG1, 0x40004213
 139              	.set CYDEV_FASTCLK_PLL_BASE, 0x40004220
 140              	.set CYDEV_FASTCLK_PLL_SIZE, 0x00000006
 141              	.set CYREG_FASTCLK_PLL_CFG0, 0x40004220
 142              	.set CYREG_FASTCLK_PLL_CFG1, 0x40004221
 143              	.set CYREG_FASTCLK_PLL_P, 0x40004222
 144              	.set CYREG_FASTCLK_PLL_Q, 0x40004223
 145              	.set CYREG_FASTCLK_PLL_SR, 0x40004225
 146              	.set CYDEV_SLOWCLK_BASE, 0x40004300
 147              	.set CYDEV_SLOWCLK_SIZE, 0x0000000b
 148              	.set CYDEV_SLOWCLK_ILO_BASE, 0x40004300
 149              	.set CYDEV_SLOWCLK_ILO_SIZE, 0x00000002
 150              	.set CYREG_SLOWCLK_ILO_CR0, 0x40004300
 151              	.set CYREG_SLOWCLK_ILO_CR1, 0x40004301
 152              	.set CYDEV_SLOWCLK_X32_BASE, 0x40004308
 153              	.set CYDEV_SLOWCLK_X32_SIZE, 0x00000003
 154              	.set CYREG_SLOWCLK_X32_CR, 0x40004308
 155              	.set CYREG_SLOWCLK_X32_CFG, 0x40004309
 156              	.set CYREG_SLOWCLK_X32_TST, 0x4000430a
 157              	.set CYDEV_BOOST_BASE, 0x40004320
 158              	.set CYDEV_BOOST_SIZE, 0x00000007
 159              	.set CYREG_BOOST_CR0, 0x40004320
 160              	.set CYREG_BOOST_CR1, 0x40004321
 161              	.set CYREG_BOOST_CR2, 0x40004322
 162              	.set CYREG_BOOST_CR3, 0x40004323
 163              	.set CYREG_BOOST_SR, 0x40004324
 164              	.set CYREG_BOOST_CR4, 0x40004325
 165              	.set CYREG_BOOST_SR2, 0x40004326
 166              	.set CYDEV_PWRSYS_BASE, 0x40004330
 167              	.set CYDEV_PWRSYS_SIZE, 0x00000002
 168              	.set CYREG_PWRSYS_CR0, 0x40004330
 169              	.set CYREG_PWRSYS_CR1, 0x40004331
 170              	.set CYDEV_PM_BASE, 0x40004380
 171              	.set CYDEV_PM_SIZE, 0x00000057
 172              	.set CYREG_PM_TW_CFG0, 0x40004380
 173              	.set CYREG_PM_TW_CFG1, 0x40004381
 174              	.set CYREG_PM_TW_CFG2, 0x40004382
 175              	.set CYREG_PM_WDT_CFG, 0x40004383
 176              	.set CYREG_PM_WDT_CR, 0x40004384
 177              	.set CYREG_PM_INT_SR, 0x40004390
 178              	.set CYREG_PM_MODE_CFG0, 0x40004391
 179              	.set CYREG_PM_MODE_CFG1, 0x40004392
 180              	.set CYREG_PM_MODE_CSR, 0x40004393
 181              	.set CYREG_PM_USB_CR0, 0x40004394
 182              	.set CYREG_PM_WAKEUP_CFG0, 0x40004398
 183              	.set CYREG_PM_WAKEUP_CFG1, 0x40004399
 184              	.set CYREG_PM_WAKEUP_CFG2, 0x4000439a
 185              	.set CYDEV_PM_ACT_BASE, 0x400043a0
 186              	.set CYDEV_PM_ACT_SIZE, 0x0000000e
 187              	.set CYREG_PM_ACT_CFG0, 0x400043a0
 188              	.set CYREG_PM_ACT_CFG1, 0x400043a1
 189              	.set CYREG_PM_ACT_CFG2, 0x400043a2
 190              	.set CYREG_PM_ACT_CFG3, 0x400043a3
 191              	.set CYREG_PM_ACT_CFG4, 0x400043a4
 192              	.set CYREG_PM_ACT_CFG5, 0x400043a5
 193              	.set CYREG_PM_ACT_CFG6, 0x400043a6
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 99


 194              	.set CYREG_PM_ACT_CFG7, 0x400043a7
 195              	.set CYREG_PM_ACT_CFG8, 0x400043a8
 196              	.set CYREG_PM_ACT_CFG9, 0x400043a9
 197              	.set CYREG_PM_ACT_CFG10, 0x400043aa
 198              	.set CYREG_PM_ACT_CFG11, 0x400043ab
 199              	.set CYREG_PM_ACT_CFG12, 0x400043ac
 200              	.set CYREG_PM_ACT_CFG13, 0x400043ad
 201              	.set CYDEV_PM_STBY_BASE, 0x400043b0
 202              	.set CYDEV_PM_STBY_SIZE, 0x0000000e
 203              	.set CYREG_PM_STBY_CFG0, 0x400043b0
 204              	.set CYREG_PM_STBY_CFG1, 0x400043b1
 205              	.set CYREG_PM_STBY_CFG2, 0x400043b2
 206              	.set CYREG_PM_STBY_CFG3, 0x400043b3
 207              	.set CYREG_PM_STBY_CFG4, 0x400043b4
 208              	.set CYREG_PM_STBY_CFG5, 0x400043b5
 209              	.set CYREG_PM_STBY_CFG6, 0x400043b6
 210              	.set CYREG_PM_STBY_CFG7, 0x400043b7
 211              	.set CYREG_PM_STBY_CFG8, 0x400043b8
 212              	.set CYREG_PM_STBY_CFG9, 0x400043b9
 213              	.set CYREG_PM_STBY_CFG10, 0x400043ba
 214              	.set CYREG_PM_STBY_CFG11, 0x400043bb
 215              	.set CYREG_PM_STBY_CFG12, 0x400043bc
 216              	.set CYREG_PM_STBY_CFG13, 0x400043bd
 217              	.set CYDEV_PM_AVAIL_BASE, 0x400043c0
 218              	.set CYDEV_PM_AVAIL_SIZE, 0x00000017
 219              	.set CYREG_PM_AVAIL_CR0, 0x400043c0
 220              	.set CYREG_PM_AVAIL_CR1, 0x400043c1
 221              	.set CYREG_PM_AVAIL_CR2, 0x400043c2
 222              	.set CYREG_PM_AVAIL_CR3, 0x400043c3
 223              	.set CYREG_PM_AVAIL_CR4, 0x400043c4
 224              	.set CYREG_PM_AVAIL_CR5, 0x400043c5
 225              	.set CYREG_PM_AVAIL_CR6, 0x400043c6
 226              	.set CYREG_PM_AVAIL_SR0, 0x400043d0
 227              	.set CYREG_PM_AVAIL_SR1, 0x400043d1
 228              	.set CYREG_PM_AVAIL_SR2, 0x400043d2
 229              	.set CYREG_PM_AVAIL_SR3, 0x400043d3
 230              	.set CYREG_PM_AVAIL_SR4, 0x400043d4
 231              	.set CYREG_PM_AVAIL_SR5, 0x400043d5
 232              	.set CYREG_PM_AVAIL_SR6, 0x400043d6
 233              	.set CYDEV_PICU_BASE, 0x40004500
 234              	.set CYDEV_PICU_SIZE, 0x000000b0
 235              	.set CYDEV_PICU_INTTYPE_BASE, 0x40004500
 236              	.set CYDEV_PICU_INTTYPE_SIZE, 0x00000080
 237              	.set CYDEV_PICU_INTTYPE_PICU0_BASE, 0x40004500
 238              	.set CYDEV_PICU_INTTYPE_PICU0_SIZE, 0x00000008
 239              	.set CYREG_PICU0_INTTYPE0, 0x40004500
 240              	.set CYREG_PICU0_INTTYPE1, 0x40004501
 241              	.set CYREG_PICU0_INTTYPE2, 0x40004502
 242              	.set CYREG_PICU0_INTTYPE3, 0x40004503
 243              	.set CYREG_PICU0_INTTYPE4, 0x40004504
 244              	.set CYREG_PICU0_INTTYPE5, 0x40004505
 245              	.set CYREG_PICU0_INTTYPE6, 0x40004506
 246              	.set CYREG_PICU0_INTTYPE7, 0x40004507
 247              	.set CYDEV_PICU_INTTYPE_PICU1_BASE, 0x40004508
 248              	.set CYDEV_PICU_INTTYPE_PICU1_SIZE, 0x00000008
 249              	.set CYREG_PICU1_INTTYPE0, 0x40004508
 250              	.set CYREG_PICU1_INTTYPE1, 0x40004509
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 100


 251              	.set CYREG_PICU1_INTTYPE2, 0x4000450a
 252              	.set CYREG_PICU1_INTTYPE3, 0x4000450b
 253              	.set CYREG_PICU1_INTTYPE4, 0x4000450c
 254              	.set CYREG_PICU1_INTTYPE5, 0x4000450d
 255              	.set CYREG_PICU1_INTTYPE6, 0x4000450e
 256              	.set CYREG_PICU1_INTTYPE7, 0x4000450f
 257              	.set CYDEV_PICU_INTTYPE_PICU2_BASE, 0x40004510
 258              	.set CYDEV_PICU_INTTYPE_PICU2_SIZE, 0x00000008
 259              	.set CYREG_PICU2_INTTYPE0, 0x40004510
 260              	.set CYREG_PICU2_INTTYPE1, 0x40004511
 261              	.set CYREG_PICU2_INTTYPE2, 0x40004512
 262              	.set CYREG_PICU2_INTTYPE3, 0x40004513
 263              	.set CYREG_PICU2_INTTYPE4, 0x40004514
 264              	.set CYREG_PICU2_INTTYPE5, 0x40004515
 265              	.set CYREG_PICU2_INTTYPE6, 0x40004516
 266              	.set CYREG_PICU2_INTTYPE7, 0x40004517
 267              	.set CYDEV_PICU_INTTYPE_PICU3_BASE, 0x40004518
 268              	.set CYDEV_PICU_INTTYPE_PICU3_SIZE, 0x00000008
 269              	.set CYREG_PICU3_INTTYPE0, 0x40004518
 270              	.set CYREG_PICU3_INTTYPE1, 0x40004519
 271              	.set CYREG_PICU3_INTTYPE2, 0x4000451a
 272              	.set CYREG_PICU3_INTTYPE3, 0x4000451b
 273              	.set CYREG_PICU3_INTTYPE4, 0x4000451c
 274              	.set CYREG_PICU3_INTTYPE5, 0x4000451d
 275              	.set CYREG_PICU3_INTTYPE6, 0x4000451e
 276              	.set CYREG_PICU3_INTTYPE7, 0x4000451f
 277              	.set CYDEV_PICU_INTTYPE_PICU4_BASE, 0x40004520
 278              	.set CYDEV_PICU_INTTYPE_PICU4_SIZE, 0x00000008
 279              	.set CYREG_PICU4_INTTYPE0, 0x40004520
 280              	.set CYREG_PICU4_INTTYPE1, 0x40004521
 281              	.set CYREG_PICU4_INTTYPE2, 0x40004522
 282              	.set CYREG_PICU4_INTTYPE3, 0x40004523
 283              	.set CYREG_PICU4_INTTYPE4, 0x40004524
 284              	.set CYREG_PICU4_INTTYPE5, 0x40004525
 285              	.set CYREG_PICU4_INTTYPE6, 0x40004526
 286              	.set CYREG_PICU4_INTTYPE7, 0x40004527
 287              	.set CYDEV_PICU_INTTYPE_PICU5_BASE, 0x40004528
 288              	.set CYDEV_PICU_INTTYPE_PICU5_SIZE, 0x00000008
 289              	.set CYREG_PICU5_INTTYPE0, 0x40004528
 290              	.set CYREG_PICU5_INTTYPE1, 0x40004529
 291              	.set CYREG_PICU5_INTTYPE2, 0x4000452a
 292              	.set CYREG_PICU5_INTTYPE3, 0x4000452b
 293              	.set CYREG_PICU5_INTTYPE4, 0x4000452c
 294              	.set CYREG_PICU5_INTTYPE5, 0x4000452d
 295              	.set CYREG_PICU5_INTTYPE6, 0x4000452e
 296              	.set CYREG_PICU5_INTTYPE7, 0x4000452f
 297              	.set CYDEV_PICU_INTTYPE_PICU6_BASE, 0x40004530
 298              	.set CYDEV_PICU_INTTYPE_PICU6_SIZE, 0x00000008
 299              	.set CYREG_PICU6_INTTYPE0, 0x40004530
 300              	.set CYREG_PICU6_INTTYPE1, 0x40004531
 301              	.set CYREG_PICU6_INTTYPE2, 0x40004532
 302              	.set CYREG_PICU6_INTTYPE3, 0x40004533
 303              	.set CYREG_PICU6_INTTYPE4, 0x40004534
 304              	.set CYREG_PICU6_INTTYPE5, 0x40004535
 305              	.set CYREG_PICU6_INTTYPE6, 0x40004536
 306              	.set CYREG_PICU6_INTTYPE7, 0x40004537
 307              	.set CYDEV_PICU_INTTYPE_PICU12_BASE, 0x40004560
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 101


 308              	.set CYDEV_PICU_INTTYPE_PICU12_SIZE, 0x00000008
 309              	.set CYREG_PICU12_INTTYPE0, 0x40004560
 310              	.set CYREG_PICU12_INTTYPE1, 0x40004561
 311              	.set CYREG_PICU12_INTTYPE2, 0x40004562
 312              	.set CYREG_PICU12_INTTYPE3, 0x40004563
 313              	.set CYREG_PICU12_INTTYPE4, 0x40004564
 314              	.set CYREG_PICU12_INTTYPE5, 0x40004565
 315              	.set CYREG_PICU12_INTTYPE6, 0x40004566
 316              	.set CYREG_PICU12_INTTYPE7, 0x40004567
 317              	.set CYDEV_PICU_INTTYPE_PICU15_BASE, 0x40004578
 318              	.set CYDEV_PICU_INTTYPE_PICU15_SIZE, 0x00000008
 319              	.set CYREG_PICU15_INTTYPE0, 0x40004578
 320              	.set CYREG_PICU15_INTTYPE1, 0x40004579
 321              	.set CYREG_PICU15_INTTYPE2, 0x4000457a
 322              	.set CYREG_PICU15_INTTYPE3, 0x4000457b
 323              	.set CYREG_PICU15_INTTYPE4, 0x4000457c
 324              	.set CYREG_PICU15_INTTYPE5, 0x4000457d
 325              	.set CYREG_PICU15_INTTYPE6, 0x4000457e
 326              	.set CYREG_PICU15_INTTYPE7, 0x4000457f
 327              	.set CYDEV_PICU_STAT_BASE, 0x40004580
 328              	.set CYDEV_PICU_STAT_SIZE, 0x00000010
 329              	.set CYDEV_PICU_STAT_PICU0_BASE, 0x40004580
 330              	.set CYDEV_PICU_STAT_PICU0_SIZE, 0x00000001
 331              	.set CYREG_PICU0_INTSTAT, 0x40004580
 332              	.set CYDEV_PICU_STAT_PICU1_BASE, 0x40004581
 333              	.set CYDEV_PICU_STAT_PICU1_SIZE, 0x00000001
 334              	.set CYREG_PICU1_INTSTAT, 0x40004581
 335              	.set CYDEV_PICU_STAT_PICU2_BASE, 0x40004582
 336              	.set CYDEV_PICU_STAT_PICU2_SIZE, 0x00000001
 337              	.set CYREG_PICU2_INTSTAT, 0x40004582
 338              	.set CYDEV_PICU_STAT_PICU3_BASE, 0x40004583
 339              	.set CYDEV_PICU_STAT_PICU3_SIZE, 0x00000001
 340              	.set CYREG_PICU3_INTSTAT, 0x40004583
 341              	.set CYDEV_PICU_STAT_PICU4_BASE, 0x40004584
 342              	.set CYDEV_PICU_STAT_PICU4_SIZE, 0x00000001
 343              	.set CYREG_PICU4_INTSTAT, 0x40004584
 344              	.set CYDEV_PICU_STAT_PICU5_BASE, 0x40004585
 345              	.set CYDEV_PICU_STAT_PICU5_SIZE, 0x00000001
 346              	.set CYREG_PICU5_INTSTAT, 0x40004585
 347              	.set CYDEV_PICU_STAT_PICU6_BASE, 0x40004586
 348              	.set CYDEV_PICU_STAT_PICU6_SIZE, 0x00000001
 349              	.set CYREG_PICU6_INTSTAT, 0x40004586
 350              	.set CYDEV_PICU_STAT_PICU12_BASE, 0x4000458c
 351              	.set CYDEV_PICU_STAT_PICU12_SIZE, 0x00000001
 352              	.set CYREG_PICU12_INTSTAT, 0x4000458c
 353              	.set CYDEV_PICU_STAT_PICU15_BASE, 0x4000458f
 354              	.set CYDEV_PICU_STAT_PICU15_SIZE, 0x00000001
 355              	.set CYREG_PICU15_INTSTAT, 0x4000458f
 356              	.set CYDEV_PICU_SNAP_BASE, 0x40004590
 357              	.set CYDEV_PICU_SNAP_SIZE, 0x00000010
 358              	.set CYDEV_PICU_SNAP_PICU0_BASE, 0x40004590
 359              	.set CYDEV_PICU_SNAP_PICU0_SIZE, 0x00000001
 360              	.set CYREG_PICU0_SNAP, 0x40004590
 361              	.set CYDEV_PICU_SNAP_PICU1_BASE, 0x40004591
 362              	.set CYDEV_PICU_SNAP_PICU1_SIZE, 0x00000001
 363              	.set CYREG_PICU1_SNAP, 0x40004591
 364              	.set CYDEV_PICU_SNAP_PICU2_BASE, 0x40004592
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 102


 365              	.set CYDEV_PICU_SNAP_PICU2_SIZE, 0x00000001
 366              	.set CYREG_PICU2_SNAP, 0x40004592
 367              	.set CYDEV_PICU_SNAP_PICU3_BASE, 0x40004593
 368              	.set CYDEV_PICU_SNAP_PICU3_SIZE, 0x00000001
 369              	.set CYREG_PICU3_SNAP, 0x40004593
 370              	.set CYDEV_PICU_SNAP_PICU4_BASE, 0x40004594
 371              	.set CYDEV_PICU_SNAP_PICU4_SIZE, 0x00000001
 372              	.set CYREG_PICU4_SNAP, 0x40004594
 373              	.set CYDEV_PICU_SNAP_PICU5_BASE, 0x40004595
 374              	.set CYDEV_PICU_SNAP_PICU5_SIZE, 0x00000001
 375              	.set CYREG_PICU5_SNAP, 0x40004595
 376              	.set CYDEV_PICU_SNAP_PICU6_BASE, 0x40004596
 377              	.set CYDEV_PICU_SNAP_PICU6_SIZE, 0x00000001
 378              	.set CYREG_PICU6_SNAP, 0x40004596
 379              	.set CYDEV_PICU_SNAP_PICU12_BASE, 0x4000459c
 380              	.set CYDEV_PICU_SNAP_PICU12_SIZE, 0x00000001
 381              	.set CYREG_PICU12_SNAP, 0x4000459c
 382              	.set CYDEV_PICU_SNAP_PICU_15_BASE, 0x4000459f
 383              	.set CYDEV_PICU_SNAP_PICU_15_SIZE, 0x00000001
 384              	.set CYREG_PICU_15_SNAP_15, 0x4000459f
 385              	.set CYDEV_PICU_DISABLE_COR_BASE, 0x400045a0
 386              	.set CYDEV_PICU_DISABLE_COR_SIZE, 0x00000010
 387              	.set CYDEV_PICU_DISABLE_COR_PICU0_BASE, 0x400045a0
 388              	.set CYDEV_PICU_DISABLE_COR_PICU0_SIZE, 0x00000001
 389              	.set CYREG_PICU0_DISABLE_COR, 0x400045a0
 390              	.set CYDEV_PICU_DISABLE_COR_PICU1_BASE, 0x400045a1
 391              	.set CYDEV_PICU_DISABLE_COR_PICU1_SIZE, 0x00000001
 392              	.set CYREG_PICU1_DISABLE_COR, 0x400045a1
 393              	.set CYDEV_PICU_DISABLE_COR_PICU2_BASE, 0x400045a2
 394              	.set CYDEV_PICU_DISABLE_COR_PICU2_SIZE, 0x00000001
 395              	.set CYREG_PICU2_DISABLE_COR, 0x400045a2
 396              	.set CYDEV_PICU_DISABLE_COR_PICU3_BASE, 0x400045a3
 397              	.set CYDEV_PICU_DISABLE_COR_PICU3_SIZE, 0x00000001
 398              	.set CYREG_PICU3_DISABLE_COR, 0x400045a3
 399              	.set CYDEV_PICU_DISABLE_COR_PICU4_BASE, 0x400045a4
 400              	.set CYDEV_PICU_DISABLE_COR_PICU4_SIZE, 0x00000001
 401              	.set CYREG_PICU4_DISABLE_COR, 0x400045a4
 402              	.set CYDEV_PICU_DISABLE_COR_PICU5_BASE, 0x400045a5
 403              	.set CYDEV_PICU_DISABLE_COR_PICU5_SIZE, 0x00000001
 404              	.set CYREG_PICU5_DISABLE_COR, 0x400045a5
 405              	.set CYDEV_PICU_DISABLE_COR_PICU6_BASE, 0x400045a6
 406              	.set CYDEV_PICU_DISABLE_COR_PICU6_SIZE, 0x00000001
 407              	.set CYREG_PICU6_DISABLE_COR, 0x400045a6
 408              	.set CYDEV_PICU_DISABLE_COR_PICU12_BASE, 0x400045ac
 409              	.set CYDEV_PICU_DISABLE_COR_PICU12_SIZE, 0x00000001
 410              	.set CYREG_PICU12_DISABLE_COR, 0x400045ac
 411              	.set CYDEV_PICU_DISABLE_COR_PICU15_BASE, 0x400045af
 412              	.set CYDEV_PICU_DISABLE_COR_PICU15_SIZE, 0x00000001
 413              	.set CYREG_PICU15_DISABLE_COR, 0x400045af
 414              	.set CYDEV_MFGCFG_BASE, 0x40004600
 415              	.set CYDEV_MFGCFG_SIZE, 0x000000ed
 416              	.set CYDEV_MFGCFG_ANAIF_BASE, 0x40004600
 417              	.set CYDEV_MFGCFG_ANAIF_SIZE, 0x00000038
 418              	.set CYDEV_MFGCFG_ANAIF_DAC0_BASE, 0x40004608
 419              	.set CYDEV_MFGCFG_ANAIF_DAC0_SIZE, 0x00000001
 420              	.set CYREG_DAC0_TR, 0x40004608
 421              	.set CYDEV_MFGCFG_ANAIF_DAC1_BASE, 0x40004609
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 103


 422              	.set CYDEV_MFGCFG_ANAIF_DAC1_SIZE, 0x00000001
 423              	.set CYREG_DAC1_TR, 0x40004609
 424              	.set CYDEV_MFGCFG_ANAIF_DAC2_BASE, 0x4000460a
 425              	.set CYDEV_MFGCFG_ANAIF_DAC2_SIZE, 0x00000001
 426              	.set CYREG_DAC2_TR, 0x4000460a
 427              	.set CYDEV_MFGCFG_ANAIF_DAC3_BASE, 0x4000460b
 428              	.set CYDEV_MFGCFG_ANAIF_DAC3_SIZE, 0x00000001
 429              	.set CYREG_DAC3_TR, 0x4000460b
 430              	.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE, 0x40004610
 431              	.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE, 0x00000001
 432              	.set CYREG_NPUMP_DSM_TR0, 0x40004610
 433              	.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE, 0x40004611
 434              	.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE, 0x00000001
 435              	.set CYREG_NPUMP_SC_TR0, 0x40004611
 436              	.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE, 0x40004612
 437              	.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE, 0x00000001
 438              	.set CYREG_NPUMP_OPAMP_TR0, 0x40004612
 439              	.set CYDEV_MFGCFG_ANAIF_SAR0_BASE, 0x40004614
 440              	.set CYDEV_MFGCFG_ANAIF_SAR0_SIZE, 0x00000001
 441              	.set CYREG_SAR0_TR0, 0x40004614
 442              	.set CYDEV_MFGCFG_ANAIF_SAR1_BASE, 0x40004616
 443              	.set CYDEV_MFGCFG_ANAIF_SAR1_SIZE, 0x00000001
 444              	.set CYREG_SAR1_TR0, 0x40004616
 445              	.set CYDEV_MFGCFG_ANAIF_OPAMP0_BASE, 0x40004620
 446              	.set CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE, 0x00000002
 447              	.set CYREG_OPAMP0_TR0, 0x40004620
 448              	.set CYREG_OPAMP0_TR1, 0x40004621
 449              	.set CYDEV_MFGCFG_ANAIF_OPAMP1_BASE, 0x40004622
 450              	.set CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE, 0x00000002
 451              	.set CYREG_OPAMP1_TR0, 0x40004622
 452              	.set CYREG_OPAMP1_TR1, 0x40004623
 453              	.set CYDEV_MFGCFG_ANAIF_OPAMP2_BASE, 0x40004624
 454              	.set CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE, 0x00000002
 455              	.set CYREG_OPAMP2_TR0, 0x40004624
 456              	.set CYREG_OPAMP2_TR1, 0x40004625
 457              	.set CYDEV_MFGCFG_ANAIF_OPAMP3_BASE, 0x40004626
 458              	.set CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE, 0x00000002
 459              	.set CYREG_OPAMP3_TR0, 0x40004626
 460              	.set CYREG_OPAMP3_TR1, 0x40004627
 461              	.set CYDEV_MFGCFG_ANAIF_CMP0_BASE, 0x40004630
 462              	.set CYDEV_MFGCFG_ANAIF_CMP0_SIZE, 0x00000002
 463              	.set CYREG_CMP0_TR0, 0x40004630
 464              	.set CYREG_CMP0_TR1, 0x40004631
 465              	.set CYDEV_MFGCFG_ANAIF_CMP1_BASE, 0x40004632
 466              	.set CYDEV_MFGCFG_ANAIF_CMP1_SIZE, 0x00000002
 467              	.set CYREG_CMP1_TR0, 0x40004632
 468              	.set CYREG_CMP1_TR1, 0x40004633
 469              	.set CYDEV_MFGCFG_ANAIF_CMP2_BASE, 0x40004634
 470              	.set CYDEV_MFGCFG_ANAIF_CMP2_SIZE, 0x00000002
 471              	.set CYREG_CMP2_TR0, 0x40004634
 472              	.set CYREG_CMP2_TR1, 0x40004635
 473              	.set CYDEV_MFGCFG_ANAIF_CMP3_BASE, 0x40004636
 474              	.set CYDEV_MFGCFG_ANAIF_CMP3_SIZE, 0x00000002
 475              	.set CYREG_CMP3_TR0, 0x40004636
 476              	.set CYREG_CMP3_TR1, 0x40004637
 477              	.set CYDEV_MFGCFG_PWRSYS_BASE, 0x40004680
 478              	.set CYDEV_MFGCFG_PWRSYS_SIZE, 0x0000000b
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 104


 479              	.set CYREG_PWRSYS_HIB_TR0, 0x40004680
 480              	.set CYREG_PWRSYS_HIB_TR1, 0x40004681
 481              	.set CYREG_PWRSYS_I2C_TR, 0x40004682
 482              	.set CYREG_PWRSYS_SLP_TR, 0x40004683
 483              	.set CYREG_PWRSYS_BUZZ_TR, 0x40004684
 484              	.set CYREG_PWRSYS_WAKE_TR0, 0x40004685
 485              	.set CYREG_PWRSYS_WAKE_TR1, 0x40004686
 486              	.set CYREG_PWRSYS_BREF_TR, 0x40004687
 487              	.set CYREG_PWRSYS_BG_TR, 0x40004688
 488              	.set CYREG_PWRSYS_WAKE_TR2, 0x40004689
 489              	.set CYREG_PWRSYS_WAKE_TR3, 0x4000468a
 490              	.set CYDEV_MFGCFG_ILO_BASE, 0x40004690
 491              	.set CYDEV_MFGCFG_ILO_SIZE, 0x00000002
 492              	.set CYREG_ILO_TR0, 0x40004690
 493              	.set CYREG_ILO_TR1, 0x40004691
 494              	.set CYDEV_MFGCFG_X32_BASE, 0x40004698
 495              	.set CYDEV_MFGCFG_X32_SIZE, 0x00000001
 496              	.set CYREG_X32_TR, 0x40004698
 497              	.set CYDEV_MFGCFG_IMO_BASE, 0x400046a0
 498              	.set CYDEV_MFGCFG_IMO_SIZE, 0x00000005
 499              	.set CYREG_IMO_TR0, 0x400046a0
 500              	.set CYREG_IMO_TR1, 0x400046a1
 501              	.set CYREG_IMO_GAIN, 0x400046a2
 502              	.set CYREG_IMO_C36M, 0x400046a3
 503              	.set CYREG_IMO_TR2, 0x400046a4
 504              	.set CYDEV_MFGCFG_XMHZ_BASE, 0x400046a8
 505              	.set CYDEV_MFGCFG_XMHZ_SIZE, 0x00000001
 506              	.set CYREG_XMHZ_TR, 0x400046a8
 507              	.set CYREG_MFGCFG_DLY, 0x400046c0
 508              	.set CYDEV_MFGCFG_MLOGIC_BASE, 0x400046e0
 509              	.set CYDEV_MFGCFG_MLOGIC_SIZE, 0x0000000d
 510              	.set CYREG_MLOGIC_DMPSTR, 0x400046e2
 511              	.set CYDEV_MFGCFG_MLOGIC_SEG_BASE, 0x400046e4
 512              	.set CYDEV_MFGCFG_MLOGIC_SEG_SIZE, 0x00000002
 513              	.set CYREG_MLOGIC_SEG_CR, 0x400046e4
 514              	.set CYREG_MLOGIC_SEG_CFG0, 0x400046e5
 515              	.set CYREG_MLOGIC_DEBUG, 0x400046e8
 516              	.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE, 0x400046ea
 517              	.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE, 0x00000001
 518              	.set CYREG_MLOGIC_CPU_SCR_CPU_SCR, 0x400046ea
 519              	.set CYREG_MLOGIC_REV_ID, 0x400046ec
 520              	.set CYDEV_RESET_BASE, 0x400046f0
 521              	.set CYDEV_RESET_SIZE, 0x0000000f
 522              	.set CYREG_RESET_IPOR_CR0, 0x400046f0
 523              	.set CYREG_RESET_IPOR_CR1, 0x400046f1
 524              	.set CYREG_RESET_IPOR_CR2, 0x400046f2
 525              	.set CYREG_RESET_IPOR_CR3, 0x400046f3
 526              	.set CYREG_RESET_CR0, 0x400046f4
 527              	.set CYREG_RESET_CR1, 0x400046f5
 528              	.set CYREG_RESET_CR2, 0x400046f6
 529              	.set CYREG_RESET_CR3, 0x400046f7
 530              	.set CYREG_RESET_CR4, 0x400046f8
 531              	.set CYREG_RESET_CR5, 0x400046f9
 532              	.set CYREG_RESET_SR0, 0x400046fa
 533              	.set CYREG_RESET_SR1, 0x400046fb
 534              	.set CYREG_RESET_SR2, 0x400046fc
 535              	.set CYREG_RESET_SR3, 0x400046fd
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 105


 536              	.set CYREG_RESET_TR, 0x400046fe
 537              	.set CYDEV_SPC_BASE, 0x40004700
 538              	.set CYDEV_SPC_SIZE, 0x00000100
 539              	.set CYREG_SPC_FM_EE_CR, 0x40004700
 540              	.set CYREG_SPC_FM_EE_WAKE_CNT, 0x40004701
 541              	.set CYREG_SPC_EE_SCR, 0x40004702
 542              	.set CYREG_SPC_EE_ERR, 0x40004703
 543              	.set CYREG_SPC_CPU_DATA, 0x40004720
 544              	.set CYREG_SPC_DMA_DATA, 0x40004721
 545              	.set CYREG_SPC_SR, 0x40004722
 546              	.set CYREG_SPC_CR, 0x40004723
 547              	.set CYDEV_SPC_DMM_MAP_BASE, 0x40004780
 548              	.set CYDEV_SPC_DMM_MAP_SIZE, 0x00000080
 549              	.set CYREG_SPC_DMM_MAP_SRAM_MBASE, 0x40004780
 550              	.set CYREG_SPC_DMM_MAP_SRAM_MSIZE, 0x00000080
 551              	.set CYDEV_CACHE_BASE, 0x40004800
 552              	.set CYDEV_CACHE_SIZE, 0x0000009c
 553              	.set CYREG_CACHE_CC_CTL, 0x40004800
 554              	.set CYREG_CACHE_ECC_CORR, 0x40004880
 555              	.set CYREG_CACHE_ECC_ERR, 0x40004888
 556              	.set CYREG_CACHE_FLASH_ERR, 0x40004890
 557              	.set CYREG_CACHE_HITMISS, 0x40004898
 558              	.set CYDEV_I2C_BASE, 0x40004900
 559              	.set CYDEV_I2C_SIZE, 0x000000e1
 560              	.set CYREG_I2C_XCFG, 0x400049c8
 561              	.set CYREG_I2C_ADR, 0x400049ca
 562              	.set CYREG_I2C_CFG, 0x400049d6
 563              	.set CYREG_I2C_CSR, 0x400049d7
 564              	.set CYREG_I2C_D, 0x400049d8
 565              	.set CYREG_I2C_MCSR, 0x400049d9
 566              	.set CYREG_I2C_CLK_DIV1, 0x400049db
 567              	.set CYREG_I2C_CLK_DIV2, 0x400049dc
 568              	.set CYREG_I2C_TMOUT_CSR, 0x400049dd
 569              	.set CYREG_I2C_TMOUT_SR, 0x400049de
 570              	.set CYREG_I2C_TMOUT_CFG0, 0x400049df
 571              	.set CYREG_I2C_TMOUT_CFG1, 0x400049e0
 572              	.set CYDEV_DEC_BASE, 0x40004e00
 573              	.set CYDEV_DEC_SIZE, 0x00000015
 574              	.set CYREG_DEC_CR, 0x40004e00
 575              	.set CYREG_DEC_SR, 0x40004e01
 576              	.set CYREG_DEC_SHIFT1, 0x40004e02
 577              	.set CYREG_DEC_SHIFT2, 0x40004e03
 578              	.set CYREG_DEC_DR2, 0x40004e04
 579              	.set CYREG_DEC_DR2H, 0x40004e05
 580              	.set CYREG_DEC_DR1, 0x40004e06
 581              	.set CYREG_DEC_OCOR, 0x40004e08
 582              	.set CYREG_DEC_OCORM, 0x40004e09
 583              	.set CYREG_DEC_OCORH, 0x40004e0a
 584              	.set CYREG_DEC_GCOR, 0x40004e0c
 585              	.set CYREG_DEC_GCORH, 0x40004e0d
 586              	.set CYREG_DEC_GVAL, 0x40004e0e
 587              	.set CYREG_DEC_OUTSAMP, 0x40004e10
 588              	.set CYREG_DEC_OUTSAMPM, 0x40004e11
 589              	.set CYREG_DEC_OUTSAMPH, 0x40004e12
 590              	.set CYREG_DEC_OUTSAMPS, 0x40004e13
 591              	.set CYREG_DEC_COHER, 0x40004e14
 592              	.set CYDEV_TMR0_BASE, 0x40004f00
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 106


 593              	.set CYDEV_TMR0_SIZE, 0x0000000c
 594              	.set CYREG_TMR0_CFG0, 0x40004f00
 595              	.set CYREG_TMR0_CFG1, 0x40004f01
 596              	.set CYREG_TMR0_CFG2, 0x40004f02
 597              	.set CYREG_TMR0_SR0, 0x40004f03
 598              	.set CYREG_TMR0_PER0, 0x40004f04
 599              	.set CYREG_TMR0_PER1, 0x40004f05
 600              	.set CYREG_TMR0_CNT_CMP0, 0x40004f06
 601              	.set CYREG_TMR0_CNT_CMP1, 0x40004f07
 602              	.set CYREG_TMR0_CAP0, 0x40004f08
 603              	.set CYREG_TMR0_CAP1, 0x40004f09
 604              	.set CYREG_TMR0_RT0, 0x40004f0a
 605              	.set CYREG_TMR0_RT1, 0x40004f0b
 606              	.set CYDEV_TMR1_BASE, 0x40004f0c
 607              	.set CYDEV_TMR1_SIZE, 0x0000000c
 608              	.set CYREG_TMR1_CFG0, 0x40004f0c
 609              	.set CYREG_TMR1_CFG1, 0x40004f0d
 610              	.set CYREG_TMR1_CFG2, 0x40004f0e
 611              	.set CYREG_TMR1_SR0, 0x40004f0f
 612              	.set CYREG_TMR1_PER0, 0x40004f10
 613              	.set CYREG_TMR1_PER1, 0x40004f11
 614              	.set CYREG_TMR1_CNT_CMP0, 0x40004f12
 615              	.set CYREG_TMR1_CNT_CMP1, 0x40004f13
 616              	.set CYREG_TMR1_CAP0, 0x40004f14
 617              	.set CYREG_TMR1_CAP1, 0x40004f15
 618              	.set CYREG_TMR1_RT0, 0x40004f16
 619              	.set CYREG_TMR1_RT1, 0x40004f17
 620              	.set CYDEV_TMR2_BASE, 0x40004f18
 621              	.set CYDEV_TMR2_SIZE, 0x0000000c
 622              	.set CYREG_TMR2_CFG0, 0x40004f18
 623              	.set CYREG_TMR2_CFG1, 0x40004f19
 624              	.set CYREG_TMR2_CFG2, 0x40004f1a
 625              	.set CYREG_TMR2_SR0, 0x40004f1b
 626              	.set CYREG_TMR2_PER0, 0x40004f1c
 627              	.set CYREG_TMR2_PER1, 0x40004f1d
 628              	.set CYREG_TMR2_CNT_CMP0, 0x40004f1e
 629              	.set CYREG_TMR2_CNT_CMP1, 0x40004f1f
 630              	.set CYREG_TMR2_CAP0, 0x40004f20
 631              	.set CYREG_TMR2_CAP1, 0x40004f21
 632              	.set CYREG_TMR2_RT0, 0x40004f22
 633              	.set CYREG_TMR2_RT1, 0x40004f23
 634              	.set CYDEV_TMR3_BASE, 0x40004f24
 635              	.set CYDEV_TMR3_SIZE, 0x0000000c
 636              	.set CYREG_TMR3_CFG0, 0x40004f24
 637              	.set CYREG_TMR3_CFG1, 0x40004f25
 638              	.set CYREG_TMR3_CFG2, 0x40004f26
 639              	.set CYREG_TMR3_SR0, 0x40004f27
 640              	.set CYREG_TMR3_PER0, 0x40004f28
 641              	.set CYREG_TMR3_PER1, 0x40004f29
 642              	.set CYREG_TMR3_CNT_CMP0, 0x40004f2a
 643              	.set CYREG_TMR3_CNT_CMP1, 0x40004f2b
 644              	.set CYREG_TMR3_CAP0, 0x40004f2c
 645              	.set CYREG_TMR3_CAP1, 0x40004f2d
 646              	.set CYREG_TMR3_RT0, 0x40004f2e
 647              	.set CYREG_TMR3_RT1, 0x40004f2f
 648              	.set CYDEV_IO_BASE, 0x40005000
 649              	.set CYDEV_IO_SIZE, 0x00000200
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 107


 650              	.set CYDEV_IO_PC_BASE, 0x40005000
 651              	.set CYDEV_IO_PC_SIZE, 0x00000080
 652              	.set CYDEV_IO_PC_PRT0_BASE, 0x40005000
 653              	.set CYDEV_IO_PC_PRT0_SIZE, 0x00000008
 654              	.set CYREG_PRT0_PC0, 0x40005000
 655              	.set CYREG_PRT0_PC1, 0x40005001
 656              	.set CYREG_PRT0_PC2, 0x40005002
 657              	.set CYREG_PRT0_PC3, 0x40005003
 658              	.set CYREG_PRT0_PC4, 0x40005004
 659              	.set CYREG_PRT0_PC5, 0x40005005
 660              	.set CYREG_PRT0_PC6, 0x40005006
 661              	.set CYREG_PRT0_PC7, 0x40005007
 662              	.set CYDEV_IO_PC_PRT1_BASE, 0x40005008
 663              	.set CYDEV_IO_PC_PRT1_SIZE, 0x00000008
 664              	.set CYREG_PRT1_PC0, 0x40005008
 665              	.set CYREG_PRT1_PC1, 0x40005009
 666              	.set CYREG_PRT1_PC2, 0x4000500a
 667              	.set CYREG_PRT1_PC3, 0x4000500b
 668              	.set CYREG_PRT1_PC4, 0x4000500c
 669              	.set CYREG_PRT1_PC5, 0x4000500d
 670              	.set CYREG_PRT1_PC6, 0x4000500e
 671              	.set CYREG_PRT1_PC7, 0x4000500f
 672              	.set CYDEV_IO_PC_PRT2_BASE, 0x40005010
 673              	.set CYDEV_IO_PC_PRT2_SIZE, 0x00000008
 674              	.set CYREG_PRT2_PC0, 0x40005010
 675              	.set CYREG_PRT2_PC1, 0x40005011
 676              	.set CYREG_PRT2_PC2, 0x40005012
 677              	.set CYREG_PRT2_PC3, 0x40005013
 678              	.set CYREG_PRT2_PC4, 0x40005014
 679              	.set CYREG_PRT2_PC5, 0x40005015
 680              	.set CYREG_PRT2_PC6, 0x40005016
 681              	.set CYREG_PRT2_PC7, 0x40005017
 682              	.set CYDEV_IO_PC_PRT3_BASE, 0x40005018
 683              	.set CYDEV_IO_PC_PRT3_SIZE, 0x00000008
 684              	.set CYREG_PRT3_PC0, 0x40005018
 685              	.set CYREG_PRT3_PC1, 0x40005019
 686              	.set CYREG_PRT3_PC2, 0x4000501a
 687              	.set CYREG_PRT3_PC3, 0x4000501b
 688              	.set CYREG_PRT3_PC4, 0x4000501c
 689              	.set CYREG_PRT3_PC5, 0x4000501d
 690              	.set CYREG_PRT3_PC6, 0x4000501e
 691              	.set CYREG_PRT3_PC7, 0x4000501f
 692              	.set CYDEV_IO_PC_PRT4_BASE, 0x40005020
 693              	.set CYDEV_IO_PC_PRT4_SIZE, 0x00000008
 694              	.set CYREG_PRT4_PC0, 0x40005020
 695              	.set CYREG_PRT4_PC1, 0x40005021
 696              	.set CYREG_PRT4_PC2, 0x40005022
 697              	.set CYREG_PRT4_PC3, 0x40005023
 698              	.set CYREG_PRT4_PC4, 0x40005024
 699              	.set CYREG_PRT4_PC5, 0x40005025
 700              	.set CYREG_PRT4_PC6, 0x40005026
 701              	.set CYREG_PRT4_PC7, 0x40005027
 702              	.set CYDEV_IO_PC_PRT5_BASE, 0x40005028
 703              	.set CYDEV_IO_PC_PRT5_SIZE, 0x00000008
 704              	.set CYREG_PRT5_PC0, 0x40005028
 705              	.set CYREG_PRT5_PC1, 0x40005029
 706              	.set CYREG_PRT5_PC2, 0x4000502a
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 108


 707              	.set CYREG_PRT5_PC3, 0x4000502b
 708              	.set CYREG_PRT5_PC4, 0x4000502c
 709              	.set CYREG_PRT5_PC5, 0x4000502d
 710              	.set CYREG_PRT5_PC6, 0x4000502e
 711              	.set CYREG_PRT5_PC7, 0x4000502f
 712              	.set CYDEV_IO_PC_PRT6_BASE, 0x40005030
 713              	.set CYDEV_IO_PC_PRT6_SIZE, 0x00000008
 714              	.set CYREG_PRT6_PC0, 0x40005030
 715              	.set CYREG_PRT6_PC1, 0x40005031
 716              	.set CYREG_PRT6_PC2, 0x40005032
 717              	.set CYREG_PRT6_PC3, 0x40005033
 718              	.set CYREG_PRT6_PC4, 0x40005034
 719              	.set CYREG_PRT6_PC5, 0x40005035
 720              	.set CYREG_PRT6_PC6, 0x40005036
 721              	.set CYREG_PRT6_PC7, 0x40005037
 722              	.set CYDEV_IO_PC_PRT12_BASE, 0x40005060
 723              	.set CYDEV_IO_PC_PRT12_SIZE, 0x00000008
 724              	.set CYREG_PRT12_PC0, 0x40005060
 725              	.set CYREG_PRT12_PC1, 0x40005061
 726              	.set CYREG_PRT12_PC2, 0x40005062
 727              	.set CYREG_PRT12_PC3, 0x40005063
 728              	.set CYREG_PRT12_PC4, 0x40005064
 729              	.set CYREG_PRT12_PC5, 0x40005065
 730              	.set CYREG_PRT12_PC6, 0x40005066
 731              	.set CYREG_PRT12_PC7, 0x40005067
 732              	.set CYDEV_IO_PC_PRT15_BASE, 0x40005078
 733              	.set CYDEV_IO_PC_PRT15_SIZE, 0x00000006
 734              	.set CYREG_IO_PC_PRT15_PC0, 0x40005078
 735              	.set CYREG_IO_PC_PRT15_PC1, 0x40005079
 736              	.set CYREG_IO_PC_PRT15_PC2, 0x4000507a
 737              	.set CYREG_IO_PC_PRT15_PC3, 0x4000507b
 738              	.set CYREG_IO_PC_PRT15_PC4, 0x4000507c
 739              	.set CYREG_IO_PC_PRT15_PC5, 0x4000507d
 740              	.set CYDEV_IO_PC_PRT15_7_6_BASE, 0x4000507e
 741              	.set CYDEV_IO_PC_PRT15_7_6_SIZE, 0x00000002
 742              	.set CYREG_IO_PC_PRT15_7_6_PC0, 0x4000507e
 743              	.set CYREG_IO_PC_PRT15_7_6_PC1, 0x4000507f
 744              	.set CYDEV_IO_DR_BASE, 0x40005080
 745              	.set CYDEV_IO_DR_SIZE, 0x00000010
 746              	.set CYDEV_IO_DR_PRT0_BASE, 0x40005080
 747              	.set CYDEV_IO_DR_PRT0_SIZE, 0x00000001
 748              	.set CYREG_PRT0_DR_ALIAS, 0x40005080
 749              	.set CYDEV_IO_DR_PRT1_BASE, 0x40005081
 750              	.set CYDEV_IO_DR_PRT1_SIZE, 0x00000001
 751              	.set CYREG_PRT1_DR_ALIAS, 0x40005081
 752              	.set CYDEV_IO_DR_PRT2_BASE, 0x40005082
 753              	.set CYDEV_IO_DR_PRT2_SIZE, 0x00000001
 754              	.set CYREG_PRT2_DR_ALIAS, 0x40005082
 755              	.set CYDEV_IO_DR_PRT3_BASE, 0x40005083
 756              	.set CYDEV_IO_DR_PRT3_SIZE, 0x00000001
 757              	.set CYREG_PRT3_DR_ALIAS, 0x40005083
 758              	.set CYDEV_IO_DR_PRT4_BASE, 0x40005084
 759              	.set CYDEV_IO_DR_PRT4_SIZE, 0x00000001
 760              	.set CYREG_PRT4_DR_ALIAS, 0x40005084
 761              	.set CYDEV_IO_DR_PRT5_BASE, 0x40005085
 762              	.set CYDEV_IO_DR_PRT5_SIZE, 0x00000001
 763              	.set CYREG_PRT5_DR_ALIAS, 0x40005085
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 109


 764              	.set CYDEV_IO_DR_PRT6_BASE, 0x40005086
 765              	.set CYDEV_IO_DR_PRT6_SIZE, 0x00000001
 766              	.set CYREG_PRT6_DR_ALIAS, 0x40005086
 767              	.set CYDEV_IO_DR_PRT12_BASE, 0x4000508c
 768              	.set CYDEV_IO_DR_PRT12_SIZE, 0x00000001
 769              	.set CYREG_PRT12_DR_ALIAS, 0x4000508c
 770              	.set CYDEV_IO_DR_PRT15_BASE, 0x4000508f
 771              	.set CYDEV_IO_DR_PRT15_SIZE, 0x00000001
 772              	.set CYREG_PRT15_DR_15_ALIAS, 0x4000508f
 773              	.set CYDEV_IO_PS_BASE, 0x40005090
 774              	.set CYDEV_IO_PS_SIZE, 0x00000010
 775              	.set CYDEV_IO_PS_PRT0_BASE, 0x40005090
 776              	.set CYDEV_IO_PS_PRT0_SIZE, 0x00000001
 777              	.set CYREG_PRT0_PS_ALIAS, 0x40005090
 778              	.set CYDEV_IO_PS_PRT1_BASE, 0x40005091
 779              	.set CYDEV_IO_PS_PRT1_SIZE, 0x00000001
 780              	.set CYREG_PRT1_PS_ALIAS, 0x40005091
 781              	.set CYDEV_IO_PS_PRT2_BASE, 0x40005092
 782              	.set CYDEV_IO_PS_PRT2_SIZE, 0x00000001
 783              	.set CYREG_PRT2_PS_ALIAS, 0x40005092
 784              	.set CYDEV_IO_PS_PRT3_BASE, 0x40005093
 785              	.set CYDEV_IO_PS_PRT3_SIZE, 0x00000001
 786              	.set CYREG_PRT3_PS_ALIAS, 0x40005093
 787              	.set CYDEV_IO_PS_PRT4_BASE, 0x40005094
 788              	.set CYDEV_IO_PS_PRT4_SIZE, 0x00000001
 789              	.set CYREG_PRT4_PS_ALIAS, 0x40005094
 790              	.set CYDEV_IO_PS_PRT5_BASE, 0x40005095
 791              	.set CYDEV_IO_PS_PRT5_SIZE, 0x00000001
 792              	.set CYREG_PRT5_PS_ALIAS, 0x40005095
 793              	.set CYDEV_IO_PS_PRT6_BASE, 0x40005096
 794              	.set CYDEV_IO_PS_PRT6_SIZE, 0x00000001
 795              	.set CYREG_PRT6_PS_ALIAS, 0x40005096
 796              	.set CYDEV_IO_PS_PRT12_BASE, 0x4000509c
 797              	.set CYDEV_IO_PS_PRT12_SIZE, 0x00000001
 798              	.set CYREG_PRT12_PS_ALIAS, 0x4000509c
 799              	.set CYDEV_IO_PS_PRT15_BASE, 0x4000509f
 800              	.set CYDEV_IO_PS_PRT15_SIZE, 0x00000001
 801              	.set CYREG_PRT15_PS15_ALIAS, 0x4000509f
 802              	.set CYDEV_IO_PRT_BASE, 0x40005100
 803              	.set CYDEV_IO_PRT_SIZE, 0x00000100
 804              	.set CYDEV_IO_PRT_PRT0_BASE, 0x40005100
 805              	.set CYDEV_IO_PRT_PRT0_SIZE, 0x00000010
 806              	.set CYREG_PRT0_DR, 0x40005100
 807              	.set CYREG_PRT0_PS, 0x40005101
 808              	.set CYREG_PRT0_DM0, 0x40005102
 809              	.set CYREG_PRT0_DM1, 0x40005103
 810              	.set CYREG_PRT0_DM2, 0x40005104
 811              	.set CYREG_PRT0_SLW, 0x40005105
 812              	.set CYREG_PRT0_BYP, 0x40005106
 813              	.set CYREG_PRT0_BIE, 0x40005107
 814              	.set CYREG_PRT0_INP_DIS, 0x40005108
 815              	.set CYREG_PRT0_CTL, 0x40005109
 816              	.set CYREG_PRT0_PRT, 0x4000510a
 817              	.set CYREG_PRT0_BIT_MASK, 0x4000510b
 818              	.set CYREG_PRT0_AMUX, 0x4000510c
 819              	.set CYREG_PRT0_AG, 0x4000510d
 820              	.set CYREG_PRT0_LCD_COM_SEG, 0x4000510e
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 110


 821              	.set CYREG_PRT0_LCD_EN, 0x4000510f
 822              	.set CYDEV_IO_PRT_PRT1_BASE, 0x40005110
 823              	.set CYDEV_IO_PRT_PRT1_SIZE, 0x00000010
 824              	.set CYREG_PRT1_DR, 0x40005110
 825              	.set CYREG_PRT1_PS, 0x40005111
 826              	.set CYREG_PRT1_DM0, 0x40005112
 827              	.set CYREG_PRT1_DM1, 0x40005113
 828              	.set CYREG_PRT1_DM2, 0x40005114
 829              	.set CYREG_PRT1_SLW, 0x40005115
 830              	.set CYREG_PRT1_BYP, 0x40005116
 831              	.set CYREG_PRT1_BIE, 0x40005117
 832              	.set CYREG_PRT1_INP_DIS, 0x40005118
 833              	.set CYREG_PRT1_CTL, 0x40005119
 834              	.set CYREG_PRT1_PRT, 0x4000511a
 835              	.set CYREG_PRT1_BIT_MASK, 0x4000511b
 836              	.set CYREG_PRT1_AMUX, 0x4000511c
 837              	.set CYREG_PRT1_AG, 0x4000511d
 838              	.set CYREG_PRT1_LCD_COM_SEG, 0x4000511e
 839              	.set CYREG_PRT1_LCD_EN, 0x4000511f
 840              	.set CYDEV_IO_PRT_PRT2_BASE, 0x40005120
 841              	.set CYDEV_IO_PRT_PRT2_SIZE, 0x00000010
 842              	.set CYREG_PRT2_DR, 0x40005120
 843              	.set CYREG_PRT2_PS, 0x40005121
 844              	.set CYREG_PRT2_DM0, 0x40005122
 845              	.set CYREG_PRT2_DM1, 0x40005123
 846              	.set CYREG_PRT2_DM2, 0x40005124
 847              	.set CYREG_PRT2_SLW, 0x40005125
 848              	.set CYREG_PRT2_BYP, 0x40005126
 849              	.set CYREG_PRT2_BIE, 0x40005127
 850              	.set CYREG_PRT2_INP_DIS, 0x40005128
 851              	.set CYREG_PRT2_CTL, 0x40005129
 852              	.set CYREG_PRT2_PRT, 0x4000512a
 853              	.set CYREG_PRT2_BIT_MASK, 0x4000512b
 854              	.set CYREG_PRT2_AMUX, 0x4000512c
 855              	.set CYREG_PRT2_AG, 0x4000512d
 856              	.set CYREG_PRT2_LCD_COM_SEG, 0x4000512e
 857              	.set CYREG_PRT2_LCD_EN, 0x4000512f
 858              	.set CYDEV_IO_PRT_PRT3_BASE, 0x40005130
 859              	.set CYDEV_IO_PRT_PRT3_SIZE, 0x00000010
 860              	.set CYREG_PRT3_DR, 0x40005130
 861              	.set CYREG_PRT3_PS, 0x40005131
 862              	.set CYREG_PRT3_DM0, 0x40005132
 863              	.set CYREG_PRT3_DM1, 0x40005133
 864              	.set CYREG_PRT3_DM2, 0x40005134
 865              	.set CYREG_PRT3_SLW, 0x40005135
 866              	.set CYREG_PRT3_BYP, 0x40005136
 867              	.set CYREG_PRT3_BIE, 0x40005137
 868              	.set CYREG_PRT3_INP_DIS, 0x40005138
 869              	.set CYREG_PRT3_CTL, 0x40005139
 870              	.set CYREG_PRT3_PRT, 0x4000513a
 871              	.set CYREG_PRT3_BIT_MASK, 0x4000513b
 872              	.set CYREG_PRT3_AMUX, 0x4000513c
 873              	.set CYREG_PRT3_AG, 0x4000513d
 874              	.set CYREG_PRT3_LCD_COM_SEG, 0x4000513e
 875              	.set CYREG_PRT3_LCD_EN, 0x4000513f
 876              	.set CYDEV_IO_PRT_PRT4_BASE, 0x40005140
 877              	.set CYDEV_IO_PRT_PRT4_SIZE, 0x00000010
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 111


 878              	.set CYREG_PRT4_DR, 0x40005140
 879              	.set CYREG_PRT4_PS, 0x40005141
 880              	.set CYREG_PRT4_DM0, 0x40005142
 881              	.set CYREG_PRT4_DM1, 0x40005143
 882              	.set CYREG_PRT4_DM2, 0x40005144
 883              	.set CYREG_PRT4_SLW, 0x40005145
 884              	.set CYREG_PRT4_BYP, 0x40005146
 885              	.set CYREG_PRT4_BIE, 0x40005147
 886              	.set CYREG_PRT4_INP_DIS, 0x40005148
 887              	.set CYREG_PRT4_CTL, 0x40005149
 888              	.set CYREG_PRT4_PRT, 0x4000514a
 889              	.set CYREG_PRT4_BIT_MASK, 0x4000514b
 890              	.set CYREG_PRT4_AMUX, 0x4000514c
 891              	.set CYREG_PRT4_AG, 0x4000514d
 892              	.set CYREG_PRT4_LCD_COM_SEG, 0x4000514e
 893              	.set CYREG_PRT4_LCD_EN, 0x4000514f
 894              	.set CYDEV_IO_PRT_PRT5_BASE, 0x40005150
 895              	.set CYDEV_IO_PRT_PRT5_SIZE, 0x00000010
 896              	.set CYREG_PRT5_DR, 0x40005150
 897              	.set CYREG_PRT5_PS, 0x40005151
 898              	.set CYREG_PRT5_DM0, 0x40005152
 899              	.set CYREG_PRT5_DM1, 0x40005153
 900              	.set CYREG_PRT5_DM2, 0x40005154
 901              	.set CYREG_PRT5_SLW, 0x40005155
 902              	.set CYREG_PRT5_BYP, 0x40005156
 903              	.set CYREG_PRT5_BIE, 0x40005157
 904              	.set CYREG_PRT5_INP_DIS, 0x40005158
 905              	.set CYREG_PRT5_CTL, 0x40005159
 906              	.set CYREG_PRT5_PRT, 0x4000515a
 907              	.set CYREG_PRT5_BIT_MASK, 0x4000515b
 908              	.set CYREG_PRT5_AMUX, 0x4000515c
 909              	.set CYREG_PRT5_AG, 0x4000515d
 910              	.set CYREG_PRT5_LCD_COM_SEG, 0x4000515e
 911              	.set CYREG_PRT5_LCD_EN, 0x4000515f
 912              	.set CYDEV_IO_PRT_PRT6_BASE, 0x40005160
 913              	.set CYDEV_IO_PRT_PRT6_SIZE, 0x00000010
 914              	.set CYREG_PRT6_DR, 0x40005160
 915              	.set CYREG_PRT6_PS, 0x40005161
 916              	.set CYREG_PRT6_DM0, 0x40005162
 917              	.set CYREG_PRT6_DM1, 0x40005163
 918              	.set CYREG_PRT6_DM2, 0x40005164
 919              	.set CYREG_PRT6_SLW, 0x40005165
 920              	.set CYREG_PRT6_BYP, 0x40005166
 921              	.set CYREG_PRT6_BIE, 0x40005167
 922              	.set CYREG_PRT6_INP_DIS, 0x40005168
 923              	.set CYREG_PRT6_CTL, 0x40005169
 924              	.set CYREG_PRT6_PRT, 0x4000516a
 925              	.set CYREG_PRT6_BIT_MASK, 0x4000516b
 926              	.set CYREG_PRT6_AMUX, 0x4000516c
 927              	.set CYREG_PRT6_AG, 0x4000516d
 928              	.set CYREG_PRT6_LCD_COM_SEG, 0x4000516e
 929              	.set CYREG_PRT6_LCD_EN, 0x4000516f
 930              	.set CYDEV_IO_PRT_PRT12_BASE, 0x400051c0
 931              	.set CYDEV_IO_PRT_PRT12_SIZE, 0x00000010
 932              	.set CYREG_PRT12_DR, 0x400051c0
 933              	.set CYREG_PRT12_PS, 0x400051c1
 934              	.set CYREG_PRT12_DM0, 0x400051c2
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 112


 935              	.set CYREG_PRT12_DM1, 0x400051c3
 936              	.set CYREG_PRT12_DM2, 0x400051c4
 937              	.set CYREG_PRT12_SLW, 0x400051c5
 938              	.set CYREG_PRT12_BYP, 0x400051c6
 939              	.set CYREG_PRT12_BIE, 0x400051c7
 940              	.set CYREG_PRT12_INP_DIS, 0x400051c8
 941              	.set CYREG_PRT12_SIO_HYST_EN, 0x400051c9
 942              	.set CYREG_PRT12_PRT, 0x400051ca
 943              	.set CYREG_PRT12_BIT_MASK, 0x400051cb
 944              	.set CYREG_PRT12_SIO_REG_HIFREQ, 0x400051cc
 945              	.set CYREG_PRT12_AG, 0x400051cd
 946              	.set CYREG_PRT12_SIO_CFG, 0x400051ce
 947              	.set CYREG_PRT12_SIO_DIFF, 0x400051cf
 948              	.set CYDEV_IO_PRT_PRT15_BASE, 0x400051f0
 949              	.set CYDEV_IO_PRT_PRT15_SIZE, 0x00000010
 950              	.set CYREG_PRT15_DR, 0x400051f0
 951              	.set CYREG_PRT15_PS, 0x400051f1
 952              	.set CYREG_PRT15_DM0, 0x400051f2
 953              	.set CYREG_PRT15_DM1, 0x400051f3
 954              	.set CYREG_PRT15_DM2, 0x400051f4
 955              	.set CYREG_PRT15_SLW, 0x400051f5
 956              	.set CYREG_PRT15_BYP, 0x400051f6
 957              	.set CYREG_PRT15_BIE, 0x400051f7
 958              	.set CYREG_PRT15_INP_DIS, 0x400051f8
 959              	.set CYREG_PRT15_CTL, 0x400051f9
 960              	.set CYREG_PRT15_PRT, 0x400051fa
 961              	.set CYREG_PRT15_BIT_MASK, 0x400051fb
 962              	.set CYREG_PRT15_AMUX, 0x400051fc
 963              	.set CYREG_PRT15_AG, 0x400051fd
 964              	.set CYREG_PRT15_LCD_COM_SEG, 0x400051fe
 965              	.set CYREG_PRT15_LCD_EN, 0x400051ff
 966              	.set CYDEV_PRTDSI_BASE, 0x40005200
 967              	.set CYDEV_PRTDSI_SIZE, 0x0000007f
 968              	.set CYDEV_PRTDSI_PRT0_BASE, 0x40005200
 969              	.set CYDEV_PRTDSI_PRT0_SIZE, 0x00000007
 970              	.set CYREG_PRT0_OUT_SEL0, 0x40005200
 971              	.set CYREG_PRT0_OUT_SEL1, 0x40005201
 972              	.set CYREG_PRT0_OE_SEL0, 0x40005202
 973              	.set CYREG_PRT0_OE_SEL1, 0x40005203
 974              	.set CYREG_PRT0_DBL_SYNC_IN, 0x40005204
 975              	.set CYREG_PRT0_SYNC_OUT, 0x40005205
 976              	.set CYREG_PRT0_CAPS_SEL, 0x40005206
 977              	.set CYDEV_PRTDSI_PRT1_BASE, 0x40005208
 978              	.set CYDEV_PRTDSI_PRT1_SIZE, 0x00000007
 979              	.set CYREG_PRT1_OUT_SEL0, 0x40005208
 980              	.set CYREG_PRT1_OUT_SEL1, 0x40005209
 981              	.set CYREG_PRT1_OE_SEL0, 0x4000520a
 982              	.set CYREG_PRT1_OE_SEL1, 0x4000520b
 983              	.set CYREG_PRT1_DBL_SYNC_IN, 0x4000520c
 984              	.set CYREG_PRT1_SYNC_OUT, 0x4000520d
 985              	.set CYREG_PRT1_CAPS_SEL, 0x4000520e
 986              	.set CYDEV_PRTDSI_PRT2_BASE, 0x40005210
 987              	.set CYDEV_PRTDSI_PRT2_SIZE, 0x00000007
 988              	.set CYREG_PRT2_OUT_SEL0, 0x40005210
 989              	.set CYREG_PRT2_OUT_SEL1, 0x40005211
 990              	.set CYREG_PRT2_OE_SEL0, 0x40005212
 991              	.set CYREG_PRT2_OE_SEL1, 0x40005213
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 113


 992              	.set CYREG_PRT2_DBL_SYNC_IN, 0x40005214
 993              	.set CYREG_PRT2_SYNC_OUT, 0x40005215
 994              	.set CYREG_PRT2_CAPS_SEL, 0x40005216
 995              	.set CYDEV_PRTDSI_PRT3_BASE, 0x40005218
 996              	.set CYDEV_PRTDSI_PRT3_SIZE, 0x00000007
 997              	.set CYREG_PRT3_OUT_SEL0, 0x40005218
 998              	.set CYREG_PRT3_OUT_SEL1, 0x40005219
 999              	.set CYREG_PRT3_OE_SEL0, 0x4000521a
 1000              	.set CYREG_PRT3_OE_SEL1, 0x4000521b
 1001              	.set CYREG_PRT3_DBL_SYNC_IN, 0x4000521c
 1002              	.set CYREG_PRT3_SYNC_OUT, 0x4000521d
 1003              	.set CYREG_PRT3_CAPS_SEL, 0x4000521e
 1004              	.set CYDEV_PRTDSI_PRT4_BASE, 0x40005220
 1005              	.set CYDEV_PRTDSI_PRT4_SIZE, 0x00000007
 1006              	.set CYREG_PRT4_OUT_SEL0, 0x40005220
 1007              	.set CYREG_PRT4_OUT_SEL1, 0x40005221
 1008              	.set CYREG_PRT4_OE_SEL0, 0x40005222
 1009              	.set CYREG_PRT4_OE_SEL1, 0x40005223
 1010              	.set CYREG_PRT4_DBL_SYNC_IN, 0x40005224
 1011              	.set CYREG_PRT4_SYNC_OUT, 0x40005225
 1012              	.set CYREG_PRT4_CAPS_SEL, 0x40005226
 1013              	.set CYDEV_PRTDSI_PRT5_BASE, 0x40005228
 1014              	.set CYDEV_PRTDSI_PRT5_SIZE, 0x00000007
 1015              	.set CYREG_PRT5_OUT_SEL0, 0x40005228
 1016              	.set CYREG_PRT5_OUT_SEL1, 0x40005229
 1017              	.set CYREG_PRT5_OE_SEL0, 0x4000522a
 1018              	.set CYREG_PRT5_OE_SEL1, 0x4000522b
 1019              	.set CYREG_PRT5_DBL_SYNC_IN, 0x4000522c
 1020              	.set CYREG_PRT5_SYNC_OUT, 0x4000522d
 1021              	.set CYREG_PRT5_CAPS_SEL, 0x4000522e
 1022              	.set CYDEV_PRTDSI_PRT6_BASE, 0x40005230
 1023              	.set CYDEV_PRTDSI_PRT6_SIZE, 0x00000007
 1024              	.set CYREG_PRT6_OUT_SEL0, 0x40005230
 1025              	.set CYREG_PRT6_OUT_SEL1, 0x40005231
 1026              	.set CYREG_PRT6_OE_SEL0, 0x40005232
 1027              	.set CYREG_PRT6_OE_SEL1, 0x40005233
 1028              	.set CYREG_PRT6_DBL_SYNC_IN, 0x40005234
 1029              	.set CYREG_PRT6_SYNC_OUT, 0x40005235
 1030              	.set CYREG_PRT6_CAPS_SEL, 0x40005236
 1031              	.set CYDEV_PRTDSI_PRT12_BASE, 0x40005260
 1032              	.set CYDEV_PRTDSI_PRT12_SIZE, 0x00000006
 1033              	.set CYREG_PRT12_OUT_SEL0, 0x40005260
 1034              	.set CYREG_PRT12_OUT_SEL1, 0x40005261
 1035              	.set CYREG_PRT12_OE_SEL0, 0x40005262
 1036              	.set CYREG_PRT12_OE_SEL1, 0x40005263
 1037              	.set CYREG_PRT12_DBL_SYNC_IN, 0x40005264
 1038              	.set CYREG_PRT12_SYNC_OUT, 0x40005265
 1039              	.set CYDEV_PRTDSI_PRT15_BASE, 0x40005278
 1040              	.set CYDEV_PRTDSI_PRT15_SIZE, 0x00000007
 1041              	.set CYREG_PRT15_OUT_SEL0, 0x40005278
 1042              	.set CYREG_PRT15_OUT_SEL1, 0x40005279
 1043              	.set CYREG_PRT15_OE_SEL0, 0x4000527a
 1044              	.set CYREG_PRT15_OE_SEL1, 0x4000527b
 1045              	.set CYREG_PRT15_DBL_SYNC_IN, 0x4000527c
 1046              	.set CYREG_PRT15_SYNC_OUT, 0x4000527d
 1047              	.set CYREG_PRT15_CAPS_SEL, 0x4000527e
 1048              	.set CYDEV_EMIF_BASE, 0x40005400
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 114


 1049              	.set CYDEV_EMIF_SIZE, 0x00000007
 1050              	.set CYREG_EMIF_NO_UDB, 0x40005400
 1051              	.set CYREG_EMIF_RP_WAIT_STATES, 0x40005401
 1052              	.set CYREG_EMIF_MEM_DWN, 0x40005402
 1053              	.set CYREG_EMIF_MEMCLK_DIV, 0x40005403
 1054              	.set CYREG_EMIF_CLOCK_EN, 0x40005404
 1055              	.set CYREG_EMIF_EM_TYPE, 0x40005405
 1056              	.set CYREG_EMIF_WP_WAIT_STATES, 0x40005406
 1057              	.set CYDEV_ANAIF_BASE, 0x40005800
 1058              	.set CYDEV_ANAIF_SIZE, 0x000003a9
 1059              	.set CYDEV_ANAIF_CFG_BASE, 0x40005800
 1060              	.set CYDEV_ANAIF_CFG_SIZE, 0x0000010f
 1061              	.set CYDEV_ANAIF_CFG_SC0_BASE, 0x40005800
 1062              	.set CYDEV_ANAIF_CFG_SC0_SIZE, 0x00000003
 1063              	.set CYREG_SC0_CR0, 0x40005800
 1064              	.set CYREG_SC0_CR1, 0x40005801
 1065              	.set CYREG_SC0_CR2, 0x40005802
 1066              	.set CYDEV_ANAIF_CFG_SC1_BASE, 0x40005804
 1067              	.set CYDEV_ANAIF_CFG_SC1_SIZE, 0x00000003
 1068              	.set CYREG_SC1_CR0, 0x40005804
 1069              	.set CYREG_SC1_CR1, 0x40005805
 1070              	.set CYREG_SC1_CR2, 0x40005806
 1071              	.set CYDEV_ANAIF_CFG_SC2_BASE, 0x40005808
 1072              	.set CYDEV_ANAIF_CFG_SC2_SIZE, 0x00000003
 1073              	.set CYREG_SC2_CR0, 0x40005808
 1074              	.set CYREG_SC2_CR1, 0x40005809
 1075              	.set CYREG_SC2_CR2, 0x4000580a
 1076              	.set CYDEV_ANAIF_CFG_SC3_BASE, 0x4000580c
 1077              	.set CYDEV_ANAIF_CFG_SC3_SIZE, 0x00000003
 1078              	.set CYREG_SC3_CR0, 0x4000580c
 1079              	.set CYREG_SC3_CR1, 0x4000580d
 1080              	.set CYREG_SC3_CR2, 0x4000580e
 1081              	.set CYDEV_ANAIF_CFG_DAC0_BASE, 0x40005820
 1082              	.set CYDEV_ANAIF_CFG_DAC0_SIZE, 0x00000003
 1083              	.set CYREG_DAC0_CR0, 0x40005820
 1084              	.set CYREG_DAC0_CR1, 0x40005821
 1085              	.set CYREG_DAC0_TST, 0x40005822
 1086              	.set CYDEV_ANAIF_CFG_DAC1_BASE, 0x40005824
 1087              	.set CYDEV_ANAIF_CFG_DAC1_SIZE, 0x00000003
 1088              	.set CYREG_DAC1_CR0, 0x40005824
 1089              	.set CYREG_DAC1_CR1, 0x40005825
 1090              	.set CYREG_DAC1_TST, 0x40005826
 1091              	.set CYDEV_ANAIF_CFG_DAC2_BASE, 0x40005828
 1092              	.set CYDEV_ANAIF_CFG_DAC2_SIZE, 0x00000003
 1093              	.set CYREG_DAC2_CR0, 0x40005828
 1094              	.set CYREG_DAC2_CR1, 0x40005829
 1095              	.set CYREG_DAC2_TST, 0x4000582a
 1096              	.set CYDEV_ANAIF_CFG_DAC3_BASE, 0x4000582c
 1097              	.set CYDEV_ANAIF_CFG_DAC3_SIZE, 0x00000003
 1098              	.set CYREG_DAC3_CR0, 0x4000582c
 1099              	.set CYREG_DAC3_CR1, 0x4000582d
 1100              	.set CYREG_DAC3_TST, 0x4000582e
 1101              	.set CYDEV_ANAIF_CFG_CMP0_BASE, 0x40005840
 1102              	.set CYDEV_ANAIF_CFG_CMP0_SIZE, 0x00000001
 1103              	.set CYREG_CMP0_CR, 0x40005840
 1104              	.set CYDEV_ANAIF_CFG_CMP1_BASE, 0x40005841
 1105              	.set CYDEV_ANAIF_CFG_CMP1_SIZE, 0x00000001
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 115


 1106              	.set CYREG_CMP1_CR, 0x40005841
 1107              	.set CYDEV_ANAIF_CFG_CMP2_BASE, 0x40005842
 1108              	.set CYDEV_ANAIF_CFG_CMP2_SIZE, 0x00000001
 1109              	.set CYREG_CMP2_CR, 0x40005842
 1110              	.set CYDEV_ANAIF_CFG_CMP3_BASE, 0x40005843
 1111              	.set CYDEV_ANAIF_CFG_CMP3_SIZE, 0x00000001
 1112              	.set CYREG_CMP3_CR, 0x40005843
 1113              	.set CYDEV_ANAIF_CFG_LUT0_BASE, 0x40005848
 1114              	.set CYDEV_ANAIF_CFG_LUT0_SIZE, 0x00000002
 1115              	.set CYREG_LUT0_CR, 0x40005848
 1116              	.set CYREG_LUT0_MX, 0x40005849
 1117              	.set CYDEV_ANAIF_CFG_LUT1_BASE, 0x4000584a
 1118              	.set CYDEV_ANAIF_CFG_LUT1_SIZE, 0x00000002
 1119              	.set CYREG_LUT1_CR, 0x4000584a
 1120              	.set CYREG_LUT1_MX, 0x4000584b
 1121              	.set CYDEV_ANAIF_CFG_LUT2_BASE, 0x4000584c
 1122              	.set CYDEV_ANAIF_CFG_LUT2_SIZE, 0x00000002
 1123              	.set CYREG_LUT2_CR, 0x4000584c
 1124              	.set CYREG_LUT2_MX, 0x4000584d
 1125              	.set CYDEV_ANAIF_CFG_LUT3_BASE, 0x4000584e
 1126              	.set CYDEV_ANAIF_CFG_LUT3_SIZE, 0x00000002
 1127              	.set CYREG_LUT3_CR, 0x4000584e
 1128              	.set CYREG_LUT3_MX, 0x4000584f
 1129              	.set CYDEV_ANAIF_CFG_OPAMP0_BASE, 0x40005858
 1130              	.set CYDEV_ANAIF_CFG_OPAMP0_SIZE, 0x00000002
 1131              	.set CYREG_OPAMP0_CR, 0x40005858
 1132              	.set CYREG_OPAMP0_RSVD, 0x40005859
 1133              	.set CYDEV_ANAIF_CFG_OPAMP1_BASE, 0x4000585a
 1134              	.set CYDEV_ANAIF_CFG_OPAMP1_SIZE, 0x00000002
 1135              	.set CYREG_OPAMP1_CR, 0x4000585a
 1136              	.set CYREG_OPAMP1_RSVD, 0x4000585b
 1137              	.set CYDEV_ANAIF_CFG_OPAMP2_BASE, 0x4000585c
 1138              	.set CYDEV_ANAIF_CFG_OPAMP2_SIZE, 0x00000002
 1139              	.set CYREG_OPAMP2_CR, 0x4000585c
 1140              	.set CYREG_OPAMP2_RSVD, 0x4000585d
 1141              	.set CYDEV_ANAIF_CFG_OPAMP3_BASE, 0x4000585e
 1142              	.set CYDEV_ANAIF_CFG_OPAMP3_SIZE, 0x00000002
 1143              	.set CYREG_OPAMP3_CR, 0x4000585e
 1144              	.set CYREG_OPAMP3_RSVD, 0x4000585f
 1145              	.set CYDEV_ANAIF_CFG_LCDDAC_BASE, 0x40005868
 1146              	.set CYDEV_ANAIF_CFG_LCDDAC_SIZE, 0x00000002
 1147              	.set CYREG_LCDDAC_CR0, 0x40005868
 1148              	.set CYREG_LCDDAC_CR1, 0x40005869
 1149              	.set CYDEV_ANAIF_CFG_LCDDRV_BASE, 0x4000586a
 1150              	.set CYDEV_ANAIF_CFG_LCDDRV_SIZE, 0x00000001
 1151              	.set CYREG_LCDDRV_CR, 0x4000586a
 1152              	.set CYDEV_ANAIF_CFG_LCDTMR_BASE, 0x4000586b
 1153              	.set CYDEV_ANAIF_CFG_LCDTMR_SIZE, 0x00000001
 1154              	.set CYREG_LCDTMR_CFG, 0x4000586b
 1155              	.set CYDEV_ANAIF_CFG_BG_BASE, 0x4000586c
 1156              	.set CYDEV_ANAIF_CFG_BG_SIZE, 0x00000004
 1157              	.set CYREG_BG_CR0, 0x4000586c
 1158              	.set CYREG_BG_RSVD, 0x4000586d
 1159              	.set CYREG_BG_DFT0, 0x4000586e
 1160              	.set CYREG_BG_DFT1, 0x4000586f
 1161              	.set CYDEV_ANAIF_CFG_CAPSL_BASE, 0x40005870
 1162              	.set CYDEV_ANAIF_CFG_CAPSL_SIZE, 0x00000002
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 116


 1163              	.set CYREG_CAPSL_CFG0, 0x40005870
 1164              	.set CYREG_CAPSL_CFG1, 0x40005871
 1165              	.set CYDEV_ANAIF_CFG_CAPSR_BASE, 0x40005872
 1166              	.set CYDEV_ANAIF_CFG_CAPSR_SIZE, 0x00000002
 1167              	.set CYREG_CAPSR_CFG0, 0x40005872
 1168              	.set CYREG_CAPSR_CFG1, 0x40005873
 1169              	.set CYDEV_ANAIF_CFG_PUMP_BASE, 0x40005876
 1170              	.set CYDEV_ANAIF_CFG_PUMP_SIZE, 0x00000002
 1171              	.set CYREG_PUMP_CR0, 0x40005876
 1172              	.set CYREG_PUMP_CR1, 0x40005877
 1173              	.set CYDEV_ANAIF_CFG_LPF0_BASE, 0x40005878
 1174              	.set CYDEV_ANAIF_CFG_LPF0_SIZE, 0x00000002
 1175              	.set CYREG_LPF0_CR0, 0x40005878
 1176              	.set CYREG_LPF0_RSVD, 0x40005879
 1177              	.set CYDEV_ANAIF_CFG_LPF1_BASE, 0x4000587a
 1178              	.set CYDEV_ANAIF_CFG_LPF1_SIZE, 0x00000002
 1179              	.set CYREG_LPF1_CR0, 0x4000587a
 1180              	.set CYREG_LPF1_RSVD, 0x4000587b
 1181              	.set CYDEV_ANAIF_CFG_MISC_BASE, 0x4000587c
 1182              	.set CYDEV_ANAIF_CFG_MISC_SIZE, 0x00000001
 1183              	.set CYREG_ANAIF_CFG_MISC_CR0, 0x4000587c
 1184              	.set CYDEV_ANAIF_CFG_DSM0_BASE, 0x40005880
 1185              	.set CYDEV_ANAIF_CFG_DSM0_SIZE, 0x00000020
 1186              	.set CYREG_DSM0_CR0, 0x40005880
 1187              	.set CYREG_DSM0_CR1, 0x40005881
 1188              	.set CYREG_DSM0_CR2, 0x40005882
 1189              	.set CYREG_DSM0_CR3, 0x40005883
 1190              	.set CYREG_DSM0_CR4, 0x40005884
 1191              	.set CYREG_DSM0_CR5, 0x40005885
 1192              	.set CYREG_DSM0_CR6, 0x40005886
 1193              	.set CYREG_DSM0_CR7, 0x40005887
 1194              	.set CYREG_DSM0_CR8, 0x40005888
 1195              	.set CYREG_DSM0_CR9, 0x40005889
 1196              	.set CYREG_DSM0_CR10, 0x4000588a
 1197              	.set CYREG_DSM0_CR11, 0x4000588b
 1198              	.set CYREG_DSM0_CR12, 0x4000588c
 1199              	.set CYREG_DSM0_CR13, 0x4000588d
 1200              	.set CYREG_DSM0_CR14, 0x4000588e
 1201              	.set CYREG_DSM0_CR15, 0x4000588f
 1202              	.set CYREG_DSM0_CR16, 0x40005890
 1203              	.set CYREG_DSM0_CR17, 0x40005891
 1204              	.set CYREG_DSM0_REF0, 0x40005892
 1205              	.set CYREG_DSM0_REF1, 0x40005893
 1206              	.set CYREG_DSM0_REF2, 0x40005894
 1207              	.set CYREG_DSM0_REF3, 0x40005895
 1208              	.set CYREG_DSM0_DEM0, 0x40005896
 1209              	.set CYREG_DSM0_DEM1, 0x40005897
 1210              	.set CYREG_DSM0_TST0, 0x40005898
 1211              	.set CYREG_DSM0_TST1, 0x40005899
 1212              	.set CYREG_DSM0_BUF0, 0x4000589a
 1213              	.set CYREG_DSM0_BUF1, 0x4000589b
 1214              	.set CYREG_DSM0_BUF2, 0x4000589c
 1215              	.set CYREG_DSM0_BUF3, 0x4000589d
 1216              	.set CYREG_DSM0_MISC, 0x4000589e
 1217              	.set CYREG_DSM0_RSVD1, 0x4000589f
 1218              	.set CYDEV_ANAIF_CFG_SAR0_BASE, 0x40005900
 1219              	.set CYDEV_ANAIF_CFG_SAR0_SIZE, 0x00000007
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 117


 1220              	.set CYREG_SAR0_CSR0, 0x40005900
 1221              	.set CYREG_SAR0_CSR1, 0x40005901
 1222              	.set CYREG_SAR0_CSR2, 0x40005902
 1223              	.set CYREG_SAR0_CSR3, 0x40005903
 1224              	.set CYREG_SAR0_CSR4, 0x40005904
 1225              	.set CYREG_SAR0_CSR5, 0x40005905
 1226              	.set CYREG_SAR0_CSR6, 0x40005906
 1227              	.set CYDEV_ANAIF_CFG_SAR1_BASE, 0x40005908
 1228              	.set CYDEV_ANAIF_CFG_SAR1_SIZE, 0x00000007
 1229              	.set CYREG_SAR1_CSR0, 0x40005908
 1230              	.set CYREG_SAR1_CSR1, 0x40005909
 1231              	.set CYREG_SAR1_CSR2, 0x4000590a
 1232              	.set CYREG_SAR1_CSR3, 0x4000590b
 1233              	.set CYREG_SAR1_CSR4, 0x4000590c
 1234              	.set CYREG_SAR1_CSR5, 0x4000590d
 1235              	.set CYREG_SAR1_CSR6, 0x4000590e
 1236              	.set CYDEV_ANAIF_RT_BASE, 0x40005a00
 1237              	.set CYDEV_ANAIF_RT_SIZE, 0x00000162
 1238              	.set CYDEV_ANAIF_RT_SC0_BASE, 0x40005a00
 1239              	.set CYDEV_ANAIF_RT_SC0_SIZE, 0x0000000d
 1240              	.set CYREG_SC0_SW0, 0x40005a00
 1241              	.set CYREG_SC0_SW2, 0x40005a02
 1242              	.set CYREG_SC0_SW3, 0x40005a03
 1243              	.set CYREG_SC0_SW4, 0x40005a04
 1244              	.set CYREG_SC0_SW6, 0x40005a06
 1245              	.set CYREG_SC0_SW7, 0x40005a07
 1246              	.set CYREG_SC0_SW8, 0x40005a08
 1247              	.set CYREG_SC0_SW10, 0x40005a0a
 1248              	.set CYREG_SC0_CLK, 0x40005a0b
 1249              	.set CYREG_SC0_BST, 0x40005a0c
 1250              	.set CYDEV_ANAIF_RT_SC1_BASE, 0x40005a10
 1251              	.set CYDEV_ANAIF_RT_SC1_SIZE, 0x0000000d
 1252              	.set CYREG_SC1_SW0, 0x40005a10
 1253              	.set CYREG_SC1_SW2, 0x40005a12
 1254              	.set CYREG_SC1_SW3, 0x40005a13
 1255              	.set CYREG_SC1_SW4, 0x40005a14
 1256              	.set CYREG_SC1_SW6, 0x40005a16
 1257              	.set CYREG_SC1_SW7, 0x40005a17
 1258              	.set CYREG_SC1_SW8, 0x40005a18
 1259              	.set CYREG_SC1_SW10, 0x40005a1a
 1260              	.set CYREG_SC1_CLK, 0x40005a1b
 1261              	.set CYREG_SC1_BST, 0x40005a1c
 1262              	.set CYDEV_ANAIF_RT_SC2_BASE, 0x40005a20
 1263              	.set CYDEV_ANAIF_RT_SC2_SIZE, 0x0000000d
 1264              	.set CYREG_SC2_SW0, 0x40005a20
 1265              	.set CYREG_SC2_SW2, 0x40005a22
 1266              	.set CYREG_SC2_SW3, 0x40005a23
 1267              	.set CYREG_SC2_SW4, 0x40005a24
 1268              	.set CYREG_SC2_SW6, 0x40005a26
 1269              	.set CYREG_SC2_SW7, 0x40005a27
 1270              	.set CYREG_SC2_SW8, 0x40005a28
 1271              	.set CYREG_SC2_SW10, 0x40005a2a
 1272              	.set CYREG_SC2_CLK, 0x40005a2b
 1273              	.set CYREG_SC2_BST, 0x40005a2c
 1274              	.set CYDEV_ANAIF_RT_SC3_BASE, 0x40005a30
 1275              	.set CYDEV_ANAIF_RT_SC3_SIZE, 0x0000000d
 1276              	.set CYREG_SC3_SW0, 0x40005a30
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 118


 1277              	.set CYREG_SC3_SW2, 0x40005a32
 1278              	.set CYREG_SC3_SW3, 0x40005a33
 1279              	.set CYREG_SC3_SW4, 0x40005a34
 1280              	.set CYREG_SC3_SW6, 0x40005a36
 1281              	.set CYREG_SC3_SW7, 0x40005a37
 1282              	.set CYREG_SC3_SW8, 0x40005a38
 1283              	.set CYREG_SC3_SW10, 0x40005a3a
 1284              	.set CYREG_SC3_CLK, 0x40005a3b
 1285              	.set CYREG_SC3_BST, 0x40005a3c
 1286              	.set CYDEV_ANAIF_RT_DAC0_BASE, 0x40005a80
 1287              	.set CYDEV_ANAIF_RT_DAC0_SIZE, 0x00000008
 1288              	.set CYREG_DAC0_SW0, 0x40005a80
 1289              	.set CYREG_DAC0_SW2, 0x40005a82
 1290              	.set CYREG_DAC0_SW3, 0x40005a83
 1291              	.set CYREG_DAC0_SW4, 0x40005a84
 1292              	.set CYREG_DAC0_STROBE, 0x40005a87
 1293              	.set CYDEV_ANAIF_RT_DAC1_BASE, 0x40005a88
 1294              	.set CYDEV_ANAIF_RT_DAC1_SIZE, 0x00000008
 1295              	.set CYREG_DAC1_SW0, 0x40005a88
 1296              	.set CYREG_DAC1_SW2, 0x40005a8a
 1297              	.set CYREG_DAC1_SW3, 0x40005a8b
 1298              	.set CYREG_DAC1_SW4, 0x40005a8c
 1299              	.set CYREG_DAC1_STROBE, 0x40005a8f
 1300              	.set CYDEV_ANAIF_RT_DAC2_BASE, 0x40005a90
 1301              	.set CYDEV_ANAIF_RT_DAC2_SIZE, 0x00000008
 1302              	.set CYREG_DAC2_SW0, 0x40005a90
 1303              	.set CYREG_DAC2_SW2, 0x40005a92
 1304              	.set CYREG_DAC2_SW3, 0x40005a93
 1305              	.set CYREG_DAC2_SW4, 0x40005a94
 1306              	.set CYREG_DAC2_STROBE, 0x40005a97
 1307              	.set CYDEV_ANAIF_RT_DAC3_BASE, 0x40005a98
 1308              	.set CYDEV_ANAIF_RT_DAC3_SIZE, 0x00000008
 1309              	.set CYREG_DAC3_SW0, 0x40005a98
 1310              	.set CYREG_DAC3_SW2, 0x40005a9a
 1311              	.set CYREG_DAC3_SW3, 0x40005a9b
 1312              	.set CYREG_DAC3_SW4, 0x40005a9c
 1313              	.set CYREG_DAC3_STROBE, 0x40005a9f
 1314              	.set CYDEV_ANAIF_RT_CMP0_BASE, 0x40005ac0
 1315              	.set CYDEV_ANAIF_RT_CMP0_SIZE, 0x00000008
 1316              	.set CYREG_CMP0_SW0, 0x40005ac0
 1317              	.set CYREG_CMP0_SW2, 0x40005ac2
 1318              	.set CYREG_CMP0_SW3, 0x40005ac3
 1319              	.set CYREG_CMP0_SW4, 0x40005ac4
 1320              	.set CYREG_CMP0_SW6, 0x40005ac6
 1321              	.set CYREG_CMP0_CLK, 0x40005ac7
 1322              	.set CYDEV_ANAIF_RT_CMP1_BASE, 0x40005ac8
 1323              	.set CYDEV_ANAIF_RT_CMP1_SIZE, 0x00000008
 1324              	.set CYREG_CMP1_SW0, 0x40005ac8
 1325              	.set CYREG_CMP1_SW2, 0x40005aca
 1326              	.set CYREG_CMP1_SW3, 0x40005acb
 1327              	.set CYREG_CMP1_SW4, 0x40005acc
 1328              	.set CYREG_CMP1_SW6, 0x40005ace
 1329              	.set CYREG_CMP1_CLK, 0x40005acf
 1330              	.set CYDEV_ANAIF_RT_CMP2_BASE, 0x40005ad0
 1331              	.set CYDEV_ANAIF_RT_CMP2_SIZE, 0x00000008
 1332              	.set CYREG_CMP2_SW0, 0x40005ad0
 1333              	.set CYREG_CMP2_SW2, 0x40005ad2
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 119


 1334              	.set CYREG_CMP2_SW3, 0x40005ad3
 1335              	.set CYREG_CMP2_SW4, 0x40005ad4
 1336              	.set CYREG_CMP2_SW6, 0x40005ad6
 1337              	.set CYREG_CMP2_CLK, 0x40005ad7
 1338              	.set CYDEV_ANAIF_RT_CMP3_BASE, 0x40005ad8
 1339              	.set CYDEV_ANAIF_RT_CMP3_SIZE, 0x00000008
 1340              	.set CYREG_CMP3_SW0, 0x40005ad8
 1341              	.set CYREG_CMP3_SW2, 0x40005ada
 1342              	.set CYREG_CMP3_SW3, 0x40005adb
 1343              	.set CYREG_CMP3_SW4, 0x40005adc
 1344              	.set CYREG_CMP3_SW6, 0x40005ade
 1345              	.set CYREG_CMP3_CLK, 0x40005adf
 1346              	.set CYDEV_ANAIF_RT_DSM0_BASE, 0x40005b00
 1347              	.set CYDEV_ANAIF_RT_DSM0_SIZE, 0x00000008
 1348              	.set CYREG_DSM0_SW0, 0x40005b00
 1349              	.set CYREG_DSM0_SW2, 0x40005b02
 1350              	.set CYREG_DSM0_SW3, 0x40005b03
 1351              	.set CYREG_DSM0_SW4, 0x40005b04
 1352              	.set CYREG_DSM0_SW6, 0x40005b06
 1353              	.set CYREG_DSM0_CLK, 0x40005b07
 1354              	.set CYDEV_ANAIF_RT_SAR0_BASE, 0x40005b20
 1355              	.set CYDEV_ANAIF_RT_SAR0_SIZE, 0x00000008
 1356              	.set CYREG_SAR0_SW0, 0x40005b20
 1357              	.set CYREG_SAR0_SW2, 0x40005b22
 1358              	.set CYREG_SAR0_SW3, 0x40005b23
 1359              	.set CYREG_SAR0_SW4, 0x40005b24
 1360              	.set CYREG_SAR0_SW6, 0x40005b26
 1361              	.set CYREG_SAR0_CLK, 0x40005b27
 1362              	.set CYDEV_ANAIF_RT_SAR1_BASE, 0x40005b28
 1363              	.set CYDEV_ANAIF_RT_SAR1_SIZE, 0x00000008
 1364              	.set CYREG_SAR1_SW0, 0x40005b28
 1365              	.set CYREG_SAR1_SW2, 0x40005b2a
 1366              	.set CYREG_SAR1_SW3, 0x40005b2b
 1367              	.set CYREG_SAR1_SW4, 0x40005b2c
 1368              	.set CYREG_SAR1_SW6, 0x40005b2e
 1369              	.set CYREG_SAR1_CLK, 0x40005b2f
 1370              	.set CYDEV_ANAIF_RT_OPAMP0_BASE, 0x40005b40
 1371              	.set CYDEV_ANAIF_RT_OPAMP0_SIZE, 0x00000002
 1372              	.set CYREG_OPAMP0_MX, 0x40005b40
 1373              	.set CYREG_OPAMP0_SW, 0x40005b41
 1374              	.set CYDEV_ANAIF_RT_OPAMP1_BASE, 0x40005b42
 1375              	.set CYDEV_ANAIF_RT_OPAMP1_SIZE, 0x00000002
 1376              	.set CYREG_OPAMP1_MX, 0x40005b42
 1377              	.set CYREG_OPAMP1_SW, 0x40005b43
 1378              	.set CYDEV_ANAIF_RT_OPAMP2_BASE, 0x40005b44
 1379              	.set CYDEV_ANAIF_RT_OPAMP2_SIZE, 0x00000002
 1380              	.set CYREG_OPAMP2_MX, 0x40005b44
 1381              	.set CYREG_OPAMP2_SW, 0x40005b45
 1382              	.set CYDEV_ANAIF_RT_OPAMP3_BASE, 0x40005b46
 1383              	.set CYDEV_ANAIF_RT_OPAMP3_SIZE, 0x00000002
 1384              	.set CYREG_OPAMP3_MX, 0x40005b46
 1385              	.set CYREG_OPAMP3_SW, 0x40005b47
 1386              	.set CYDEV_ANAIF_RT_LCDDAC_BASE, 0x40005b50
 1387              	.set CYDEV_ANAIF_RT_LCDDAC_SIZE, 0x00000005
 1388              	.set CYREG_LCDDAC_SW0, 0x40005b50
 1389              	.set CYREG_LCDDAC_SW1, 0x40005b51
 1390              	.set CYREG_LCDDAC_SW2, 0x40005b52
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 120


 1391              	.set CYREG_LCDDAC_SW3, 0x40005b53
 1392              	.set CYREG_LCDDAC_SW4, 0x40005b54
 1393              	.set CYDEV_ANAIF_RT_SC_BASE, 0x40005b56
 1394              	.set CYDEV_ANAIF_RT_SC_SIZE, 0x00000001
 1395              	.set CYREG_SC_MISC, 0x40005b56
 1396              	.set CYDEV_ANAIF_RT_BUS_BASE, 0x40005b58
 1397              	.set CYDEV_ANAIF_RT_BUS_SIZE, 0x00000004
 1398              	.set CYREG_BUS_SW0, 0x40005b58
 1399              	.set CYREG_BUS_SW2, 0x40005b5a
 1400              	.set CYREG_BUS_SW3, 0x40005b5b
 1401              	.set CYDEV_ANAIF_RT_DFT_BASE, 0x40005b5c
 1402              	.set CYDEV_ANAIF_RT_DFT_SIZE, 0x00000006
 1403              	.set CYREG_DFT_CR0, 0x40005b5c
 1404              	.set CYREG_DFT_CR1, 0x40005b5d
 1405              	.set CYREG_DFT_CR2, 0x40005b5e
 1406              	.set CYREG_DFT_CR3, 0x40005b5f
 1407              	.set CYREG_DFT_CR4, 0x40005b60
 1408              	.set CYREG_DFT_CR5, 0x40005b61
 1409              	.set CYDEV_ANAIF_WRK_BASE, 0x40005b80
 1410              	.set CYDEV_ANAIF_WRK_SIZE, 0x00000029
 1411              	.set CYDEV_ANAIF_WRK_DAC0_BASE, 0x40005b80
 1412              	.set CYDEV_ANAIF_WRK_DAC0_SIZE, 0x00000001
 1413              	.set CYREG_DAC0_D, 0x40005b80
 1414              	.set CYDEV_ANAIF_WRK_DAC1_BASE, 0x40005b81
 1415              	.set CYDEV_ANAIF_WRK_DAC1_SIZE, 0x00000001
 1416              	.set CYREG_DAC1_D, 0x40005b81
 1417              	.set CYDEV_ANAIF_WRK_DAC2_BASE, 0x40005b82
 1418              	.set CYDEV_ANAIF_WRK_DAC2_SIZE, 0x00000001
 1419              	.set CYREG_DAC2_D, 0x40005b82
 1420              	.set CYDEV_ANAIF_WRK_DAC3_BASE, 0x40005b83
 1421              	.set CYDEV_ANAIF_WRK_DAC3_SIZE, 0x00000001
 1422              	.set CYREG_DAC3_D, 0x40005b83
 1423              	.set CYDEV_ANAIF_WRK_DSM0_BASE, 0x40005b88
 1424              	.set CYDEV_ANAIF_WRK_DSM0_SIZE, 0x00000002
 1425              	.set CYREG_DSM0_OUT0, 0x40005b88
 1426              	.set CYREG_DSM0_OUT1, 0x40005b89
 1427              	.set CYDEV_ANAIF_WRK_LUT_BASE, 0x40005b90
 1428              	.set CYDEV_ANAIF_WRK_LUT_SIZE, 0x00000005
 1429              	.set CYREG_LUT_SR, 0x40005b90
 1430              	.set CYREG_LUT_WRK1, 0x40005b91
 1431              	.set CYREG_LUT_MSK, 0x40005b92
 1432              	.set CYREG_LUT_CLK, 0x40005b93
 1433              	.set CYREG_LUT_CPTR, 0x40005b94
 1434              	.set CYDEV_ANAIF_WRK_CMP_BASE, 0x40005b96
 1435              	.set CYDEV_ANAIF_WRK_CMP_SIZE, 0x00000002
 1436              	.set CYREG_CMP_WRK, 0x40005b96
 1437              	.set CYREG_CMP_TST, 0x40005b97
 1438              	.set CYDEV_ANAIF_WRK_SC_BASE, 0x40005b98
 1439              	.set CYDEV_ANAIF_WRK_SC_SIZE, 0x00000005
 1440              	.set CYREG_SC_SR, 0x40005b98
 1441              	.set CYREG_SC_WRK1, 0x40005b99
 1442              	.set CYREG_SC_MSK, 0x40005b9a
 1443              	.set CYREG_SC_CMPINV, 0x40005b9b
 1444              	.set CYREG_SC_CPTR, 0x40005b9c
 1445              	.set CYDEV_ANAIF_WRK_SAR0_BASE, 0x40005ba0
 1446              	.set CYDEV_ANAIF_WRK_SAR0_SIZE, 0x00000002
 1447              	.set CYREG_SAR0_WRK0, 0x40005ba0
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 121


 1448              	.set CYREG_SAR0_WRK1, 0x40005ba1
 1449              	.set CYDEV_ANAIF_WRK_SAR1_BASE, 0x40005ba2
 1450              	.set CYDEV_ANAIF_WRK_SAR1_SIZE, 0x00000002
 1451              	.set CYREG_SAR1_WRK0, 0x40005ba2
 1452              	.set CYREG_SAR1_WRK1, 0x40005ba3
 1453              	.set CYDEV_ANAIF_WRK_SARS_BASE, 0x40005ba8
 1454              	.set CYDEV_ANAIF_WRK_SARS_SIZE, 0x00000001
 1455              	.set CYREG_ANAIF_WRK_SARS_SOF, 0x40005ba8
 1456              	.set CYDEV_USB_BASE, 0x40006000
 1457              	.set CYDEV_USB_SIZE, 0x00000300
 1458              	.set CYREG_USB_EP0_DR0, 0x40006000
 1459              	.set CYREG_USB_EP0_DR1, 0x40006001
 1460              	.set CYREG_USB_EP0_DR2, 0x40006002
 1461              	.set CYREG_USB_EP0_DR3, 0x40006003
 1462              	.set CYREG_USB_EP0_DR4, 0x40006004
 1463              	.set CYREG_USB_EP0_DR5, 0x40006005
 1464              	.set CYREG_USB_EP0_DR6, 0x40006006
 1465              	.set CYREG_USB_EP0_DR7, 0x40006007
 1466              	.set CYREG_USB_CR0, 0x40006008
 1467              	.set CYREG_USB_CR1, 0x40006009
 1468              	.set CYREG_USB_SIE_EP_INT_EN, 0x4000600a
 1469              	.set CYREG_USB_SIE_EP_INT_SR, 0x4000600b
 1470              	.set CYDEV_USB_SIE_EP1_BASE, 0x4000600c
 1471              	.set CYDEV_USB_SIE_EP1_SIZE, 0x00000003
 1472              	.set CYREG_USB_SIE_EP1_CNT0, 0x4000600c
 1473              	.set CYREG_USB_SIE_EP1_CNT1, 0x4000600d
 1474              	.set CYREG_USB_SIE_EP1_CR0, 0x4000600e
 1475              	.set CYREG_USB_USBIO_CR0, 0x40006010
 1476              	.set CYREG_USB_USBIO_CR1, 0x40006012
 1477              	.set CYREG_USB_DYN_RECONFIG, 0x40006014
 1478              	.set CYREG_USB_SOF0, 0x40006018
 1479              	.set CYREG_USB_SOF1, 0x40006019
 1480              	.set CYDEV_USB_SIE_EP2_BASE, 0x4000601c
 1481              	.set CYDEV_USB_SIE_EP2_SIZE, 0x00000003
 1482              	.set CYREG_USB_SIE_EP2_CNT0, 0x4000601c
 1483              	.set CYREG_USB_SIE_EP2_CNT1, 0x4000601d
 1484              	.set CYREG_USB_SIE_EP2_CR0, 0x4000601e
 1485              	.set CYREG_USB_EP0_CR, 0x40006028
 1486              	.set CYREG_USB_EP0_CNT, 0x40006029
 1487              	.set CYDEV_USB_SIE_EP3_BASE, 0x4000602c
 1488              	.set CYDEV_USB_SIE_EP3_SIZE, 0x00000003
 1489              	.set CYREG_USB_SIE_EP3_CNT0, 0x4000602c
 1490              	.set CYREG_USB_SIE_EP3_CNT1, 0x4000602d
 1491              	.set CYREG_USB_SIE_EP3_CR0, 0x4000602e
 1492              	.set CYDEV_USB_SIE_EP4_BASE, 0x4000603c
 1493              	.set CYDEV_USB_SIE_EP4_SIZE, 0x00000003
 1494              	.set CYREG_USB_SIE_EP4_CNT0, 0x4000603c
 1495              	.set CYREG_USB_SIE_EP4_CNT1, 0x4000603d
 1496              	.set CYREG_USB_SIE_EP4_CR0, 0x4000603e
 1497              	.set CYDEV_USB_SIE_EP5_BASE, 0x4000604c
 1498              	.set CYDEV_USB_SIE_EP5_SIZE, 0x00000003
 1499              	.set CYREG_USB_SIE_EP5_CNT0, 0x4000604c
 1500              	.set CYREG_USB_SIE_EP5_CNT1, 0x4000604d
 1501              	.set CYREG_USB_SIE_EP5_CR0, 0x4000604e
 1502              	.set CYDEV_USB_SIE_EP6_BASE, 0x4000605c
 1503              	.set CYDEV_USB_SIE_EP6_SIZE, 0x00000003
 1504              	.set CYREG_USB_SIE_EP6_CNT0, 0x4000605c
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 122


 1505              	.set CYREG_USB_SIE_EP6_CNT1, 0x4000605d
 1506              	.set CYREG_USB_SIE_EP6_CR0, 0x4000605e
 1507              	.set CYDEV_USB_SIE_EP7_BASE, 0x4000606c
 1508              	.set CYDEV_USB_SIE_EP7_SIZE, 0x00000003
 1509              	.set CYREG_USB_SIE_EP7_CNT0, 0x4000606c
 1510              	.set CYREG_USB_SIE_EP7_CNT1, 0x4000606d
 1511              	.set CYREG_USB_SIE_EP7_CR0, 0x4000606e
 1512              	.set CYDEV_USB_SIE_EP8_BASE, 0x4000607c
 1513              	.set CYDEV_USB_SIE_EP8_SIZE, 0x00000003
 1514              	.set CYREG_USB_SIE_EP8_CNT0, 0x4000607c
 1515              	.set CYREG_USB_SIE_EP8_CNT1, 0x4000607d
 1516              	.set CYREG_USB_SIE_EP8_CR0, 0x4000607e
 1517              	.set CYDEV_USB_ARB_EP1_BASE, 0x40006080
 1518              	.set CYDEV_USB_ARB_EP1_SIZE, 0x00000003
 1519              	.set CYREG_USB_ARB_EP1_CFG, 0x40006080
 1520              	.set CYREG_USB_ARB_EP1_INT_EN, 0x40006081
 1521              	.set CYREG_USB_ARB_EP1_SR, 0x40006082
 1522              	.set CYDEV_USB_ARB_RW1_BASE, 0x40006084
 1523              	.set CYDEV_USB_ARB_RW1_SIZE, 0x00000005
 1524              	.set CYREG_USB_ARB_RW1_WA, 0x40006084
 1525              	.set CYREG_USB_ARB_RW1_WA_MSB, 0x40006085
 1526              	.set CYREG_USB_ARB_RW1_RA, 0x40006086
 1527              	.set CYREG_USB_ARB_RW1_RA_MSB, 0x40006087
 1528              	.set CYREG_USB_ARB_RW1_DR, 0x40006088
 1529              	.set CYREG_USB_BUF_SIZE, 0x4000608c
 1530              	.set CYREG_USB_EP_ACTIVE, 0x4000608e
 1531              	.set CYREG_USB_EP_TYPE, 0x4000608f
 1532              	.set CYDEV_USB_ARB_EP2_BASE, 0x40006090
 1533              	.set CYDEV_USB_ARB_EP2_SIZE, 0x00000003
 1534              	.set CYREG_USB_ARB_EP2_CFG, 0x40006090
 1535              	.set CYREG_USB_ARB_EP2_INT_EN, 0x40006091
 1536              	.set CYREG_USB_ARB_EP2_SR, 0x40006092
 1537              	.set CYDEV_USB_ARB_RW2_BASE, 0x40006094
 1538              	.set CYDEV_USB_ARB_RW2_SIZE, 0x00000005
 1539              	.set CYREG_USB_ARB_RW2_WA, 0x40006094
 1540              	.set CYREG_USB_ARB_RW2_WA_MSB, 0x40006095
 1541              	.set CYREG_USB_ARB_RW2_RA, 0x40006096
 1542              	.set CYREG_USB_ARB_RW2_RA_MSB, 0x40006097
 1543              	.set CYREG_USB_ARB_RW2_DR, 0x40006098
 1544              	.set CYREG_USB_ARB_CFG, 0x4000609c
 1545              	.set CYREG_USB_USB_CLK_EN, 0x4000609d
 1546              	.set CYREG_USB_ARB_INT_EN, 0x4000609e
 1547              	.set CYREG_USB_ARB_INT_SR, 0x4000609f
 1548              	.set CYDEV_USB_ARB_EP3_BASE, 0x400060a0
 1549              	.set CYDEV_USB_ARB_EP3_SIZE, 0x00000003
 1550              	.set CYREG_USB_ARB_EP3_CFG, 0x400060a0
 1551              	.set CYREG_USB_ARB_EP3_INT_EN, 0x400060a1
 1552              	.set CYREG_USB_ARB_EP3_SR, 0x400060a2
 1553              	.set CYDEV_USB_ARB_RW3_BASE, 0x400060a4
 1554              	.set CYDEV_USB_ARB_RW3_SIZE, 0x00000005
 1555              	.set CYREG_USB_ARB_RW3_WA, 0x400060a4
 1556              	.set CYREG_USB_ARB_RW3_WA_MSB, 0x400060a5
 1557              	.set CYREG_USB_ARB_RW3_RA, 0x400060a6
 1558              	.set CYREG_USB_ARB_RW3_RA_MSB, 0x400060a7
 1559              	.set CYREG_USB_ARB_RW3_DR, 0x400060a8
 1560              	.set CYREG_USB_CWA, 0x400060ac
 1561              	.set CYREG_USB_CWA_MSB, 0x400060ad
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 123


 1562              	.set CYDEV_USB_ARB_EP4_BASE, 0x400060b0
 1563              	.set CYDEV_USB_ARB_EP4_SIZE, 0x00000003
 1564              	.set CYREG_USB_ARB_EP4_CFG, 0x400060b0
 1565              	.set CYREG_USB_ARB_EP4_INT_EN, 0x400060b1
 1566              	.set CYREG_USB_ARB_EP4_SR, 0x400060b2
 1567              	.set CYDEV_USB_ARB_RW4_BASE, 0x400060b4
 1568              	.set CYDEV_USB_ARB_RW4_SIZE, 0x00000005
 1569              	.set CYREG_USB_ARB_RW4_WA, 0x400060b4
 1570              	.set CYREG_USB_ARB_RW4_WA_MSB, 0x400060b5
 1571              	.set CYREG_USB_ARB_RW4_RA, 0x400060b6
 1572              	.set CYREG_USB_ARB_RW4_RA_MSB, 0x400060b7
 1573              	.set CYREG_USB_ARB_RW4_DR, 0x400060b8
 1574              	.set CYREG_USB_DMA_THRES, 0x400060bc
 1575              	.set CYREG_USB_DMA_THRES_MSB, 0x400060bd
 1576              	.set CYDEV_USB_ARB_EP5_BASE, 0x400060c0
 1577              	.set CYDEV_USB_ARB_EP5_SIZE, 0x00000003
 1578              	.set CYREG_USB_ARB_EP5_CFG, 0x400060c0
 1579              	.set CYREG_USB_ARB_EP5_INT_EN, 0x400060c1
 1580              	.set CYREG_USB_ARB_EP5_SR, 0x400060c2
 1581              	.set CYDEV_USB_ARB_RW5_BASE, 0x400060c4
 1582              	.set CYDEV_USB_ARB_RW5_SIZE, 0x00000005
 1583              	.set CYREG_USB_ARB_RW5_WA, 0x400060c4
 1584              	.set CYREG_USB_ARB_RW5_WA_MSB, 0x400060c5
 1585              	.set CYREG_USB_ARB_RW5_RA, 0x400060c6
 1586              	.set CYREG_USB_ARB_RW5_RA_MSB, 0x400060c7
 1587              	.set CYREG_USB_ARB_RW5_DR, 0x400060c8
 1588              	.set CYREG_USB_BUS_RST_CNT, 0x400060cc
 1589              	.set CYDEV_USB_ARB_EP6_BASE, 0x400060d0
 1590              	.set CYDEV_USB_ARB_EP6_SIZE, 0x00000003
 1591              	.set CYREG_USB_ARB_EP6_CFG, 0x400060d0
 1592              	.set CYREG_USB_ARB_EP6_INT_EN, 0x400060d1
 1593              	.set CYREG_USB_ARB_EP6_SR, 0x400060d2
 1594              	.set CYDEV_USB_ARB_RW6_BASE, 0x400060d4
 1595              	.set CYDEV_USB_ARB_RW6_SIZE, 0x00000005
 1596              	.set CYREG_USB_ARB_RW6_WA, 0x400060d4
 1597              	.set CYREG_USB_ARB_RW6_WA_MSB, 0x400060d5
 1598              	.set CYREG_USB_ARB_RW6_RA, 0x400060d6
 1599              	.set CYREG_USB_ARB_RW6_RA_MSB, 0x400060d7
 1600              	.set CYREG_USB_ARB_RW6_DR, 0x400060d8
 1601              	.set CYDEV_USB_ARB_EP7_BASE, 0x400060e0
 1602              	.set CYDEV_USB_ARB_EP7_SIZE, 0x00000003
 1603              	.set CYREG_USB_ARB_EP7_CFG, 0x400060e0
 1604              	.set CYREG_USB_ARB_EP7_INT_EN, 0x400060e1
 1605              	.set CYREG_USB_ARB_EP7_SR, 0x400060e2
 1606              	.set CYDEV_USB_ARB_RW7_BASE, 0x400060e4
 1607              	.set CYDEV_USB_ARB_RW7_SIZE, 0x00000005
 1608              	.set CYREG_USB_ARB_RW7_WA, 0x400060e4
 1609              	.set CYREG_USB_ARB_RW7_WA_MSB, 0x400060e5
 1610              	.set CYREG_USB_ARB_RW7_RA, 0x400060e6
 1611              	.set CYREG_USB_ARB_RW7_RA_MSB, 0x400060e7
 1612              	.set CYREG_USB_ARB_RW7_DR, 0x400060e8
 1613              	.set CYDEV_USB_ARB_EP8_BASE, 0x400060f0
 1614              	.set CYDEV_USB_ARB_EP8_SIZE, 0x00000003
 1615              	.set CYREG_USB_ARB_EP8_CFG, 0x400060f0
 1616              	.set CYREG_USB_ARB_EP8_INT_EN, 0x400060f1
 1617              	.set CYREG_USB_ARB_EP8_SR, 0x400060f2
 1618              	.set CYDEV_USB_ARB_RW8_BASE, 0x400060f4
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 124


 1619              	.set CYDEV_USB_ARB_RW8_SIZE, 0x00000005
 1620              	.set CYREG_USB_ARB_RW8_WA, 0x400060f4
 1621              	.set CYREG_USB_ARB_RW8_WA_MSB, 0x400060f5
 1622              	.set CYREG_USB_ARB_RW8_RA, 0x400060f6
 1623              	.set CYREG_USB_ARB_RW8_RA_MSB, 0x400060f7
 1624              	.set CYREG_USB_ARB_RW8_DR, 0x400060f8
 1625              	.set CYDEV_USB_MEM_BASE, 0x40006100
 1626              	.set CYDEV_USB_MEM_SIZE, 0x00000200
 1627              	.set CYREG_USB_MEM_DATA_MBASE, 0x40006100
 1628              	.set CYREG_USB_MEM_DATA_MSIZE, 0x00000200
 1629              	.set CYDEV_UWRK_BASE, 0x40006400
 1630              	.set CYDEV_UWRK_SIZE, 0x00000b60
 1631              	.set CYDEV_UWRK_UWRK8_BASE, 0x40006400
 1632              	.set CYDEV_UWRK_UWRK8_SIZE, 0x000003b0
 1633              	.set CYDEV_UWRK_UWRK8_B0_BASE, 0x40006400
 1634              	.set CYDEV_UWRK_UWRK8_B0_SIZE, 0x000000b0
 1635              	.set CYREG_B0_UDB00_A0, 0x40006400
 1636              	.set CYREG_B0_UDB01_A0, 0x40006401
 1637              	.set CYREG_B0_UDB02_A0, 0x40006402
 1638              	.set CYREG_B0_UDB03_A0, 0x40006403
 1639              	.set CYREG_B0_UDB04_A0, 0x40006404
 1640              	.set CYREG_B0_UDB05_A0, 0x40006405
 1641              	.set CYREG_B0_UDB06_A0, 0x40006406
 1642              	.set CYREG_B0_UDB07_A0, 0x40006407
 1643              	.set CYREG_B0_UDB08_A0, 0x40006408
 1644              	.set CYREG_B0_UDB09_A0, 0x40006409
 1645              	.set CYREG_B0_UDB10_A0, 0x4000640a
 1646              	.set CYREG_B0_UDB11_A0, 0x4000640b
 1647              	.set CYREG_B0_UDB12_A0, 0x4000640c
 1648              	.set CYREG_B0_UDB13_A0, 0x4000640d
 1649              	.set CYREG_B0_UDB14_A0, 0x4000640e
 1650              	.set CYREG_B0_UDB15_A0, 0x4000640f
 1651              	.set CYREG_B0_UDB00_A1, 0x40006410
 1652              	.set CYREG_B0_UDB01_A1, 0x40006411
 1653              	.set CYREG_B0_UDB02_A1, 0x40006412
 1654              	.set CYREG_B0_UDB03_A1, 0x40006413
 1655              	.set CYREG_B0_UDB04_A1, 0x40006414
 1656              	.set CYREG_B0_UDB05_A1, 0x40006415
 1657              	.set CYREG_B0_UDB06_A1, 0x40006416
 1658              	.set CYREG_B0_UDB07_A1, 0x40006417
 1659              	.set CYREG_B0_UDB08_A1, 0x40006418
 1660              	.set CYREG_B0_UDB09_A1, 0x40006419
 1661              	.set CYREG_B0_UDB10_A1, 0x4000641a
 1662              	.set CYREG_B0_UDB11_A1, 0x4000641b
 1663              	.set CYREG_B0_UDB12_A1, 0x4000641c
 1664              	.set CYREG_B0_UDB13_A1, 0x4000641d
 1665              	.set CYREG_B0_UDB14_A1, 0x4000641e
 1666              	.set CYREG_B0_UDB15_A1, 0x4000641f
 1667              	.set CYREG_B0_UDB00_D0, 0x40006420
 1668              	.set CYREG_B0_UDB01_D0, 0x40006421
 1669              	.set CYREG_B0_UDB02_D0, 0x40006422
 1670              	.set CYREG_B0_UDB03_D0, 0x40006423
 1671              	.set CYREG_B0_UDB04_D0, 0x40006424
 1672              	.set CYREG_B0_UDB05_D0, 0x40006425
 1673              	.set CYREG_B0_UDB06_D0, 0x40006426
 1674              	.set CYREG_B0_UDB07_D0, 0x40006427
 1675              	.set CYREG_B0_UDB08_D0, 0x40006428
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 125


 1676              	.set CYREG_B0_UDB09_D0, 0x40006429
 1677              	.set CYREG_B0_UDB10_D0, 0x4000642a
 1678              	.set CYREG_B0_UDB11_D0, 0x4000642b
 1679              	.set CYREG_B0_UDB12_D0, 0x4000642c
 1680              	.set CYREG_B0_UDB13_D0, 0x4000642d
 1681              	.set CYREG_B0_UDB14_D0, 0x4000642e
 1682              	.set CYREG_B0_UDB15_D0, 0x4000642f
 1683              	.set CYREG_B0_UDB00_D1, 0x40006430
 1684              	.set CYREG_B0_UDB01_D1, 0x40006431
 1685              	.set CYREG_B0_UDB02_D1, 0x40006432
 1686              	.set CYREG_B0_UDB03_D1, 0x40006433
 1687              	.set CYREG_B0_UDB04_D1, 0x40006434
 1688              	.set CYREG_B0_UDB05_D1, 0x40006435
 1689              	.set CYREG_B0_UDB06_D1, 0x40006436
 1690              	.set CYREG_B0_UDB07_D1, 0x40006437
 1691              	.set CYREG_B0_UDB08_D1, 0x40006438
 1692              	.set CYREG_B0_UDB09_D1, 0x40006439
 1693              	.set CYREG_B0_UDB10_D1, 0x4000643a
 1694              	.set CYREG_B0_UDB11_D1, 0x4000643b
 1695              	.set CYREG_B0_UDB12_D1, 0x4000643c
 1696              	.set CYREG_B0_UDB13_D1, 0x4000643d
 1697              	.set CYREG_B0_UDB14_D1, 0x4000643e
 1698              	.set CYREG_B0_UDB15_D1, 0x4000643f
 1699              	.set CYREG_B0_UDB00_F0, 0x40006440
 1700              	.set CYREG_B0_UDB01_F0, 0x40006441
 1701              	.set CYREG_B0_UDB02_F0, 0x40006442
 1702              	.set CYREG_B0_UDB03_F0, 0x40006443
 1703              	.set CYREG_B0_UDB04_F0, 0x40006444
 1704              	.set CYREG_B0_UDB05_F0, 0x40006445
 1705              	.set CYREG_B0_UDB06_F0, 0x40006446
 1706              	.set CYREG_B0_UDB07_F0, 0x40006447
 1707              	.set CYREG_B0_UDB08_F0, 0x40006448
 1708              	.set CYREG_B0_UDB09_F0, 0x40006449
 1709              	.set CYREG_B0_UDB10_F0, 0x4000644a
 1710              	.set CYREG_B0_UDB11_F0, 0x4000644b
 1711              	.set CYREG_B0_UDB12_F0, 0x4000644c
 1712              	.set CYREG_B0_UDB13_F0, 0x4000644d
 1713              	.set CYREG_B0_UDB14_F0, 0x4000644e
 1714              	.set CYREG_B0_UDB15_F0, 0x4000644f
 1715              	.set CYREG_B0_UDB00_F1, 0x40006450
 1716              	.set CYREG_B0_UDB01_F1, 0x40006451
 1717              	.set CYREG_B0_UDB02_F1, 0x40006452
 1718              	.set CYREG_B0_UDB03_F1, 0x40006453
 1719              	.set CYREG_B0_UDB04_F1, 0x40006454
 1720              	.set CYREG_B0_UDB05_F1, 0x40006455
 1721              	.set CYREG_B0_UDB06_F1, 0x40006456
 1722              	.set CYREG_B0_UDB07_F1, 0x40006457
 1723              	.set CYREG_B0_UDB08_F1, 0x40006458
 1724              	.set CYREG_B0_UDB09_F1, 0x40006459
 1725              	.set CYREG_B0_UDB10_F1, 0x4000645a
 1726              	.set CYREG_B0_UDB11_F1, 0x4000645b
 1727              	.set CYREG_B0_UDB12_F1, 0x4000645c
 1728              	.set CYREG_B0_UDB13_F1, 0x4000645d
 1729              	.set CYREG_B0_UDB14_F1, 0x4000645e
 1730              	.set CYREG_B0_UDB15_F1, 0x4000645f
 1731              	.set CYREG_B0_UDB00_ST, 0x40006460
 1732              	.set CYREG_B0_UDB01_ST, 0x40006461
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 126


 1733              	.set CYREG_B0_UDB02_ST, 0x40006462
 1734              	.set CYREG_B0_UDB03_ST, 0x40006463
 1735              	.set CYREG_B0_UDB04_ST, 0x40006464
 1736              	.set CYREG_B0_UDB05_ST, 0x40006465
 1737              	.set CYREG_B0_UDB06_ST, 0x40006466
 1738              	.set CYREG_B0_UDB07_ST, 0x40006467
 1739              	.set CYREG_B0_UDB08_ST, 0x40006468
 1740              	.set CYREG_B0_UDB09_ST, 0x40006469
 1741              	.set CYREG_B0_UDB10_ST, 0x4000646a
 1742              	.set CYREG_B0_UDB11_ST, 0x4000646b
 1743              	.set CYREG_B0_UDB12_ST, 0x4000646c
 1744              	.set CYREG_B0_UDB13_ST, 0x4000646d
 1745              	.set CYREG_B0_UDB14_ST, 0x4000646e
 1746              	.set CYREG_B0_UDB15_ST, 0x4000646f
 1747              	.set CYREG_B0_UDB00_CTL, 0x40006470
 1748              	.set CYREG_B0_UDB01_CTL, 0x40006471
 1749              	.set CYREG_B0_UDB02_CTL, 0x40006472
 1750              	.set CYREG_B0_UDB03_CTL, 0x40006473
 1751              	.set CYREG_B0_UDB04_CTL, 0x40006474
 1752              	.set CYREG_B0_UDB05_CTL, 0x40006475
 1753              	.set CYREG_B0_UDB06_CTL, 0x40006476
 1754              	.set CYREG_B0_UDB07_CTL, 0x40006477
 1755              	.set CYREG_B0_UDB08_CTL, 0x40006478
 1756              	.set CYREG_B0_UDB09_CTL, 0x40006479
 1757              	.set CYREG_B0_UDB10_CTL, 0x4000647a
 1758              	.set CYREG_B0_UDB11_CTL, 0x4000647b
 1759              	.set CYREG_B0_UDB12_CTL, 0x4000647c
 1760              	.set CYREG_B0_UDB13_CTL, 0x4000647d
 1761              	.set CYREG_B0_UDB14_CTL, 0x4000647e
 1762              	.set CYREG_B0_UDB15_CTL, 0x4000647f
 1763              	.set CYREG_B0_UDB00_MSK, 0x40006480
 1764              	.set CYREG_B0_UDB01_MSK, 0x40006481
 1765              	.set CYREG_B0_UDB02_MSK, 0x40006482
 1766              	.set CYREG_B0_UDB03_MSK, 0x40006483
 1767              	.set CYREG_B0_UDB04_MSK, 0x40006484
 1768              	.set CYREG_B0_UDB05_MSK, 0x40006485
 1769              	.set CYREG_B0_UDB06_MSK, 0x40006486
 1770              	.set CYREG_B0_UDB07_MSK, 0x40006487
 1771              	.set CYREG_B0_UDB08_MSK, 0x40006488
 1772              	.set CYREG_B0_UDB09_MSK, 0x40006489
 1773              	.set CYREG_B0_UDB10_MSK, 0x4000648a
 1774              	.set CYREG_B0_UDB11_MSK, 0x4000648b
 1775              	.set CYREG_B0_UDB12_MSK, 0x4000648c
 1776              	.set CYREG_B0_UDB13_MSK, 0x4000648d
 1777              	.set CYREG_B0_UDB14_MSK, 0x4000648e
 1778              	.set CYREG_B0_UDB15_MSK, 0x4000648f
 1779              	.set CYREG_B0_UDB00_ACTL, 0x40006490
 1780              	.set CYREG_B0_UDB01_ACTL, 0x40006491
 1781              	.set CYREG_B0_UDB02_ACTL, 0x40006492
 1782              	.set CYREG_B0_UDB03_ACTL, 0x40006493
 1783              	.set CYREG_B0_UDB04_ACTL, 0x40006494
 1784              	.set CYREG_B0_UDB05_ACTL, 0x40006495
 1785              	.set CYREG_B0_UDB06_ACTL, 0x40006496
 1786              	.set CYREG_B0_UDB07_ACTL, 0x40006497
 1787              	.set CYREG_B0_UDB08_ACTL, 0x40006498
 1788              	.set CYREG_B0_UDB09_ACTL, 0x40006499
 1789              	.set CYREG_B0_UDB10_ACTL, 0x4000649a
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 127


 1790              	.set CYREG_B0_UDB11_ACTL, 0x4000649b
 1791              	.set CYREG_B0_UDB12_ACTL, 0x4000649c
 1792              	.set CYREG_B0_UDB13_ACTL, 0x4000649d
 1793              	.set CYREG_B0_UDB14_ACTL, 0x4000649e
 1794              	.set CYREG_B0_UDB15_ACTL, 0x4000649f
 1795              	.set CYREG_B0_UDB00_MC, 0x400064a0
 1796              	.set CYREG_B0_UDB01_MC, 0x400064a1
 1797              	.set CYREG_B0_UDB02_MC, 0x400064a2
 1798              	.set CYREG_B0_UDB03_MC, 0x400064a3
 1799              	.set CYREG_B0_UDB04_MC, 0x400064a4
 1800              	.set CYREG_B0_UDB05_MC, 0x400064a5
 1801              	.set CYREG_B0_UDB06_MC, 0x400064a6
 1802              	.set CYREG_B0_UDB07_MC, 0x400064a7
 1803              	.set CYREG_B0_UDB08_MC, 0x400064a8
 1804              	.set CYREG_B0_UDB09_MC, 0x400064a9
 1805              	.set CYREG_B0_UDB10_MC, 0x400064aa
 1806              	.set CYREG_B0_UDB11_MC, 0x400064ab
 1807              	.set CYREG_B0_UDB12_MC, 0x400064ac
 1808              	.set CYREG_B0_UDB13_MC, 0x400064ad
 1809              	.set CYREG_B0_UDB14_MC, 0x400064ae
 1810              	.set CYREG_B0_UDB15_MC, 0x400064af
 1811              	.set CYDEV_UWRK_UWRK8_B1_BASE, 0x40006500
 1812              	.set CYDEV_UWRK_UWRK8_B1_SIZE, 0x000000b0
 1813              	.set CYREG_B1_UDB04_A0, 0x40006504
 1814              	.set CYREG_B1_UDB05_A0, 0x40006505
 1815              	.set CYREG_B1_UDB06_A0, 0x40006506
 1816              	.set CYREG_B1_UDB07_A0, 0x40006507
 1817              	.set CYREG_B1_UDB08_A0, 0x40006508
 1818              	.set CYREG_B1_UDB09_A0, 0x40006509
 1819              	.set CYREG_B1_UDB10_A0, 0x4000650a
 1820              	.set CYREG_B1_UDB11_A0, 0x4000650b
 1821              	.set CYREG_B1_UDB04_A1, 0x40006514
 1822              	.set CYREG_B1_UDB05_A1, 0x40006515
 1823              	.set CYREG_B1_UDB06_A1, 0x40006516
 1824              	.set CYREG_B1_UDB07_A1, 0x40006517
 1825              	.set CYREG_B1_UDB08_A1, 0x40006518
 1826              	.set CYREG_B1_UDB09_A1, 0x40006519
 1827              	.set CYREG_B1_UDB10_A1, 0x4000651a
 1828              	.set CYREG_B1_UDB11_A1, 0x4000651b
 1829              	.set CYREG_B1_UDB04_D0, 0x40006524
 1830              	.set CYREG_B1_UDB05_D0, 0x40006525
 1831              	.set CYREG_B1_UDB06_D0, 0x40006526
 1832              	.set CYREG_B1_UDB07_D0, 0x40006527
 1833              	.set CYREG_B1_UDB08_D0, 0x40006528
 1834              	.set CYREG_B1_UDB09_D0, 0x40006529
 1835              	.set CYREG_B1_UDB10_D0, 0x4000652a
 1836              	.set CYREG_B1_UDB11_D0, 0x4000652b
 1837              	.set CYREG_B1_UDB04_D1, 0x40006534
 1838              	.set CYREG_B1_UDB05_D1, 0x40006535
 1839              	.set CYREG_B1_UDB06_D1, 0x40006536
 1840              	.set CYREG_B1_UDB07_D1, 0x40006537
 1841              	.set CYREG_B1_UDB08_D1, 0x40006538
 1842              	.set CYREG_B1_UDB09_D1, 0x40006539
 1843              	.set CYREG_B1_UDB10_D1, 0x4000653a
 1844              	.set CYREG_B1_UDB11_D1, 0x4000653b
 1845              	.set CYREG_B1_UDB04_F0, 0x40006544
 1846              	.set CYREG_B1_UDB05_F0, 0x40006545
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 128


 1847              	.set CYREG_B1_UDB06_F0, 0x40006546
 1848              	.set CYREG_B1_UDB07_F0, 0x40006547
 1849              	.set CYREG_B1_UDB08_F0, 0x40006548
 1850              	.set CYREG_B1_UDB09_F0, 0x40006549
 1851              	.set CYREG_B1_UDB10_F0, 0x4000654a
 1852              	.set CYREG_B1_UDB11_F0, 0x4000654b
 1853              	.set CYREG_B1_UDB04_F1, 0x40006554
 1854              	.set CYREG_B1_UDB05_F1, 0x40006555
 1855              	.set CYREG_B1_UDB06_F1, 0x40006556
 1856              	.set CYREG_B1_UDB07_F1, 0x40006557
 1857              	.set CYREG_B1_UDB08_F1, 0x40006558
 1858              	.set CYREG_B1_UDB09_F1, 0x40006559
 1859              	.set CYREG_B1_UDB10_F1, 0x4000655a
 1860              	.set CYREG_B1_UDB11_F1, 0x4000655b
 1861              	.set CYREG_B1_UDB04_ST, 0x40006564
 1862              	.set CYREG_B1_UDB05_ST, 0x40006565
 1863              	.set CYREG_B1_UDB06_ST, 0x40006566
 1864              	.set CYREG_B1_UDB07_ST, 0x40006567
 1865              	.set CYREG_B1_UDB08_ST, 0x40006568
 1866              	.set CYREG_B1_UDB09_ST, 0x40006569
 1867              	.set CYREG_B1_UDB10_ST, 0x4000656a
 1868              	.set CYREG_B1_UDB11_ST, 0x4000656b
 1869              	.set CYREG_B1_UDB04_CTL, 0x40006574
 1870              	.set CYREG_B1_UDB05_CTL, 0x40006575
 1871              	.set CYREG_B1_UDB06_CTL, 0x40006576
 1872              	.set CYREG_B1_UDB07_CTL, 0x40006577
 1873              	.set CYREG_B1_UDB08_CTL, 0x40006578
 1874              	.set CYREG_B1_UDB09_CTL, 0x40006579
 1875              	.set CYREG_B1_UDB10_CTL, 0x4000657a
 1876              	.set CYREG_B1_UDB11_CTL, 0x4000657b
 1877              	.set CYREG_B1_UDB04_MSK, 0x40006584
 1878              	.set CYREG_B1_UDB05_MSK, 0x40006585
 1879              	.set CYREG_B1_UDB06_MSK, 0x40006586
 1880              	.set CYREG_B1_UDB07_MSK, 0x40006587
 1881              	.set CYREG_B1_UDB08_MSK, 0x40006588
 1882              	.set CYREG_B1_UDB09_MSK, 0x40006589
 1883              	.set CYREG_B1_UDB10_MSK, 0x4000658a
 1884              	.set CYREG_B1_UDB11_MSK, 0x4000658b
 1885              	.set CYREG_B1_UDB04_ACTL, 0x40006594
 1886              	.set CYREG_B1_UDB05_ACTL, 0x40006595
 1887              	.set CYREG_B1_UDB06_ACTL, 0x40006596
 1888              	.set CYREG_B1_UDB07_ACTL, 0x40006597
 1889              	.set CYREG_B1_UDB08_ACTL, 0x40006598
 1890              	.set CYREG_B1_UDB09_ACTL, 0x40006599
 1891              	.set CYREG_B1_UDB10_ACTL, 0x4000659a
 1892              	.set CYREG_B1_UDB11_ACTL, 0x4000659b
 1893              	.set CYREG_B1_UDB04_MC, 0x400065a4
 1894              	.set CYREG_B1_UDB05_MC, 0x400065a5
 1895              	.set CYREG_B1_UDB06_MC, 0x400065a6
 1896              	.set CYREG_B1_UDB07_MC, 0x400065a7
 1897              	.set CYREG_B1_UDB08_MC, 0x400065a8
 1898              	.set CYREG_B1_UDB09_MC, 0x400065a9
 1899              	.set CYREG_B1_UDB10_MC, 0x400065aa
 1900              	.set CYREG_B1_UDB11_MC, 0x400065ab
 1901              	.set CYDEV_UWRK_UWRK16_BASE, 0x40006800
 1902              	.set CYDEV_UWRK_UWRK16_SIZE, 0x00000760
 1903              	.set CYDEV_UWRK_UWRK16_CAT_BASE, 0x40006800
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 129


 1904              	.set CYDEV_UWRK_UWRK16_CAT_SIZE, 0x00000760
 1905              	.set CYDEV_UWRK_UWRK16_CAT_B0_BASE, 0x40006800
 1906              	.set CYDEV_UWRK_UWRK16_CAT_B0_SIZE, 0x00000160
 1907              	.set CYREG_B0_UDB00_A0_A1, 0x40006800
 1908              	.set CYREG_B0_UDB01_A0_A1, 0x40006802
 1909              	.set CYREG_B0_UDB02_A0_A1, 0x40006804
 1910              	.set CYREG_B0_UDB03_A0_A1, 0x40006806
 1911              	.set CYREG_B0_UDB04_A0_A1, 0x40006808
 1912              	.set CYREG_B0_UDB05_A0_A1, 0x4000680a
 1913              	.set CYREG_B0_UDB06_A0_A1, 0x4000680c
 1914              	.set CYREG_B0_UDB07_A0_A1, 0x4000680e
 1915              	.set CYREG_B0_UDB08_A0_A1, 0x40006810
 1916              	.set CYREG_B0_UDB09_A0_A1, 0x40006812
 1917              	.set CYREG_B0_UDB10_A0_A1, 0x40006814
 1918              	.set CYREG_B0_UDB11_A0_A1, 0x40006816
 1919              	.set CYREG_B0_UDB12_A0_A1, 0x40006818
 1920              	.set CYREG_B0_UDB13_A0_A1, 0x4000681a
 1921              	.set CYREG_B0_UDB14_A0_A1, 0x4000681c
 1922              	.set CYREG_B0_UDB15_A0_A1, 0x4000681e
 1923              	.set CYREG_B0_UDB00_D0_D1, 0x40006840
 1924              	.set CYREG_B0_UDB01_D0_D1, 0x40006842
 1925              	.set CYREG_B0_UDB02_D0_D1, 0x40006844
 1926              	.set CYREG_B0_UDB03_D0_D1, 0x40006846
 1927              	.set CYREG_B0_UDB04_D0_D1, 0x40006848
 1928              	.set CYREG_B0_UDB05_D0_D1, 0x4000684a
 1929              	.set CYREG_B0_UDB06_D0_D1, 0x4000684c
 1930              	.set CYREG_B0_UDB07_D0_D1, 0x4000684e
 1931              	.set CYREG_B0_UDB08_D0_D1, 0x40006850
 1932              	.set CYREG_B0_UDB09_D0_D1, 0x40006852
 1933              	.set CYREG_B0_UDB10_D0_D1, 0x40006854
 1934              	.set CYREG_B0_UDB11_D0_D1, 0x40006856
 1935              	.set CYREG_B0_UDB12_D0_D1, 0x40006858
 1936              	.set CYREG_B0_UDB13_D0_D1, 0x4000685a
 1937              	.set CYREG_B0_UDB14_D0_D1, 0x4000685c
 1938              	.set CYREG_B0_UDB15_D0_D1, 0x4000685e
 1939              	.set CYREG_B0_UDB00_F0_F1, 0x40006880
 1940              	.set CYREG_B0_UDB01_F0_F1, 0x40006882
 1941              	.set CYREG_B0_UDB02_F0_F1, 0x40006884
 1942              	.set CYREG_B0_UDB03_F0_F1, 0x40006886
 1943              	.set CYREG_B0_UDB04_F0_F1, 0x40006888
 1944              	.set CYREG_B0_UDB05_F0_F1, 0x4000688a
 1945              	.set CYREG_B0_UDB06_F0_F1, 0x4000688c
 1946              	.set CYREG_B0_UDB07_F0_F1, 0x4000688e
 1947              	.set CYREG_B0_UDB08_F0_F1, 0x40006890
 1948              	.set CYREG_B0_UDB09_F0_F1, 0x40006892
 1949              	.set CYREG_B0_UDB10_F0_F1, 0x40006894
 1950              	.set CYREG_B0_UDB11_F0_F1, 0x40006896
 1951              	.set CYREG_B0_UDB12_F0_F1, 0x40006898
 1952              	.set CYREG_B0_UDB13_F0_F1, 0x4000689a
 1953              	.set CYREG_B0_UDB14_F0_F1, 0x4000689c
 1954              	.set CYREG_B0_UDB15_F0_F1, 0x4000689e
 1955              	.set CYREG_B0_UDB00_ST_CTL, 0x400068c0
 1956              	.set CYREG_B0_UDB01_ST_CTL, 0x400068c2
 1957              	.set CYREG_B0_UDB02_ST_CTL, 0x400068c4
 1958              	.set CYREG_B0_UDB03_ST_CTL, 0x400068c6
 1959              	.set CYREG_B0_UDB04_ST_CTL, 0x400068c8
 1960              	.set CYREG_B0_UDB05_ST_CTL, 0x400068ca
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 130


 1961              	.set CYREG_B0_UDB06_ST_CTL, 0x400068cc
 1962              	.set CYREG_B0_UDB07_ST_CTL, 0x400068ce
 1963              	.set CYREG_B0_UDB08_ST_CTL, 0x400068d0
 1964              	.set CYREG_B0_UDB09_ST_CTL, 0x400068d2
 1965              	.set CYREG_B0_UDB10_ST_CTL, 0x400068d4
 1966              	.set CYREG_B0_UDB11_ST_CTL, 0x400068d6
 1967              	.set CYREG_B0_UDB12_ST_CTL, 0x400068d8
 1968              	.set CYREG_B0_UDB13_ST_CTL, 0x400068da
 1969              	.set CYREG_B0_UDB14_ST_CTL, 0x400068dc
 1970              	.set CYREG_B0_UDB15_ST_CTL, 0x400068de
 1971              	.set CYREG_B0_UDB00_MSK_ACTL, 0x40006900
 1972              	.set CYREG_B0_UDB01_MSK_ACTL, 0x40006902
 1973              	.set CYREG_B0_UDB02_MSK_ACTL, 0x40006904
 1974              	.set CYREG_B0_UDB03_MSK_ACTL, 0x40006906
 1975              	.set CYREG_B0_UDB04_MSK_ACTL, 0x40006908
 1976              	.set CYREG_B0_UDB05_MSK_ACTL, 0x4000690a
 1977              	.set CYREG_B0_UDB06_MSK_ACTL, 0x4000690c
 1978              	.set CYREG_B0_UDB07_MSK_ACTL, 0x4000690e
 1979              	.set CYREG_B0_UDB08_MSK_ACTL, 0x40006910
 1980              	.set CYREG_B0_UDB09_MSK_ACTL, 0x40006912
 1981              	.set CYREG_B0_UDB10_MSK_ACTL, 0x40006914
 1982              	.set CYREG_B0_UDB11_MSK_ACTL, 0x40006916
 1983              	.set CYREG_B0_UDB12_MSK_ACTL, 0x40006918
 1984              	.set CYREG_B0_UDB13_MSK_ACTL, 0x4000691a
 1985              	.set CYREG_B0_UDB14_MSK_ACTL, 0x4000691c
 1986              	.set CYREG_B0_UDB15_MSK_ACTL, 0x4000691e
 1987              	.set CYREG_B0_UDB00_MC_00, 0x40006940
 1988              	.set CYREG_B0_UDB01_MC_00, 0x40006942
 1989              	.set CYREG_B0_UDB02_MC_00, 0x40006944
 1990              	.set CYREG_B0_UDB03_MC_00, 0x40006946
 1991              	.set CYREG_B0_UDB04_MC_00, 0x40006948
 1992              	.set CYREG_B0_UDB05_MC_00, 0x4000694a
 1993              	.set CYREG_B0_UDB06_MC_00, 0x4000694c
 1994              	.set CYREG_B0_UDB07_MC_00, 0x4000694e
 1995              	.set CYREG_B0_UDB08_MC_00, 0x40006950
 1996              	.set CYREG_B0_UDB09_MC_00, 0x40006952
 1997              	.set CYREG_B0_UDB10_MC_00, 0x40006954
 1998              	.set CYREG_B0_UDB11_MC_00, 0x40006956
 1999              	.set CYREG_B0_UDB12_MC_00, 0x40006958
 2000              	.set CYREG_B0_UDB13_MC_00, 0x4000695a
 2001              	.set CYREG_B0_UDB14_MC_00, 0x4000695c
 2002              	.set CYREG_B0_UDB15_MC_00, 0x4000695e
 2003              	.set CYDEV_UWRK_UWRK16_CAT_B1_BASE, 0x40006a00
 2004              	.set CYDEV_UWRK_UWRK16_CAT_B1_SIZE, 0x00000160
 2005              	.set CYREG_B1_UDB04_A0_A1, 0x40006a08
 2006              	.set CYREG_B1_UDB05_A0_A1, 0x40006a0a
 2007              	.set CYREG_B1_UDB06_A0_A1, 0x40006a0c
 2008              	.set CYREG_B1_UDB07_A0_A1, 0x40006a0e
 2009              	.set CYREG_B1_UDB08_A0_A1, 0x40006a10
 2010              	.set CYREG_B1_UDB09_A0_A1, 0x40006a12
 2011              	.set CYREG_B1_UDB10_A0_A1, 0x40006a14
 2012              	.set CYREG_B1_UDB11_A0_A1, 0x40006a16
 2013              	.set CYREG_B1_UDB04_D0_D1, 0x40006a48
 2014              	.set CYREG_B1_UDB05_D0_D1, 0x40006a4a
 2015              	.set CYREG_B1_UDB06_D0_D1, 0x40006a4c
 2016              	.set CYREG_B1_UDB07_D0_D1, 0x40006a4e
 2017              	.set CYREG_B1_UDB08_D0_D1, 0x40006a50
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 131


 2018              	.set CYREG_B1_UDB09_D0_D1, 0x40006a52
 2019              	.set CYREG_B1_UDB10_D0_D1, 0x40006a54
 2020              	.set CYREG_B1_UDB11_D0_D1, 0x40006a56
 2021              	.set CYREG_B1_UDB04_F0_F1, 0x40006a88
 2022              	.set CYREG_B1_UDB05_F0_F1, 0x40006a8a
 2023              	.set CYREG_B1_UDB06_F0_F1, 0x40006a8c
 2024              	.set CYREG_B1_UDB07_F0_F1, 0x40006a8e
 2025              	.set CYREG_B1_UDB08_F0_F1, 0x40006a90
 2026              	.set CYREG_B1_UDB09_F0_F1, 0x40006a92
 2027              	.set CYREG_B1_UDB10_F0_F1, 0x40006a94
 2028              	.set CYREG_B1_UDB11_F0_F1, 0x40006a96
 2029              	.set CYREG_B1_UDB04_ST_CTL, 0x40006ac8
 2030              	.set CYREG_B1_UDB05_ST_CTL, 0x40006aca
 2031              	.set CYREG_B1_UDB06_ST_CTL, 0x40006acc
 2032              	.set CYREG_B1_UDB07_ST_CTL, 0x40006ace
 2033              	.set CYREG_B1_UDB08_ST_CTL, 0x40006ad0
 2034              	.set CYREG_B1_UDB09_ST_CTL, 0x40006ad2
 2035              	.set CYREG_B1_UDB10_ST_CTL, 0x40006ad4
 2036              	.set CYREG_B1_UDB11_ST_CTL, 0x40006ad6
 2037              	.set CYREG_B1_UDB04_MSK_ACTL, 0x40006b08
 2038              	.set CYREG_B1_UDB05_MSK_ACTL, 0x40006b0a
 2039              	.set CYREG_B1_UDB06_MSK_ACTL, 0x40006b0c
 2040              	.set CYREG_B1_UDB07_MSK_ACTL, 0x40006b0e
 2041              	.set CYREG_B1_UDB08_MSK_ACTL, 0x40006b10
 2042              	.set CYREG_B1_UDB09_MSK_ACTL, 0x40006b12
 2043              	.set CYREG_B1_UDB10_MSK_ACTL, 0x40006b14
 2044              	.set CYREG_B1_UDB11_MSK_ACTL, 0x40006b16
 2045              	.set CYREG_B1_UDB04_MC_00, 0x40006b48
 2046              	.set CYREG_B1_UDB05_MC_00, 0x40006b4a
 2047              	.set CYREG_B1_UDB06_MC_00, 0x40006b4c
 2048              	.set CYREG_B1_UDB07_MC_00, 0x40006b4e
 2049              	.set CYREG_B1_UDB08_MC_00, 0x40006b50
 2050              	.set CYREG_B1_UDB09_MC_00, 0x40006b52
 2051              	.set CYREG_B1_UDB10_MC_00, 0x40006b54
 2052              	.set CYREG_B1_UDB11_MC_00, 0x40006b56
 2053              	.set CYDEV_UWRK_UWRK16_DEF_BASE, 0x40006800
 2054              	.set CYDEV_UWRK_UWRK16_DEF_SIZE, 0x0000075e
 2055              	.set CYDEV_UWRK_UWRK16_DEF_B0_BASE, 0x40006800
 2056              	.set CYDEV_UWRK_UWRK16_DEF_B0_SIZE, 0x0000015e
 2057              	.set CYREG_B0_UDB00_01_A0, 0x40006800
 2058              	.set CYREG_B0_UDB01_02_A0, 0x40006802
 2059              	.set CYREG_B0_UDB02_03_A0, 0x40006804
 2060              	.set CYREG_B0_UDB03_04_A0, 0x40006806
 2061              	.set CYREG_B0_UDB04_05_A0, 0x40006808
 2062              	.set CYREG_B0_UDB05_06_A0, 0x4000680a
 2063              	.set CYREG_B0_UDB06_07_A0, 0x4000680c
 2064              	.set CYREG_B0_UDB07_08_A0, 0x4000680e
 2065              	.set CYREG_B0_UDB08_09_A0, 0x40006810
 2066              	.set CYREG_B0_UDB09_10_A0, 0x40006812
 2067              	.set CYREG_B0_UDB10_11_A0, 0x40006814
 2068              	.set CYREG_B0_UDB11_12_A0, 0x40006816
 2069              	.set CYREG_B0_UDB12_13_A0, 0x40006818
 2070              	.set CYREG_B0_UDB13_14_A0, 0x4000681a
 2071              	.set CYREG_B0_UDB14_15_A0, 0x4000681c
 2072              	.set CYREG_B0_UDB00_01_A1, 0x40006820
 2073              	.set CYREG_B0_UDB01_02_A1, 0x40006822
 2074              	.set CYREG_B0_UDB02_03_A1, 0x40006824
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 132


 2075              	.set CYREG_B0_UDB03_04_A1, 0x40006826
 2076              	.set CYREG_B0_UDB04_05_A1, 0x40006828
 2077              	.set CYREG_B0_UDB05_06_A1, 0x4000682a
 2078              	.set CYREG_B0_UDB06_07_A1, 0x4000682c
 2079              	.set CYREG_B0_UDB07_08_A1, 0x4000682e
 2080              	.set CYREG_B0_UDB08_09_A1, 0x40006830
 2081              	.set CYREG_B0_UDB09_10_A1, 0x40006832
 2082              	.set CYREG_B0_UDB10_11_A1, 0x40006834
 2083              	.set CYREG_B0_UDB11_12_A1, 0x40006836
 2084              	.set CYREG_B0_UDB12_13_A1, 0x40006838
 2085              	.set CYREG_B0_UDB13_14_A1, 0x4000683a
 2086              	.set CYREG_B0_UDB14_15_A1, 0x4000683c
 2087              	.set CYREG_B0_UDB00_01_D0, 0x40006840
 2088              	.set CYREG_B0_UDB01_02_D0, 0x40006842
 2089              	.set CYREG_B0_UDB02_03_D0, 0x40006844
 2090              	.set CYREG_B0_UDB03_04_D0, 0x40006846
 2091              	.set CYREG_B0_UDB04_05_D0, 0x40006848
 2092              	.set CYREG_B0_UDB05_06_D0, 0x4000684a
 2093              	.set CYREG_B0_UDB06_07_D0, 0x4000684c
 2094              	.set CYREG_B0_UDB07_08_D0, 0x4000684e
 2095              	.set CYREG_B0_UDB08_09_D0, 0x40006850
 2096              	.set CYREG_B0_UDB09_10_D0, 0x40006852
 2097              	.set CYREG_B0_UDB10_11_D0, 0x40006854
 2098              	.set CYREG_B0_UDB11_12_D0, 0x40006856
 2099              	.set CYREG_B0_UDB12_13_D0, 0x40006858
 2100              	.set CYREG_B0_UDB13_14_D0, 0x4000685a
 2101              	.set CYREG_B0_UDB14_15_D0, 0x4000685c
 2102              	.set CYREG_B0_UDB00_01_D1, 0x40006860
 2103              	.set CYREG_B0_UDB01_02_D1, 0x40006862
 2104              	.set CYREG_B0_UDB02_03_D1, 0x40006864
 2105              	.set CYREG_B0_UDB03_04_D1, 0x40006866
 2106              	.set CYREG_B0_UDB04_05_D1, 0x40006868
 2107              	.set CYREG_B0_UDB05_06_D1, 0x4000686a
 2108              	.set CYREG_B0_UDB06_07_D1, 0x4000686c
 2109              	.set CYREG_B0_UDB07_08_D1, 0x4000686e
 2110              	.set CYREG_B0_UDB08_09_D1, 0x40006870
 2111              	.set CYREG_B0_UDB09_10_D1, 0x40006872
 2112              	.set CYREG_B0_UDB10_11_D1, 0x40006874
 2113              	.set CYREG_B0_UDB11_12_D1, 0x40006876
 2114              	.set CYREG_B0_UDB12_13_D1, 0x40006878
 2115              	.set CYREG_B0_UDB13_14_D1, 0x4000687a
 2116              	.set CYREG_B0_UDB14_15_D1, 0x4000687c
 2117              	.set CYREG_B0_UDB00_01_F0, 0x40006880
 2118              	.set CYREG_B0_UDB01_02_F0, 0x40006882
 2119              	.set CYREG_B0_UDB02_03_F0, 0x40006884
 2120              	.set CYREG_B0_UDB03_04_F0, 0x40006886
 2121              	.set CYREG_B0_UDB04_05_F0, 0x40006888
 2122              	.set CYREG_B0_UDB05_06_F0, 0x4000688a
 2123              	.set CYREG_B0_UDB06_07_F0, 0x4000688c
 2124              	.set CYREG_B0_UDB07_08_F0, 0x4000688e
 2125              	.set CYREG_B0_UDB08_09_F0, 0x40006890
 2126              	.set CYREG_B0_UDB09_10_F0, 0x40006892
 2127              	.set CYREG_B0_UDB10_11_F0, 0x40006894
 2128              	.set CYREG_B0_UDB11_12_F0, 0x40006896
 2129              	.set CYREG_B0_UDB12_13_F0, 0x40006898
 2130              	.set CYREG_B0_UDB13_14_F0, 0x4000689a
 2131              	.set CYREG_B0_UDB14_15_F0, 0x4000689c
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 133


 2132              	.set CYREG_B0_UDB00_01_F1, 0x400068a0
 2133              	.set CYREG_B0_UDB01_02_F1, 0x400068a2
 2134              	.set CYREG_B0_UDB02_03_F1, 0x400068a4
 2135              	.set CYREG_B0_UDB03_04_F1, 0x400068a6
 2136              	.set CYREG_B0_UDB04_05_F1, 0x400068a8
 2137              	.set CYREG_B0_UDB05_06_F1, 0x400068aa
 2138              	.set CYREG_B0_UDB06_07_F1, 0x400068ac
 2139              	.set CYREG_B0_UDB07_08_F1, 0x400068ae
 2140              	.set CYREG_B0_UDB08_09_F1, 0x400068b0
 2141              	.set CYREG_B0_UDB09_10_F1, 0x400068b2
 2142              	.set CYREG_B0_UDB10_11_F1, 0x400068b4
 2143              	.set CYREG_B0_UDB11_12_F1, 0x400068b6
 2144              	.set CYREG_B0_UDB12_13_F1, 0x400068b8
 2145              	.set CYREG_B0_UDB13_14_F1, 0x400068ba
 2146              	.set CYREG_B0_UDB14_15_F1, 0x400068bc
 2147              	.set CYREG_B0_UDB00_01_ST, 0x400068c0
 2148              	.set CYREG_B0_UDB01_02_ST, 0x400068c2
 2149              	.set CYREG_B0_UDB02_03_ST, 0x400068c4
 2150              	.set CYREG_B0_UDB03_04_ST, 0x400068c6
 2151              	.set CYREG_B0_UDB04_05_ST, 0x400068c8
 2152              	.set CYREG_B0_UDB05_06_ST, 0x400068ca
 2153              	.set CYREG_B0_UDB06_07_ST, 0x400068cc
 2154              	.set CYREG_B0_UDB07_08_ST, 0x400068ce
 2155              	.set CYREG_B0_UDB08_09_ST, 0x400068d0
 2156              	.set CYREG_B0_UDB09_10_ST, 0x400068d2
 2157              	.set CYREG_B0_UDB10_11_ST, 0x400068d4
 2158              	.set CYREG_B0_UDB11_12_ST, 0x400068d6
 2159              	.set CYREG_B0_UDB12_13_ST, 0x400068d8
 2160              	.set CYREG_B0_UDB13_14_ST, 0x400068da
 2161              	.set CYREG_B0_UDB14_15_ST, 0x400068dc
 2162              	.set CYREG_B0_UDB00_01_CTL, 0x400068e0
 2163              	.set CYREG_B0_UDB01_02_CTL, 0x400068e2
 2164              	.set CYREG_B0_UDB02_03_CTL, 0x400068e4
 2165              	.set CYREG_B0_UDB03_04_CTL, 0x400068e6
 2166              	.set CYREG_B0_UDB04_05_CTL, 0x400068e8
 2167              	.set CYREG_B0_UDB05_06_CTL, 0x400068ea
 2168              	.set CYREG_B0_UDB06_07_CTL, 0x400068ec
 2169              	.set CYREG_B0_UDB07_08_CTL, 0x400068ee
 2170              	.set CYREG_B0_UDB08_09_CTL, 0x400068f0
 2171              	.set CYREG_B0_UDB09_10_CTL, 0x400068f2
 2172              	.set CYREG_B0_UDB10_11_CTL, 0x400068f4
 2173              	.set CYREG_B0_UDB11_12_CTL, 0x400068f6
 2174              	.set CYREG_B0_UDB12_13_CTL, 0x400068f8
 2175              	.set CYREG_B0_UDB13_14_CTL, 0x400068fa
 2176              	.set CYREG_B0_UDB14_15_CTL, 0x400068fc
 2177              	.set CYREG_B0_UDB00_01_MSK, 0x40006900
 2178              	.set CYREG_B0_UDB01_02_MSK, 0x40006902
 2179              	.set CYREG_B0_UDB02_03_MSK, 0x40006904
 2180              	.set CYREG_B0_UDB03_04_MSK, 0x40006906
 2181              	.set CYREG_B0_UDB04_05_MSK, 0x40006908
 2182              	.set CYREG_B0_UDB05_06_MSK, 0x4000690a
 2183              	.set CYREG_B0_UDB06_07_MSK, 0x4000690c
 2184              	.set CYREG_B0_UDB07_08_MSK, 0x4000690e
 2185              	.set CYREG_B0_UDB08_09_MSK, 0x40006910
 2186              	.set CYREG_B0_UDB09_10_MSK, 0x40006912
 2187              	.set CYREG_B0_UDB10_11_MSK, 0x40006914
 2188              	.set CYREG_B0_UDB11_12_MSK, 0x40006916
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 134


 2189              	.set CYREG_B0_UDB12_13_MSK, 0x40006918
 2190              	.set CYREG_B0_UDB13_14_MSK, 0x4000691a
 2191              	.set CYREG_B0_UDB14_15_MSK, 0x4000691c
 2192              	.set CYREG_B0_UDB00_01_ACTL, 0x40006920
 2193              	.set CYREG_B0_UDB01_02_ACTL, 0x40006922
 2194              	.set CYREG_B0_UDB02_03_ACTL, 0x40006924
 2195              	.set CYREG_B0_UDB03_04_ACTL, 0x40006926
 2196              	.set CYREG_B0_UDB04_05_ACTL, 0x40006928
 2197              	.set CYREG_B0_UDB05_06_ACTL, 0x4000692a
 2198              	.set CYREG_B0_UDB06_07_ACTL, 0x4000692c
 2199              	.set CYREG_B0_UDB07_08_ACTL, 0x4000692e
 2200              	.set CYREG_B0_UDB08_09_ACTL, 0x40006930
 2201              	.set CYREG_B0_UDB09_10_ACTL, 0x40006932
 2202              	.set CYREG_B0_UDB10_11_ACTL, 0x40006934
 2203              	.set CYREG_B0_UDB11_12_ACTL, 0x40006936
 2204              	.set CYREG_B0_UDB12_13_ACTL, 0x40006938
 2205              	.set CYREG_B0_UDB13_14_ACTL, 0x4000693a
 2206              	.set CYREG_B0_UDB14_15_ACTL, 0x4000693c
 2207              	.set CYREG_B0_UDB00_01_MC, 0x40006940
 2208              	.set CYREG_B0_UDB01_02_MC, 0x40006942
 2209              	.set CYREG_B0_UDB02_03_MC, 0x40006944
 2210              	.set CYREG_B0_UDB03_04_MC, 0x40006946
 2211              	.set CYREG_B0_UDB04_05_MC, 0x40006948
 2212              	.set CYREG_B0_UDB05_06_MC, 0x4000694a
 2213              	.set CYREG_B0_UDB06_07_MC, 0x4000694c
 2214              	.set CYREG_B0_UDB07_08_MC, 0x4000694e
 2215              	.set CYREG_B0_UDB08_09_MC, 0x40006950
 2216              	.set CYREG_B0_UDB09_10_MC, 0x40006952
 2217              	.set CYREG_B0_UDB10_11_MC, 0x40006954
 2218              	.set CYREG_B0_UDB11_12_MC, 0x40006956
 2219              	.set CYREG_B0_UDB12_13_MC, 0x40006958
 2220              	.set CYREG_B0_UDB13_14_MC, 0x4000695a
 2221              	.set CYREG_B0_UDB14_15_MC, 0x4000695c
 2222              	.set CYDEV_UWRK_UWRK16_DEF_B1_BASE, 0x40006a00
 2223              	.set CYDEV_UWRK_UWRK16_DEF_B1_SIZE, 0x0000015e
 2224              	.set CYREG_B1_UDB04_05_A0, 0x40006a08
 2225              	.set CYREG_B1_UDB05_06_A0, 0x40006a0a
 2226              	.set CYREG_B1_UDB06_07_A0, 0x40006a0c
 2227              	.set CYREG_B1_UDB07_08_A0, 0x40006a0e
 2228              	.set CYREG_B1_UDB08_09_A0, 0x40006a10
 2229              	.set CYREG_B1_UDB09_10_A0, 0x40006a12
 2230              	.set CYREG_B1_UDB10_11_A0, 0x40006a14
 2231              	.set CYREG_B1_UDB11_12_A0, 0x40006a16
 2232              	.set CYREG_B1_UDB04_05_A1, 0x40006a28
 2233              	.set CYREG_B1_UDB05_06_A1, 0x40006a2a
 2234              	.set CYREG_B1_UDB06_07_A1, 0x40006a2c
 2235              	.set CYREG_B1_UDB07_08_A1, 0x40006a2e
 2236              	.set CYREG_B1_UDB08_09_A1, 0x40006a30
 2237              	.set CYREG_B1_UDB09_10_A1, 0x40006a32
 2238              	.set CYREG_B1_UDB10_11_A1, 0x40006a34
 2239              	.set CYREG_B1_UDB11_12_A1, 0x40006a36
 2240              	.set CYREG_B1_UDB04_05_D0, 0x40006a48
 2241              	.set CYREG_B1_UDB05_06_D0, 0x40006a4a
 2242              	.set CYREG_B1_UDB06_07_D0, 0x40006a4c
 2243              	.set CYREG_B1_UDB07_08_D0, 0x40006a4e
 2244              	.set CYREG_B1_UDB08_09_D0, 0x40006a50
 2245              	.set CYREG_B1_UDB09_10_D0, 0x40006a52
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 135


 2246              	.set CYREG_B1_UDB10_11_D0, 0x40006a54
 2247              	.set CYREG_B1_UDB11_12_D0, 0x40006a56
 2248              	.set CYREG_B1_UDB04_05_D1, 0x40006a68
 2249              	.set CYREG_B1_UDB05_06_D1, 0x40006a6a
 2250              	.set CYREG_B1_UDB06_07_D1, 0x40006a6c
 2251              	.set CYREG_B1_UDB07_08_D1, 0x40006a6e
 2252              	.set CYREG_B1_UDB08_09_D1, 0x40006a70
 2253              	.set CYREG_B1_UDB09_10_D1, 0x40006a72
 2254              	.set CYREG_B1_UDB10_11_D1, 0x40006a74
 2255              	.set CYREG_B1_UDB11_12_D1, 0x40006a76
 2256              	.set CYREG_B1_UDB04_05_F0, 0x40006a88
 2257              	.set CYREG_B1_UDB05_06_F0, 0x40006a8a
 2258              	.set CYREG_B1_UDB06_07_F0, 0x40006a8c
 2259              	.set CYREG_B1_UDB07_08_F0, 0x40006a8e
 2260              	.set CYREG_B1_UDB08_09_F0, 0x40006a90
 2261              	.set CYREG_B1_UDB09_10_F0, 0x40006a92
 2262              	.set CYREG_B1_UDB10_11_F0, 0x40006a94
 2263              	.set CYREG_B1_UDB11_12_F0, 0x40006a96
 2264              	.set CYREG_B1_UDB04_05_F1, 0x40006aa8
 2265              	.set CYREG_B1_UDB05_06_F1, 0x40006aaa
 2266              	.set CYREG_B1_UDB06_07_F1, 0x40006aac
 2267              	.set CYREG_B1_UDB07_08_F1, 0x40006aae
 2268              	.set CYREG_B1_UDB08_09_F1, 0x40006ab0
 2269              	.set CYREG_B1_UDB09_10_F1, 0x40006ab2
 2270              	.set CYREG_B1_UDB10_11_F1, 0x40006ab4
 2271              	.set CYREG_B1_UDB11_12_F1, 0x40006ab6
 2272              	.set CYREG_B1_UDB04_05_ST, 0x40006ac8
 2273              	.set CYREG_B1_UDB05_06_ST, 0x40006aca
 2274              	.set CYREG_B1_UDB06_07_ST, 0x40006acc
 2275              	.set CYREG_B1_UDB07_08_ST, 0x40006ace
 2276              	.set CYREG_B1_UDB08_09_ST, 0x40006ad0
 2277              	.set CYREG_B1_UDB09_10_ST, 0x40006ad2
 2278              	.set CYREG_B1_UDB10_11_ST, 0x40006ad4
 2279              	.set CYREG_B1_UDB11_12_ST, 0x40006ad6
 2280              	.set CYREG_B1_UDB04_05_CTL, 0x40006ae8
 2281              	.set CYREG_B1_UDB05_06_CTL, 0x40006aea
 2282              	.set CYREG_B1_UDB06_07_CTL, 0x40006aec
 2283              	.set CYREG_B1_UDB07_08_CTL, 0x40006aee
 2284              	.set CYREG_B1_UDB08_09_CTL, 0x40006af0
 2285              	.set CYREG_B1_UDB09_10_CTL, 0x40006af2
 2286              	.set CYREG_B1_UDB10_11_CTL, 0x40006af4
 2287              	.set CYREG_B1_UDB11_12_CTL, 0x40006af6
 2288              	.set CYREG_B1_UDB04_05_MSK, 0x40006b08
 2289              	.set CYREG_B1_UDB05_06_MSK, 0x40006b0a
 2290              	.set CYREG_B1_UDB06_07_MSK, 0x40006b0c
 2291              	.set CYREG_B1_UDB07_08_MSK, 0x40006b0e
 2292              	.set CYREG_B1_UDB08_09_MSK, 0x40006b10
 2293              	.set CYREG_B1_UDB09_10_MSK, 0x40006b12
 2294              	.set CYREG_B1_UDB10_11_MSK, 0x40006b14
 2295              	.set CYREG_B1_UDB11_12_MSK, 0x40006b16
 2296              	.set CYREG_B1_UDB04_05_ACTL, 0x40006b28
 2297              	.set CYREG_B1_UDB05_06_ACTL, 0x40006b2a
 2298              	.set CYREG_B1_UDB06_07_ACTL, 0x40006b2c
 2299              	.set CYREG_B1_UDB07_08_ACTL, 0x40006b2e
 2300              	.set CYREG_B1_UDB08_09_ACTL, 0x40006b30
 2301              	.set CYREG_B1_UDB09_10_ACTL, 0x40006b32
 2302              	.set CYREG_B1_UDB10_11_ACTL, 0x40006b34
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 136


 2303              	.set CYREG_B1_UDB11_12_ACTL, 0x40006b36
 2304              	.set CYREG_B1_UDB04_05_MC, 0x40006b48
 2305              	.set CYREG_B1_UDB05_06_MC, 0x40006b4a
 2306              	.set CYREG_B1_UDB06_07_MC, 0x40006b4c
 2307              	.set CYREG_B1_UDB07_08_MC, 0x40006b4e
 2308              	.set CYREG_B1_UDB08_09_MC, 0x40006b50
 2309              	.set CYREG_B1_UDB09_10_MC, 0x40006b52
 2310              	.set CYREG_B1_UDB10_11_MC, 0x40006b54
 2311              	.set CYREG_B1_UDB11_12_MC, 0x40006b56
 2312              	.set CYDEV_PHUB_BASE, 0x40007000
 2313              	.set CYDEV_PHUB_SIZE, 0x00000c00
 2314              	.set CYREG_PHUB_CFG, 0x40007000
 2315              	.set CYREG_PHUB_ERR, 0x40007004
 2316              	.set CYREG_PHUB_ERR_ADR, 0x40007008
 2317              	.set CYDEV_PHUB_CH0_BASE, 0x40007010
 2318              	.set CYDEV_PHUB_CH0_SIZE, 0x0000000c
 2319              	.set CYREG_PHUB_CH0_BASIC_CFG, 0x40007010
 2320              	.set CYREG_PHUB_CH0_ACTION, 0x40007014
 2321              	.set CYREG_PHUB_CH0_BASIC_STATUS, 0x40007018
 2322              	.set CYDEV_PHUB_CH1_BASE, 0x40007020
 2323              	.set CYDEV_PHUB_CH1_SIZE, 0x0000000c
 2324              	.set CYREG_PHUB_CH1_BASIC_CFG, 0x40007020
 2325              	.set CYREG_PHUB_CH1_ACTION, 0x40007024
 2326              	.set CYREG_PHUB_CH1_BASIC_STATUS, 0x40007028
 2327              	.set CYDEV_PHUB_CH2_BASE, 0x40007030
 2328              	.set CYDEV_PHUB_CH2_SIZE, 0x0000000c
 2329              	.set CYREG_PHUB_CH2_BASIC_CFG, 0x40007030
 2330              	.set CYREG_PHUB_CH2_ACTION, 0x40007034
 2331              	.set CYREG_PHUB_CH2_BASIC_STATUS, 0x40007038
 2332              	.set CYDEV_PHUB_CH3_BASE, 0x40007040
 2333              	.set CYDEV_PHUB_CH3_SIZE, 0x0000000c
 2334              	.set CYREG_PHUB_CH3_BASIC_CFG, 0x40007040
 2335              	.set CYREG_PHUB_CH3_ACTION, 0x40007044
 2336              	.set CYREG_PHUB_CH3_BASIC_STATUS, 0x40007048
 2337              	.set CYDEV_PHUB_CH4_BASE, 0x40007050
 2338              	.set CYDEV_PHUB_CH4_SIZE, 0x0000000c
 2339              	.set CYREG_PHUB_CH4_BASIC_CFG, 0x40007050
 2340              	.set CYREG_PHUB_CH4_ACTION, 0x40007054
 2341              	.set CYREG_PHUB_CH4_BASIC_STATUS, 0x40007058
 2342              	.set CYDEV_PHUB_CH5_BASE, 0x40007060
 2343              	.set CYDEV_PHUB_CH5_SIZE, 0x0000000c
 2344              	.set CYREG_PHUB_CH5_BASIC_CFG, 0x40007060
 2345              	.set CYREG_PHUB_CH5_ACTION, 0x40007064
 2346              	.set CYREG_PHUB_CH5_BASIC_STATUS, 0x40007068
 2347              	.set CYDEV_PHUB_CH6_BASE, 0x40007070
 2348              	.set CYDEV_PHUB_CH6_SIZE, 0x0000000c
 2349              	.set CYREG_PHUB_CH6_BASIC_CFG, 0x40007070
 2350              	.set CYREG_PHUB_CH6_ACTION, 0x40007074
 2351              	.set CYREG_PHUB_CH6_BASIC_STATUS, 0x40007078
 2352              	.set CYDEV_PHUB_CH7_BASE, 0x40007080
 2353              	.set CYDEV_PHUB_CH7_SIZE, 0x0000000c
 2354              	.set CYREG_PHUB_CH7_BASIC_CFG, 0x40007080
 2355              	.set CYREG_PHUB_CH7_ACTION, 0x40007084
 2356              	.set CYREG_PHUB_CH7_BASIC_STATUS, 0x40007088
 2357              	.set CYDEV_PHUB_CH8_BASE, 0x40007090
 2358              	.set CYDEV_PHUB_CH8_SIZE, 0x0000000c
 2359              	.set CYREG_PHUB_CH8_BASIC_CFG, 0x40007090
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 137


 2360              	.set CYREG_PHUB_CH8_ACTION, 0x40007094
 2361              	.set CYREG_PHUB_CH8_BASIC_STATUS, 0x40007098
 2362              	.set CYDEV_PHUB_CH9_BASE, 0x400070a0
 2363              	.set CYDEV_PHUB_CH9_SIZE, 0x0000000c
 2364              	.set CYREG_PHUB_CH9_BASIC_CFG, 0x400070a0
 2365              	.set CYREG_PHUB_CH9_ACTION, 0x400070a4
 2366              	.set CYREG_PHUB_CH9_BASIC_STATUS, 0x400070a8
 2367              	.set CYDEV_PHUB_CH10_BASE, 0x400070b0
 2368              	.set CYDEV_PHUB_CH10_SIZE, 0x0000000c
 2369              	.set CYREG_PHUB_CH10_BASIC_CFG, 0x400070b0
 2370              	.set CYREG_PHUB_CH10_ACTION, 0x400070b4
 2371              	.set CYREG_PHUB_CH10_BASIC_STATUS, 0x400070b8
 2372              	.set CYDEV_PHUB_CH11_BASE, 0x400070c0
 2373              	.set CYDEV_PHUB_CH11_SIZE, 0x0000000c
 2374              	.set CYREG_PHUB_CH11_BASIC_CFG, 0x400070c0
 2375              	.set CYREG_PHUB_CH11_ACTION, 0x400070c4
 2376              	.set CYREG_PHUB_CH11_BASIC_STATUS, 0x400070c8
 2377              	.set CYDEV_PHUB_CH12_BASE, 0x400070d0
 2378              	.set CYDEV_PHUB_CH12_SIZE, 0x0000000c
 2379              	.set CYREG_PHUB_CH12_BASIC_CFG, 0x400070d0
 2380              	.set CYREG_PHUB_CH12_ACTION, 0x400070d4
 2381              	.set CYREG_PHUB_CH12_BASIC_STATUS, 0x400070d8
 2382              	.set CYDEV_PHUB_CH13_BASE, 0x400070e0
 2383              	.set CYDEV_PHUB_CH13_SIZE, 0x0000000c
 2384              	.set CYREG_PHUB_CH13_BASIC_CFG, 0x400070e0
 2385              	.set CYREG_PHUB_CH13_ACTION, 0x400070e4
 2386              	.set CYREG_PHUB_CH13_BASIC_STATUS, 0x400070e8
 2387              	.set CYDEV_PHUB_CH14_BASE, 0x400070f0
 2388              	.set CYDEV_PHUB_CH14_SIZE, 0x0000000c
 2389              	.set CYREG_PHUB_CH14_BASIC_CFG, 0x400070f0
 2390              	.set CYREG_PHUB_CH14_ACTION, 0x400070f4
 2391              	.set CYREG_PHUB_CH14_BASIC_STATUS, 0x400070f8
 2392              	.set CYDEV_PHUB_CH15_BASE, 0x40007100
 2393              	.set CYDEV_PHUB_CH15_SIZE, 0x0000000c
 2394              	.set CYREG_PHUB_CH15_BASIC_CFG, 0x40007100
 2395              	.set CYREG_PHUB_CH15_ACTION, 0x40007104
 2396              	.set CYREG_PHUB_CH15_BASIC_STATUS, 0x40007108
 2397              	.set CYDEV_PHUB_CH16_BASE, 0x40007110
 2398              	.set CYDEV_PHUB_CH16_SIZE, 0x0000000c
 2399              	.set CYREG_PHUB_CH16_BASIC_CFG, 0x40007110
 2400              	.set CYREG_PHUB_CH16_ACTION, 0x40007114
 2401              	.set CYREG_PHUB_CH16_BASIC_STATUS, 0x40007118
 2402              	.set CYDEV_PHUB_CH17_BASE, 0x40007120
 2403              	.set CYDEV_PHUB_CH17_SIZE, 0x0000000c
 2404              	.set CYREG_PHUB_CH17_BASIC_CFG, 0x40007120
 2405              	.set CYREG_PHUB_CH17_ACTION, 0x40007124
 2406              	.set CYREG_PHUB_CH17_BASIC_STATUS, 0x40007128
 2407              	.set CYDEV_PHUB_CH18_BASE, 0x40007130
 2408              	.set CYDEV_PHUB_CH18_SIZE, 0x0000000c
 2409              	.set CYREG_PHUB_CH18_BASIC_CFG, 0x40007130
 2410              	.set CYREG_PHUB_CH18_ACTION, 0x40007134
 2411              	.set CYREG_PHUB_CH18_BASIC_STATUS, 0x40007138
 2412              	.set CYDEV_PHUB_CH19_BASE, 0x40007140
 2413              	.set CYDEV_PHUB_CH19_SIZE, 0x0000000c
 2414              	.set CYREG_PHUB_CH19_BASIC_CFG, 0x40007140
 2415              	.set CYREG_PHUB_CH19_ACTION, 0x40007144
 2416              	.set CYREG_PHUB_CH19_BASIC_STATUS, 0x40007148
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 138


 2417              	.set CYDEV_PHUB_CH20_BASE, 0x40007150
 2418              	.set CYDEV_PHUB_CH20_SIZE, 0x0000000c
 2419              	.set CYREG_PHUB_CH20_BASIC_CFG, 0x40007150
 2420              	.set CYREG_PHUB_CH20_ACTION, 0x40007154
 2421              	.set CYREG_PHUB_CH20_BASIC_STATUS, 0x40007158
 2422              	.set CYDEV_PHUB_CH21_BASE, 0x40007160
 2423              	.set CYDEV_PHUB_CH21_SIZE, 0x0000000c
 2424              	.set CYREG_PHUB_CH21_BASIC_CFG, 0x40007160
 2425              	.set CYREG_PHUB_CH21_ACTION, 0x40007164
 2426              	.set CYREG_PHUB_CH21_BASIC_STATUS, 0x40007168
 2427              	.set CYDEV_PHUB_CH22_BASE, 0x40007170
 2428              	.set CYDEV_PHUB_CH22_SIZE, 0x0000000c
 2429              	.set CYREG_PHUB_CH22_BASIC_CFG, 0x40007170
 2430              	.set CYREG_PHUB_CH22_ACTION, 0x40007174
 2431              	.set CYREG_PHUB_CH22_BASIC_STATUS, 0x40007178
 2432              	.set CYDEV_PHUB_CH23_BASE, 0x40007180
 2433              	.set CYDEV_PHUB_CH23_SIZE, 0x0000000c
 2434              	.set CYREG_PHUB_CH23_BASIC_CFG, 0x40007180
 2435              	.set CYREG_PHUB_CH23_ACTION, 0x40007184
 2436              	.set CYREG_PHUB_CH23_BASIC_STATUS, 0x40007188
 2437              	.set CYDEV_PHUB_CFGMEM0_BASE, 0x40007600
 2438              	.set CYDEV_PHUB_CFGMEM0_SIZE, 0x00000008
 2439              	.set CYREG_PHUB_CFGMEM0_CFG0, 0x40007600
 2440              	.set CYREG_PHUB_CFGMEM0_CFG1, 0x40007604
 2441              	.set CYDEV_PHUB_CFGMEM1_BASE, 0x40007608
 2442              	.set CYDEV_PHUB_CFGMEM1_SIZE, 0x00000008
 2443              	.set CYREG_PHUB_CFGMEM1_CFG0, 0x40007608
 2444              	.set CYREG_PHUB_CFGMEM1_CFG1, 0x4000760c
 2445              	.set CYDEV_PHUB_CFGMEM2_BASE, 0x40007610
 2446              	.set CYDEV_PHUB_CFGMEM2_SIZE, 0x00000008
 2447              	.set CYREG_PHUB_CFGMEM2_CFG0, 0x40007610
 2448              	.set CYREG_PHUB_CFGMEM2_CFG1, 0x40007614
 2449              	.set CYDEV_PHUB_CFGMEM3_BASE, 0x40007618
 2450              	.set CYDEV_PHUB_CFGMEM3_SIZE, 0x00000008
 2451              	.set CYREG_PHUB_CFGMEM3_CFG0, 0x40007618
 2452              	.set CYREG_PHUB_CFGMEM3_CFG1, 0x4000761c
 2453              	.set CYDEV_PHUB_CFGMEM4_BASE, 0x40007620
 2454              	.set CYDEV_PHUB_CFGMEM4_SIZE, 0x00000008
 2455              	.set CYREG_PHUB_CFGMEM4_CFG0, 0x40007620
 2456              	.set CYREG_PHUB_CFGMEM4_CFG1, 0x40007624
 2457              	.set CYDEV_PHUB_CFGMEM5_BASE, 0x40007628
 2458              	.set CYDEV_PHUB_CFGMEM5_SIZE, 0x00000008
 2459              	.set CYREG_PHUB_CFGMEM5_CFG0, 0x40007628
 2460              	.set CYREG_PHUB_CFGMEM5_CFG1, 0x4000762c
 2461              	.set CYDEV_PHUB_CFGMEM6_BASE, 0x40007630
 2462              	.set CYDEV_PHUB_CFGMEM6_SIZE, 0x00000008
 2463              	.set CYREG_PHUB_CFGMEM6_CFG0, 0x40007630
 2464              	.set CYREG_PHUB_CFGMEM6_CFG1, 0x40007634
 2465              	.set CYDEV_PHUB_CFGMEM7_BASE, 0x40007638
 2466              	.set CYDEV_PHUB_CFGMEM7_SIZE, 0x00000008
 2467              	.set CYREG_PHUB_CFGMEM7_CFG0, 0x40007638
 2468              	.set CYREG_PHUB_CFGMEM7_CFG1, 0x4000763c
 2469              	.set CYDEV_PHUB_CFGMEM8_BASE, 0x40007640
 2470              	.set CYDEV_PHUB_CFGMEM8_SIZE, 0x00000008
 2471              	.set CYREG_PHUB_CFGMEM8_CFG0, 0x40007640
 2472              	.set CYREG_PHUB_CFGMEM8_CFG1, 0x40007644
 2473              	.set CYDEV_PHUB_CFGMEM9_BASE, 0x40007648
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 139


 2474              	.set CYDEV_PHUB_CFGMEM9_SIZE, 0x00000008
 2475              	.set CYREG_PHUB_CFGMEM9_CFG0, 0x40007648
 2476              	.set CYREG_PHUB_CFGMEM9_CFG1, 0x4000764c
 2477              	.set CYDEV_PHUB_CFGMEM10_BASE, 0x40007650
 2478              	.set CYDEV_PHUB_CFGMEM10_SIZE, 0x00000008
 2479              	.set CYREG_PHUB_CFGMEM10_CFG0, 0x40007650
 2480              	.set CYREG_PHUB_CFGMEM10_CFG1, 0x40007654
 2481              	.set CYDEV_PHUB_CFGMEM11_BASE, 0x40007658
 2482              	.set CYDEV_PHUB_CFGMEM11_SIZE, 0x00000008
 2483              	.set CYREG_PHUB_CFGMEM11_CFG0, 0x40007658
 2484              	.set CYREG_PHUB_CFGMEM11_CFG1, 0x4000765c
 2485              	.set CYDEV_PHUB_CFGMEM12_BASE, 0x40007660
 2486              	.set CYDEV_PHUB_CFGMEM12_SIZE, 0x00000008
 2487              	.set CYREG_PHUB_CFGMEM12_CFG0, 0x40007660
 2488              	.set CYREG_PHUB_CFGMEM12_CFG1, 0x40007664
 2489              	.set CYDEV_PHUB_CFGMEM13_BASE, 0x40007668
 2490              	.set CYDEV_PHUB_CFGMEM13_SIZE, 0x00000008
 2491              	.set CYREG_PHUB_CFGMEM13_CFG0, 0x40007668
 2492              	.set CYREG_PHUB_CFGMEM13_CFG1, 0x4000766c
 2493              	.set CYDEV_PHUB_CFGMEM14_BASE, 0x40007670
 2494              	.set CYDEV_PHUB_CFGMEM14_SIZE, 0x00000008
 2495              	.set CYREG_PHUB_CFGMEM14_CFG0, 0x40007670
 2496              	.set CYREG_PHUB_CFGMEM14_CFG1, 0x40007674
 2497              	.set CYDEV_PHUB_CFGMEM15_BASE, 0x40007678
 2498              	.set CYDEV_PHUB_CFGMEM15_SIZE, 0x00000008
 2499              	.set CYREG_PHUB_CFGMEM15_CFG0, 0x40007678
 2500              	.set CYREG_PHUB_CFGMEM15_CFG1, 0x4000767c
 2501              	.set CYDEV_PHUB_CFGMEM16_BASE, 0x40007680
 2502              	.set CYDEV_PHUB_CFGMEM16_SIZE, 0x00000008
 2503              	.set CYREG_PHUB_CFGMEM16_CFG0, 0x40007680
 2504              	.set CYREG_PHUB_CFGMEM16_CFG1, 0x40007684
 2505              	.set CYDEV_PHUB_CFGMEM17_BASE, 0x40007688
 2506              	.set CYDEV_PHUB_CFGMEM17_SIZE, 0x00000008
 2507              	.set CYREG_PHUB_CFGMEM17_CFG0, 0x40007688
 2508              	.set CYREG_PHUB_CFGMEM17_CFG1, 0x4000768c
 2509              	.set CYDEV_PHUB_CFGMEM18_BASE, 0x40007690
 2510              	.set CYDEV_PHUB_CFGMEM18_SIZE, 0x00000008
 2511              	.set CYREG_PHUB_CFGMEM18_CFG0, 0x40007690
 2512              	.set CYREG_PHUB_CFGMEM18_CFG1, 0x40007694
 2513              	.set CYDEV_PHUB_CFGMEM19_BASE, 0x40007698
 2514              	.set CYDEV_PHUB_CFGMEM19_SIZE, 0x00000008
 2515              	.set CYREG_PHUB_CFGMEM19_CFG0, 0x40007698
 2516              	.set CYREG_PHUB_CFGMEM19_CFG1, 0x4000769c
 2517              	.set CYDEV_PHUB_CFGMEM20_BASE, 0x400076a0
 2518              	.set CYDEV_PHUB_CFGMEM20_SIZE, 0x00000008
 2519              	.set CYREG_PHUB_CFGMEM20_CFG0, 0x400076a0
 2520              	.set CYREG_PHUB_CFGMEM20_CFG1, 0x400076a4
 2521              	.set CYDEV_PHUB_CFGMEM21_BASE, 0x400076a8
 2522              	.set CYDEV_PHUB_CFGMEM21_SIZE, 0x00000008
 2523              	.set CYREG_PHUB_CFGMEM21_CFG0, 0x400076a8
 2524              	.set CYREG_PHUB_CFGMEM21_CFG1, 0x400076ac
 2525              	.set CYDEV_PHUB_CFGMEM22_BASE, 0x400076b0
 2526              	.set CYDEV_PHUB_CFGMEM22_SIZE, 0x00000008
 2527              	.set CYREG_PHUB_CFGMEM22_CFG0, 0x400076b0
 2528              	.set CYREG_PHUB_CFGMEM22_CFG1, 0x400076b4
 2529              	.set CYDEV_PHUB_CFGMEM23_BASE, 0x400076b8
 2530              	.set CYDEV_PHUB_CFGMEM23_SIZE, 0x00000008
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 140


 2531              	.set CYREG_PHUB_CFGMEM23_CFG0, 0x400076b8
 2532              	.set CYREG_PHUB_CFGMEM23_CFG1, 0x400076bc
 2533              	.set CYDEV_PHUB_TDMEM0_BASE, 0x40007800
 2534              	.set CYDEV_PHUB_TDMEM0_SIZE, 0x00000008
 2535              	.set CYREG_PHUB_TDMEM0_ORIG_TD0, 0x40007800
 2536              	.set CYREG_PHUB_TDMEM0_ORIG_TD1, 0x40007804
 2537              	.set CYDEV_PHUB_TDMEM1_BASE, 0x40007808
 2538              	.set CYDEV_PHUB_TDMEM1_SIZE, 0x00000008
 2539              	.set CYREG_PHUB_TDMEM1_ORIG_TD0, 0x40007808
 2540              	.set CYREG_PHUB_TDMEM1_ORIG_TD1, 0x4000780c
 2541              	.set CYDEV_PHUB_TDMEM2_BASE, 0x40007810
 2542              	.set CYDEV_PHUB_TDMEM2_SIZE, 0x00000008
 2543              	.set CYREG_PHUB_TDMEM2_ORIG_TD0, 0x40007810
 2544              	.set CYREG_PHUB_TDMEM2_ORIG_TD1, 0x40007814
 2545              	.set CYDEV_PHUB_TDMEM3_BASE, 0x40007818
 2546              	.set CYDEV_PHUB_TDMEM3_SIZE, 0x00000008
 2547              	.set CYREG_PHUB_TDMEM3_ORIG_TD0, 0x40007818
 2548              	.set CYREG_PHUB_TDMEM3_ORIG_TD1, 0x4000781c
 2549              	.set CYDEV_PHUB_TDMEM4_BASE, 0x40007820
 2550              	.set CYDEV_PHUB_TDMEM4_SIZE, 0x00000008
 2551              	.set CYREG_PHUB_TDMEM4_ORIG_TD0, 0x40007820
 2552              	.set CYREG_PHUB_TDMEM4_ORIG_TD1, 0x40007824
 2553              	.set CYDEV_PHUB_TDMEM5_BASE, 0x40007828
 2554              	.set CYDEV_PHUB_TDMEM5_SIZE, 0x00000008
 2555              	.set CYREG_PHUB_TDMEM5_ORIG_TD0, 0x40007828
 2556              	.set CYREG_PHUB_TDMEM5_ORIG_TD1, 0x4000782c
 2557              	.set CYDEV_PHUB_TDMEM6_BASE, 0x40007830
 2558              	.set CYDEV_PHUB_TDMEM6_SIZE, 0x00000008
 2559              	.set CYREG_PHUB_TDMEM6_ORIG_TD0, 0x40007830
 2560              	.set CYREG_PHUB_TDMEM6_ORIG_TD1, 0x40007834
 2561              	.set CYDEV_PHUB_TDMEM7_BASE, 0x40007838
 2562              	.set CYDEV_PHUB_TDMEM7_SIZE, 0x00000008
 2563              	.set CYREG_PHUB_TDMEM7_ORIG_TD0, 0x40007838
 2564              	.set CYREG_PHUB_TDMEM7_ORIG_TD1, 0x4000783c
 2565              	.set CYDEV_PHUB_TDMEM8_BASE, 0x40007840
 2566              	.set CYDEV_PHUB_TDMEM8_SIZE, 0x00000008
 2567              	.set CYREG_PHUB_TDMEM8_ORIG_TD0, 0x40007840
 2568              	.set CYREG_PHUB_TDMEM8_ORIG_TD1, 0x40007844
 2569              	.set CYDEV_PHUB_TDMEM9_BASE, 0x40007848
 2570              	.set CYDEV_PHUB_TDMEM9_SIZE, 0x00000008
 2571              	.set CYREG_PHUB_TDMEM9_ORIG_TD0, 0x40007848
 2572              	.set CYREG_PHUB_TDMEM9_ORIG_TD1, 0x4000784c
 2573              	.set CYDEV_PHUB_TDMEM10_BASE, 0x40007850
 2574              	.set CYDEV_PHUB_TDMEM10_SIZE, 0x00000008
 2575              	.set CYREG_PHUB_TDMEM10_ORIG_TD0, 0x40007850
 2576              	.set CYREG_PHUB_TDMEM10_ORIG_TD1, 0x40007854
 2577              	.set CYDEV_PHUB_TDMEM11_BASE, 0x40007858
 2578              	.set CYDEV_PHUB_TDMEM11_SIZE, 0x00000008
 2579              	.set CYREG_PHUB_TDMEM11_ORIG_TD0, 0x40007858
 2580              	.set CYREG_PHUB_TDMEM11_ORIG_TD1, 0x4000785c
 2581              	.set CYDEV_PHUB_TDMEM12_BASE, 0x40007860
 2582              	.set CYDEV_PHUB_TDMEM12_SIZE, 0x00000008
 2583              	.set CYREG_PHUB_TDMEM12_ORIG_TD0, 0x40007860
 2584              	.set CYREG_PHUB_TDMEM12_ORIG_TD1, 0x40007864
 2585              	.set CYDEV_PHUB_TDMEM13_BASE, 0x40007868
 2586              	.set CYDEV_PHUB_TDMEM13_SIZE, 0x00000008
 2587              	.set CYREG_PHUB_TDMEM13_ORIG_TD0, 0x40007868
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 141


 2588              	.set CYREG_PHUB_TDMEM13_ORIG_TD1, 0x4000786c
 2589              	.set CYDEV_PHUB_TDMEM14_BASE, 0x40007870
 2590              	.set CYDEV_PHUB_TDMEM14_SIZE, 0x00000008
 2591              	.set CYREG_PHUB_TDMEM14_ORIG_TD0, 0x40007870
 2592              	.set CYREG_PHUB_TDMEM14_ORIG_TD1, 0x40007874
 2593              	.set CYDEV_PHUB_TDMEM15_BASE, 0x40007878
 2594              	.set CYDEV_PHUB_TDMEM15_SIZE, 0x00000008
 2595              	.set CYREG_PHUB_TDMEM15_ORIG_TD0, 0x40007878
 2596              	.set CYREG_PHUB_TDMEM15_ORIG_TD1, 0x4000787c
 2597              	.set CYDEV_PHUB_TDMEM16_BASE, 0x40007880
 2598              	.set CYDEV_PHUB_TDMEM16_SIZE, 0x00000008
 2599              	.set CYREG_PHUB_TDMEM16_ORIG_TD0, 0x40007880
 2600              	.set CYREG_PHUB_TDMEM16_ORIG_TD1, 0x40007884
 2601              	.set CYDEV_PHUB_TDMEM17_BASE, 0x40007888
 2602              	.set CYDEV_PHUB_TDMEM17_SIZE, 0x00000008
 2603              	.set CYREG_PHUB_TDMEM17_ORIG_TD0, 0x40007888
 2604              	.set CYREG_PHUB_TDMEM17_ORIG_TD1, 0x4000788c
 2605              	.set CYDEV_PHUB_TDMEM18_BASE, 0x40007890
 2606              	.set CYDEV_PHUB_TDMEM18_SIZE, 0x00000008
 2607              	.set CYREG_PHUB_TDMEM18_ORIG_TD0, 0x40007890
 2608              	.set CYREG_PHUB_TDMEM18_ORIG_TD1, 0x40007894
 2609              	.set CYDEV_PHUB_TDMEM19_BASE, 0x40007898
 2610              	.set CYDEV_PHUB_TDMEM19_SIZE, 0x00000008
 2611              	.set CYREG_PHUB_TDMEM19_ORIG_TD0, 0x40007898
 2612              	.set CYREG_PHUB_TDMEM19_ORIG_TD1, 0x4000789c
 2613              	.set CYDEV_PHUB_TDMEM20_BASE, 0x400078a0
 2614              	.set CYDEV_PHUB_TDMEM20_SIZE, 0x00000008
 2615              	.set CYREG_PHUB_TDMEM20_ORIG_TD0, 0x400078a0
 2616              	.set CYREG_PHUB_TDMEM20_ORIG_TD1, 0x400078a4
 2617              	.set CYDEV_PHUB_TDMEM21_BASE, 0x400078a8
 2618              	.set CYDEV_PHUB_TDMEM21_SIZE, 0x00000008
 2619              	.set CYREG_PHUB_TDMEM21_ORIG_TD0, 0x400078a8
 2620              	.set CYREG_PHUB_TDMEM21_ORIG_TD1, 0x400078ac
 2621              	.set CYDEV_PHUB_TDMEM22_BASE, 0x400078b0
 2622              	.set CYDEV_PHUB_TDMEM22_SIZE, 0x00000008
 2623              	.set CYREG_PHUB_TDMEM22_ORIG_TD0, 0x400078b0
 2624              	.set CYREG_PHUB_TDMEM22_ORIG_TD1, 0x400078b4
 2625              	.set CYDEV_PHUB_TDMEM23_BASE, 0x400078b8
 2626              	.set CYDEV_PHUB_TDMEM23_SIZE, 0x00000008
 2627              	.set CYREG_PHUB_TDMEM23_ORIG_TD0, 0x400078b8
 2628              	.set CYREG_PHUB_TDMEM23_ORIG_TD1, 0x400078bc
 2629              	.set CYDEV_PHUB_TDMEM24_BASE, 0x400078c0
 2630              	.set CYDEV_PHUB_TDMEM24_SIZE, 0x00000008
 2631              	.set CYREG_PHUB_TDMEM24_ORIG_TD0, 0x400078c0
 2632              	.set CYREG_PHUB_TDMEM24_ORIG_TD1, 0x400078c4
 2633              	.set CYDEV_PHUB_TDMEM25_BASE, 0x400078c8
 2634              	.set CYDEV_PHUB_TDMEM25_SIZE, 0x00000008
 2635              	.set CYREG_PHUB_TDMEM25_ORIG_TD0, 0x400078c8
 2636              	.set CYREG_PHUB_TDMEM25_ORIG_TD1, 0x400078cc
 2637              	.set CYDEV_PHUB_TDMEM26_BASE, 0x400078d0
 2638              	.set CYDEV_PHUB_TDMEM26_SIZE, 0x00000008
 2639              	.set CYREG_PHUB_TDMEM26_ORIG_TD0, 0x400078d0
 2640              	.set CYREG_PHUB_TDMEM26_ORIG_TD1, 0x400078d4
 2641              	.set CYDEV_PHUB_TDMEM27_BASE, 0x400078d8
 2642              	.set CYDEV_PHUB_TDMEM27_SIZE, 0x00000008
 2643              	.set CYREG_PHUB_TDMEM27_ORIG_TD0, 0x400078d8
 2644              	.set CYREG_PHUB_TDMEM27_ORIG_TD1, 0x400078dc
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 142


 2645              	.set CYDEV_PHUB_TDMEM28_BASE, 0x400078e0
 2646              	.set CYDEV_PHUB_TDMEM28_SIZE, 0x00000008
 2647              	.set CYREG_PHUB_TDMEM28_ORIG_TD0, 0x400078e0
 2648              	.set CYREG_PHUB_TDMEM28_ORIG_TD1, 0x400078e4
 2649              	.set CYDEV_PHUB_TDMEM29_BASE, 0x400078e8
 2650              	.set CYDEV_PHUB_TDMEM29_SIZE, 0x00000008
 2651              	.set CYREG_PHUB_TDMEM29_ORIG_TD0, 0x400078e8
 2652              	.set CYREG_PHUB_TDMEM29_ORIG_TD1, 0x400078ec
 2653              	.set CYDEV_PHUB_TDMEM30_BASE, 0x400078f0
 2654              	.set CYDEV_PHUB_TDMEM30_SIZE, 0x00000008
 2655              	.set CYREG_PHUB_TDMEM30_ORIG_TD0, 0x400078f0
 2656              	.set CYREG_PHUB_TDMEM30_ORIG_TD1, 0x400078f4
 2657              	.set CYDEV_PHUB_TDMEM31_BASE, 0x400078f8
 2658              	.set CYDEV_PHUB_TDMEM31_SIZE, 0x00000008
 2659              	.set CYREG_PHUB_TDMEM31_ORIG_TD0, 0x400078f8
 2660              	.set CYREG_PHUB_TDMEM31_ORIG_TD1, 0x400078fc
 2661              	.set CYDEV_PHUB_TDMEM32_BASE, 0x40007900
 2662              	.set CYDEV_PHUB_TDMEM32_SIZE, 0x00000008
 2663              	.set CYREG_PHUB_TDMEM32_ORIG_TD0, 0x40007900
 2664              	.set CYREG_PHUB_TDMEM32_ORIG_TD1, 0x40007904
 2665              	.set CYDEV_PHUB_TDMEM33_BASE, 0x40007908
 2666              	.set CYDEV_PHUB_TDMEM33_SIZE, 0x00000008
 2667              	.set CYREG_PHUB_TDMEM33_ORIG_TD0, 0x40007908
 2668              	.set CYREG_PHUB_TDMEM33_ORIG_TD1, 0x4000790c
 2669              	.set CYDEV_PHUB_TDMEM34_BASE, 0x40007910
 2670              	.set CYDEV_PHUB_TDMEM34_SIZE, 0x00000008
 2671              	.set CYREG_PHUB_TDMEM34_ORIG_TD0, 0x40007910
 2672              	.set CYREG_PHUB_TDMEM34_ORIG_TD1, 0x40007914
 2673              	.set CYDEV_PHUB_TDMEM35_BASE, 0x40007918
 2674              	.set CYDEV_PHUB_TDMEM35_SIZE, 0x00000008
 2675              	.set CYREG_PHUB_TDMEM35_ORIG_TD0, 0x40007918
 2676              	.set CYREG_PHUB_TDMEM35_ORIG_TD1, 0x4000791c
 2677              	.set CYDEV_PHUB_TDMEM36_BASE, 0x40007920
 2678              	.set CYDEV_PHUB_TDMEM36_SIZE, 0x00000008
 2679              	.set CYREG_PHUB_TDMEM36_ORIG_TD0, 0x40007920
 2680              	.set CYREG_PHUB_TDMEM36_ORIG_TD1, 0x40007924
 2681              	.set CYDEV_PHUB_TDMEM37_BASE, 0x40007928
 2682              	.set CYDEV_PHUB_TDMEM37_SIZE, 0x00000008
 2683              	.set CYREG_PHUB_TDMEM37_ORIG_TD0, 0x40007928
 2684              	.set CYREG_PHUB_TDMEM37_ORIG_TD1, 0x4000792c
 2685              	.set CYDEV_PHUB_TDMEM38_BASE, 0x40007930
 2686              	.set CYDEV_PHUB_TDMEM38_SIZE, 0x00000008
 2687              	.set CYREG_PHUB_TDMEM38_ORIG_TD0, 0x40007930
 2688              	.set CYREG_PHUB_TDMEM38_ORIG_TD1, 0x40007934
 2689              	.set CYDEV_PHUB_TDMEM39_BASE, 0x40007938
 2690              	.set CYDEV_PHUB_TDMEM39_SIZE, 0x00000008
 2691              	.set CYREG_PHUB_TDMEM39_ORIG_TD0, 0x40007938
 2692              	.set CYREG_PHUB_TDMEM39_ORIG_TD1, 0x4000793c
 2693              	.set CYDEV_PHUB_TDMEM40_BASE, 0x40007940
 2694              	.set CYDEV_PHUB_TDMEM40_SIZE, 0x00000008
 2695              	.set CYREG_PHUB_TDMEM40_ORIG_TD0, 0x40007940
 2696              	.set CYREG_PHUB_TDMEM40_ORIG_TD1, 0x40007944
 2697              	.set CYDEV_PHUB_TDMEM41_BASE, 0x40007948
 2698              	.set CYDEV_PHUB_TDMEM41_SIZE, 0x00000008
 2699              	.set CYREG_PHUB_TDMEM41_ORIG_TD0, 0x40007948
 2700              	.set CYREG_PHUB_TDMEM41_ORIG_TD1, 0x4000794c
 2701              	.set CYDEV_PHUB_TDMEM42_BASE, 0x40007950
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 143


 2702              	.set CYDEV_PHUB_TDMEM42_SIZE, 0x00000008
 2703              	.set CYREG_PHUB_TDMEM42_ORIG_TD0, 0x40007950
 2704              	.set CYREG_PHUB_TDMEM42_ORIG_TD1, 0x40007954
 2705              	.set CYDEV_PHUB_TDMEM43_BASE, 0x40007958
 2706              	.set CYDEV_PHUB_TDMEM43_SIZE, 0x00000008
 2707              	.set CYREG_PHUB_TDMEM43_ORIG_TD0, 0x40007958
 2708              	.set CYREG_PHUB_TDMEM43_ORIG_TD1, 0x4000795c
 2709              	.set CYDEV_PHUB_TDMEM44_BASE, 0x40007960
 2710              	.set CYDEV_PHUB_TDMEM44_SIZE, 0x00000008
 2711              	.set CYREG_PHUB_TDMEM44_ORIG_TD0, 0x40007960
 2712              	.set CYREG_PHUB_TDMEM44_ORIG_TD1, 0x40007964
 2713              	.set CYDEV_PHUB_TDMEM45_BASE, 0x40007968
 2714              	.set CYDEV_PHUB_TDMEM45_SIZE, 0x00000008
 2715              	.set CYREG_PHUB_TDMEM45_ORIG_TD0, 0x40007968
 2716              	.set CYREG_PHUB_TDMEM45_ORIG_TD1, 0x4000796c
 2717              	.set CYDEV_PHUB_TDMEM46_BASE, 0x40007970
 2718              	.set CYDEV_PHUB_TDMEM46_SIZE, 0x00000008
 2719              	.set CYREG_PHUB_TDMEM46_ORIG_TD0, 0x40007970
 2720              	.set CYREG_PHUB_TDMEM46_ORIG_TD1, 0x40007974
 2721              	.set CYDEV_PHUB_TDMEM47_BASE, 0x40007978
 2722              	.set CYDEV_PHUB_TDMEM47_SIZE, 0x00000008
 2723              	.set CYREG_PHUB_TDMEM47_ORIG_TD0, 0x40007978
 2724              	.set CYREG_PHUB_TDMEM47_ORIG_TD1, 0x4000797c
 2725              	.set CYDEV_PHUB_TDMEM48_BASE, 0x40007980
 2726              	.set CYDEV_PHUB_TDMEM48_SIZE, 0x00000008
 2727              	.set CYREG_PHUB_TDMEM48_ORIG_TD0, 0x40007980
 2728              	.set CYREG_PHUB_TDMEM48_ORIG_TD1, 0x40007984
 2729              	.set CYDEV_PHUB_TDMEM49_BASE, 0x40007988
 2730              	.set CYDEV_PHUB_TDMEM49_SIZE, 0x00000008
 2731              	.set CYREG_PHUB_TDMEM49_ORIG_TD0, 0x40007988
 2732              	.set CYREG_PHUB_TDMEM49_ORIG_TD1, 0x4000798c
 2733              	.set CYDEV_PHUB_TDMEM50_BASE, 0x40007990
 2734              	.set CYDEV_PHUB_TDMEM50_SIZE, 0x00000008
 2735              	.set CYREG_PHUB_TDMEM50_ORIG_TD0, 0x40007990
 2736              	.set CYREG_PHUB_TDMEM50_ORIG_TD1, 0x40007994
 2737              	.set CYDEV_PHUB_TDMEM51_BASE, 0x40007998
 2738              	.set CYDEV_PHUB_TDMEM51_SIZE, 0x00000008
 2739              	.set CYREG_PHUB_TDMEM51_ORIG_TD0, 0x40007998
 2740              	.set CYREG_PHUB_TDMEM51_ORIG_TD1, 0x4000799c
 2741              	.set CYDEV_PHUB_TDMEM52_BASE, 0x400079a0
 2742              	.set CYDEV_PHUB_TDMEM52_SIZE, 0x00000008
 2743              	.set CYREG_PHUB_TDMEM52_ORIG_TD0, 0x400079a0
 2744              	.set CYREG_PHUB_TDMEM52_ORIG_TD1, 0x400079a4
 2745              	.set CYDEV_PHUB_TDMEM53_BASE, 0x400079a8
 2746              	.set CYDEV_PHUB_TDMEM53_SIZE, 0x00000008
 2747              	.set CYREG_PHUB_TDMEM53_ORIG_TD0, 0x400079a8
 2748              	.set CYREG_PHUB_TDMEM53_ORIG_TD1, 0x400079ac
 2749              	.set CYDEV_PHUB_TDMEM54_BASE, 0x400079b0
 2750              	.set CYDEV_PHUB_TDMEM54_SIZE, 0x00000008
 2751              	.set CYREG_PHUB_TDMEM54_ORIG_TD0, 0x400079b0
 2752              	.set CYREG_PHUB_TDMEM54_ORIG_TD1, 0x400079b4
 2753              	.set CYDEV_PHUB_TDMEM55_BASE, 0x400079b8
 2754              	.set CYDEV_PHUB_TDMEM55_SIZE, 0x00000008
 2755              	.set CYREG_PHUB_TDMEM55_ORIG_TD0, 0x400079b8
 2756              	.set CYREG_PHUB_TDMEM55_ORIG_TD1, 0x400079bc
 2757              	.set CYDEV_PHUB_TDMEM56_BASE, 0x400079c0
 2758              	.set CYDEV_PHUB_TDMEM56_SIZE, 0x00000008
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 144


 2759              	.set CYREG_PHUB_TDMEM56_ORIG_TD0, 0x400079c0
 2760              	.set CYREG_PHUB_TDMEM56_ORIG_TD1, 0x400079c4
 2761              	.set CYDEV_PHUB_TDMEM57_BASE, 0x400079c8
 2762              	.set CYDEV_PHUB_TDMEM57_SIZE, 0x00000008
 2763              	.set CYREG_PHUB_TDMEM57_ORIG_TD0, 0x400079c8
 2764              	.set CYREG_PHUB_TDMEM57_ORIG_TD1, 0x400079cc
 2765              	.set CYDEV_PHUB_TDMEM58_BASE, 0x400079d0
 2766              	.set CYDEV_PHUB_TDMEM58_SIZE, 0x00000008
 2767              	.set CYREG_PHUB_TDMEM58_ORIG_TD0, 0x400079d0
 2768              	.set CYREG_PHUB_TDMEM58_ORIG_TD1, 0x400079d4
 2769              	.set CYDEV_PHUB_TDMEM59_BASE, 0x400079d8
 2770              	.set CYDEV_PHUB_TDMEM59_SIZE, 0x00000008
 2771              	.set CYREG_PHUB_TDMEM59_ORIG_TD0, 0x400079d8
 2772              	.set CYREG_PHUB_TDMEM59_ORIG_TD1, 0x400079dc
 2773              	.set CYDEV_PHUB_TDMEM60_BASE, 0x400079e0
 2774              	.set CYDEV_PHUB_TDMEM60_SIZE, 0x00000008
 2775              	.set CYREG_PHUB_TDMEM60_ORIG_TD0, 0x400079e0
 2776              	.set CYREG_PHUB_TDMEM60_ORIG_TD1, 0x400079e4
 2777              	.set CYDEV_PHUB_TDMEM61_BASE, 0x400079e8
 2778              	.set CYDEV_PHUB_TDMEM61_SIZE, 0x00000008
 2779              	.set CYREG_PHUB_TDMEM61_ORIG_TD0, 0x400079e8
 2780              	.set CYREG_PHUB_TDMEM61_ORIG_TD1, 0x400079ec
 2781              	.set CYDEV_PHUB_TDMEM62_BASE, 0x400079f0
 2782              	.set CYDEV_PHUB_TDMEM62_SIZE, 0x00000008
 2783              	.set CYREG_PHUB_TDMEM62_ORIG_TD0, 0x400079f0
 2784              	.set CYREG_PHUB_TDMEM62_ORIG_TD1, 0x400079f4
 2785              	.set CYDEV_PHUB_TDMEM63_BASE, 0x400079f8
 2786              	.set CYDEV_PHUB_TDMEM63_SIZE, 0x00000008
 2787              	.set CYREG_PHUB_TDMEM63_ORIG_TD0, 0x400079f8
 2788              	.set CYREG_PHUB_TDMEM63_ORIG_TD1, 0x400079fc
 2789              	.set CYDEV_PHUB_TDMEM64_BASE, 0x40007a00
 2790              	.set CYDEV_PHUB_TDMEM64_SIZE, 0x00000008
 2791              	.set CYREG_PHUB_TDMEM64_ORIG_TD0, 0x40007a00
 2792              	.set CYREG_PHUB_TDMEM64_ORIG_TD1, 0x40007a04
 2793              	.set CYDEV_PHUB_TDMEM65_BASE, 0x40007a08
 2794              	.set CYDEV_PHUB_TDMEM65_SIZE, 0x00000008
 2795              	.set CYREG_PHUB_TDMEM65_ORIG_TD0, 0x40007a08
 2796              	.set CYREG_PHUB_TDMEM65_ORIG_TD1, 0x40007a0c
 2797              	.set CYDEV_PHUB_TDMEM66_BASE, 0x40007a10
 2798              	.set CYDEV_PHUB_TDMEM66_SIZE, 0x00000008
 2799              	.set CYREG_PHUB_TDMEM66_ORIG_TD0, 0x40007a10
 2800              	.set CYREG_PHUB_TDMEM66_ORIG_TD1, 0x40007a14
 2801              	.set CYDEV_PHUB_TDMEM67_BASE, 0x40007a18
 2802              	.set CYDEV_PHUB_TDMEM67_SIZE, 0x00000008
 2803              	.set CYREG_PHUB_TDMEM67_ORIG_TD0, 0x40007a18
 2804              	.set CYREG_PHUB_TDMEM67_ORIG_TD1, 0x40007a1c
 2805              	.set CYDEV_PHUB_TDMEM68_BASE, 0x40007a20
 2806              	.set CYDEV_PHUB_TDMEM68_SIZE, 0x00000008
 2807              	.set CYREG_PHUB_TDMEM68_ORIG_TD0, 0x40007a20
 2808              	.set CYREG_PHUB_TDMEM68_ORIG_TD1, 0x40007a24
 2809              	.set CYDEV_PHUB_TDMEM69_BASE, 0x40007a28
 2810              	.set CYDEV_PHUB_TDMEM69_SIZE, 0x00000008
 2811              	.set CYREG_PHUB_TDMEM69_ORIG_TD0, 0x40007a28
 2812              	.set CYREG_PHUB_TDMEM69_ORIG_TD1, 0x40007a2c
 2813              	.set CYDEV_PHUB_TDMEM70_BASE, 0x40007a30
 2814              	.set CYDEV_PHUB_TDMEM70_SIZE, 0x00000008
 2815              	.set CYREG_PHUB_TDMEM70_ORIG_TD0, 0x40007a30
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 145


 2816              	.set CYREG_PHUB_TDMEM70_ORIG_TD1, 0x40007a34
 2817              	.set CYDEV_PHUB_TDMEM71_BASE, 0x40007a38
 2818              	.set CYDEV_PHUB_TDMEM71_SIZE, 0x00000008
 2819              	.set CYREG_PHUB_TDMEM71_ORIG_TD0, 0x40007a38
 2820              	.set CYREG_PHUB_TDMEM71_ORIG_TD1, 0x40007a3c
 2821              	.set CYDEV_PHUB_TDMEM72_BASE, 0x40007a40
 2822              	.set CYDEV_PHUB_TDMEM72_SIZE, 0x00000008
 2823              	.set CYREG_PHUB_TDMEM72_ORIG_TD0, 0x40007a40
 2824              	.set CYREG_PHUB_TDMEM72_ORIG_TD1, 0x40007a44
 2825              	.set CYDEV_PHUB_TDMEM73_BASE, 0x40007a48
 2826              	.set CYDEV_PHUB_TDMEM73_SIZE, 0x00000008
 2827              	.set CYREG_PHUB_TDMEM73_ORIG_TD0, 0x40007a48
 2828              	.set CYREG_PHUB_TDMEM73_ORIG_TD1, 0x40007a4c
 2829              	.set CYDEV_PHUB_TDMEM74_BASE, 0x40007a50
 2830              	.set CYDEV_PHUB_TDMEM74_SIZE, 0x00000008
 2831              	.set CYREG_PHUB_TDMEM74_ORIG_TD0, 0x40007a50
 2832              	.set CYREG_PHUB_TDMEM74_ORIG_TD1, 0x40007a54
 2833              	.set CYDEV_PHUB_TDMEM75_BASE, 0x40007a58
 2834              	.set CYDEV_PHUB_TDMEM75_SIZE, 0x00000008
 2835              	.set CYREG_PHUB_TDMEM75_ORIG_TD0, 0x40007a58
 2836              	.set CYREG_PHUB_TDMEM75_ORIG_TD1, 0x40007a5c
 2837              	.set CYDEV_PHUB_TDMEM76_BASE, 0x40007a60
 2838              	.set CYDEV_PHUB_TDMEM76_SIZE, 0x00000008
 2839              	.set CYREG_PHUB_TDMEM76_ORIG_TD0, 0x40007a60
 2840              	.set CYREG_PHUB_TDMEM76_ORIG_TD1, 0x40007a64
 2841              	.set CYDEV_PHUB_TDMEM77_BASE, 0x40007a68
 2842              	.set CYDEV_PHUB_TDMEM77_SIZE, 0x00000008
 2843              	.set CYREG_PHUB_TDMEM77_ORIG_TD0, 0x40007a68
 2844              	.set CYREG_PHUB_TDMEM77_ORIG_TD1, 0x40007a6c
 2845              	.set CYDEV_PHUB_TDMEM78_BASE, 0x40007a70
 2846              	.set CYDEV_PHUB_TDMEM78_SIZE, 0x00000008
 2847              	.set CYREG_PHUB_TDMEM78_ORIG_TD0, 0x40007a70
 2848              	.set CYREG_PHUB_TDMEM78_ORIG_TD1, 0x40007a74
 2849              	.set CYDEV_PHUB_TDMEM79_BASE, 0x40007a78
 2850              	.set CYDEV_PHUB_TDMEM79_SIZE, 0x00000008
 2851              	.set CYREG_PHUB_TDMEM79_ORIG_TD0, 0x40007a78
 2852              	.set CYREG_PHUB_TDMEM79_ORIG_TD1, 0x40007a7c
 2853              	.set CYDEV_PHUB_TDMEM80_BASE, 0x40007a80
 2854              	.set CYDEV_PHUB_TDMEM80_SIZE, 0x00000008
 2855              	.set CYREG_PHUB_TDMEM80_ORIG_TD0, 0x40007a80
 2856              	.set CYREG_PHUB_TDMEM80_ORIG_TD1, 0x40007a84
 2857              	.set CYDEV_PHUB_TDMEM81_BASE, 0x40007a88
 2858              	.set CYDEV_PHUB_TDMEM81_SIZE, 0x00000008
 2859              	.set CYREG_PHUB_TDMEM81_ORIG_TD0, 0x40007a88
 2860              	.set CYREG_PHUB_TDMEM81_ORIG_TD1, 0x40007a8c
 2861              	.set CYDEV_PHUB_TDMEM82_BASE, 0x40007a90
 2862              	.set CYDEV_PHUB_TDMEM82_SIZE, 0x00000008
 2863              	.set CYREG_PHUB_TDMEM82_ORIG_TD0, 0x40007a90
 2864              	.set CYREG_PHUB_TDMEM82_ORIG_TD1, 0x40007a94
 2865              	.set CYDEV_PHUB_TDMEM83_BASE, 0x40007a98
 2866              	.set CYDEV_PHUB_TDMEM83_SIZE, 0x00000008
 2867              	.set CYREG_PHUB_TDMEM83_ORIG_TD0, 0x40007a98
 2868              	.set CYREG_PHUB_TDMEM83_ORIG_TD1, 0x40007a9c
 2869              	.set CYDEV_PHUB_TDMEM84_BASE, 0x40007aa0
 2870              	.set CYDEV_PHUB_TDMEM84_SIZE, 0x00000008
 2871              	.set CYREG_PHUB_TDMEM84_ORIG_TD0, 0x40007aa0
 2872              	.set CYREG_PHUB_TDMEM84_ORIG_TD1, 0x40007aa4
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 146


 2873              	.set CYDEV_PHUB_TDMEM85_BASE, 0x40007aa8
 2874              	.set CYDEV_PHUB_TDMEM85_SIZE, 0x00000008
 2875              	.set CYREG_PHUB_TDMEM85_ORIG_TD0, 0x40007aa8
 2876              	.set CYREG_PHUB_TDMEM85_ORIG_TD1, 0x40007aac
 2877              	.set CYDEV_PHUB_TDMEM86_BASE, 0x40007ab0
 2878              	.set CYDEV_PHUB_TDMEM86_SIZE, 0x00000008
 2879              	.set CYREG_PHUB_TDMEM86_ORIG_TD0, 0x40007ab0
 2880              	.set CYREG_PHUB_TDMEM86_ORIG_TD1, 0x40007ab4
 2881              	.set CYDEV_PHUB_TDMEM87_BASE, 0x40007ab8
 2882              	.set CYDEV_PHUB_TDMEM87_SIZE, 0x00000008
 2883              	.set CYREG_PHUB_TDMEM87_ORIG_TD0, 0x40007ab8
 2884              	.set CYREG_PHUB_TDMEM87_ORIG_TD1, 0x40007abc
 2885              	.set CYDEV_PHUB_TDMEM88_BASE, 0x40007ac0
 2886              	.set CYDEV_PHUB_TDMEM88_SIZE, 0x00000008
 2887              	.set CYREG_PHUB_TDMEM88_ORIG_TD0, 0x40007ac0
 2888              	.set CYREG_PHUB_TDMEM88_ORIG_TD1, 0x40007ac4
 2889              	.set CYDEV_PHUB_TDMEM89_BASE, 0x40007ac8
 2890              	.set CYDEV_PHUB_TDMEM89_SIZE, 0x00000008
 2891              	.set CYREG_PHUB_TDMEM89_ORIG_TD0, 0x40007ac8
 2892              	.set CYREG_PHUB_TDMEM89_ORIG_TD1, 0x40007acc
 2893              	.set CYDEV_PHUB_TDMEM90_BASE, 0x40007ad0
 2894              	.set CYDEV_PHUB_TDMEM90_SIZE, 0x00000008
 2895              	.set CYREG_PHUB_TDMEM90_ORIG_TD0, 0x40007ad0
 2896              	.set CYREG_PHUB_TDMEM90_ORIG_TD1, 0x40007ad4
 2897              	.set CYDEV_PHUB_TDMEM91_BASE, 0x40007ad8
 2898              	.set CYDEV_PHUB_TDMEM91_SIZE, 0x00000008
 2899              	.set CYREG_PHUB_TDMEM91_ORIG_TD0, 0x40007ad8
 2900              	.set CYREG_PHUB_TDMEM91_ORIG_TD1, 0x40007adc
 2901              	.set CYDEV_PHUB_TDMEM92_BASE, 0x40007ae0
 2902              	.set CYDEV_PHUB_TDMEM92_SIZE, 0x00000008
 2903              	.set CYREG_PHUB_TDMEM92_ORIG_TD0, 0x40007ae0
 2904              	.set CYREG_PHUB_TDMEM92_ORIG_TD1, 0x40007ae4
 2905              	.set CYDEV_PHUB_TDMEM93_BASE, 0x40007ae8
 2906              	.set CYDEV_PHUB_TDMEM93_SIZE, 0x00000008
 2907              	.set CYREG_PHUB_TDMEM93_ORIG_TD0, 0x40007ae8
 2908              	.set CYREG_PHUB_TDMEM93_ORIG_TD1, 0x40007aec
 2909              	.set CYDEV_PHUB_TDMEM94_BASE, 0x40007af0
 2910              	.set CYDEV_PHUB_TDMEM94_SIZE, 0x00000008
 2911              	.set CYREG_PHUB_TDMEM94_ORIG_TD0, 0x40007af0
 2912              	.set CYREG_PHUB_TDMEM94_ORIG_TD1, 0x40007af4
 2913              	.set CYDEV_PHUB_TDMEM95_BASE, 0x40007af8
 2914              	.set CYDEV_PHUB_TDMEM95_SIZE, 0x00000008
 2915              	.set CYREG_PHUB_TDMEM95_ORIG_TD0, 0x40007af8
 2916              	.set CYREG_PHUB_TDMEM95_ORIG_TD1, 0x40007afc
 2917              	.set CYDEV_PHUB_TDMEM96_BASE, 0x40007b00
 2918              	.set CYDEV_PHUB_TDMEM96_SIZE, 0x00000008
 2919              	.set CYREG_PHUB_TDMEM96_ORIG_TD0, 0x40007b00
 2920              	.set CYREG_PHUB_TDMEM96_ORIG_TD1, 0x40007b04
 2921              	.set CYDEV_PHUB_TDMEM97_BASE, 0x40007b08
 2922              	.set CYDEV_PHUB_TDMEM97_SIZE, 0x00000008
 2923              	.set CYREG_PHUB_TDMEM97_ORIG_TD0, 0x40007b08
 2924              	.set CYREG_PHUB_TDMEM97_ORIG_TD1, 0x40007b0c
 2925              	.set CYDEV_PHUB_TDMEM98_BASE, 0x40007b10
 2926              	.set CYDEV_PHUB_TDMEM98_SIZE, 0x00000008
 2927              	.set CYREG_PHUB_TDMEM98_ORIG_TD0, 0x40007b10
 2928              	.set CYREG_PHUB_TDMEM98_ORIG_TD1, 0x40007b14
 2929              	.set CYDEV_PHUB_TDMEM99_BASE, 0x40007b18
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 147


 2930              	.set CYDEV_PHUB_TDMEM99_SIZE, 0x00000008
 2931              	.set CYREG_PHUB_TDMEM99_ORIG_TD0, 0x40007b18
 2932              	.set CYREG_PHUB_TDMEM99_ORIG_TD1, 0x40007b1c
 2933              	.set CYDEV_PHUB_TDMEM100_BASE, 0x40007b20
 2934              	.set CYDEV_PHUB_TDMEM100_SIZE, 0x00000008
 2935              	.set CYREG_PHUB_TDMEM100_ORIG_TD0, 0x40007b20
 2936              	.set CYREG_PHUB_TDMEM100_ORIG_TD1, 0x40007b24
 2937              	.set CYDEV_PHUB_TDMEM101_BASE, 0x40007b28
 2938              	.set CYDEV_PHUB_TDMEM101_SIZE, 0x00000008
 2939              	.set CYREG_PHUB_TDMEM101_ORIG_TD0, 0x40007b28
 2940              	.set CYREG_PHUB_TDMEM101_ORIG_TD1, 0x40007b2c
 2941              	.set CYDEV_PHUB_TDMEM102_BASE, 0x40007b30
 2942              	.set CYDEV_PHUB_TDMEM102_SIZE, 0x00000008
 2943              	.set CYREG_PHUB_TDMEM102_ORIG_TD0, 0x40007b30
 2944              	.set CYREG_PHUB_TDMEM102_ORIG_TD1, 0x40007b34
 2945              	.set CYDEV_PHUB_TDMEM103_BASE, 0x40007b38
 2946              	.set CYDEV_PHUB_TDMEM103_SIZE, 0x00000008
 2947              	.set CYREG_PHUB_TDMEM103_ORIG_TD0, 0x40007b38
 2948              	.set CYREG_PHUB_TDMEM103_ORIG_TD1, 0x40007b3c
 2949              	.set CYDEV_PHUB_TDMEM104_BASE, 0x40007b40
 2950              	.set CYDEV_PHUB_TDMEM104_SIZE, 0x00000008
 2951              	.set CYREG_PHUB_TDMEM104_ORIG_TD0, 0x40007b40
 2952              	.set CYREG_PHUB_TDMEM104_ORIG_TD1, 0x40007b44
 2953              	.set CYDEV_PHUB_TDMEM105_BASE, 0x40007b48
 2954              	.set CYDEV_PHUB_TDMEM105_SIZE, 0x00000008
 2955              	.set CYREG_PHUB_TDMEM105_ORIG_TD0, 0x40007b48
 2956              	.set CYREG_PHUB_TDMEM105_ORIG_TD1, 0x40007b4c
 2957              	.set CYDEV_PHUB_TDMEM106_BASE, 0x40007b50
 2958              	.set CYDEV_PHUB_TDMEM106_SIZE, 0x00000008
 2959              	.set CYREG_PHUB_TDMEM106_ORIG_TD0, 0x40007b50
 2960              	.set CYREG_PHUB_TDMEM106_ORIG_TD1, 0x40007b54
 2961              	.set CYDEV_PHUB_TDMEM107_BASE, 0x40007b58
 2962              	.set CYDEV_PHUB_TDMEM107_SIZE, 0x00000008
 2963              	.set CYREG_PHUB_TDMEM107_ORIG_TD0, 0x40007b58
 2964              	.set CYREG_PHUB_TDMEM107_ORIG_TD1, 0x40007b5c
 2965              	.set CYDEV_PHUB_TDMEM108_BASE, 0x40007b60
 2966              	.set CYDEV_PHUB_TDMEM108_SIZE, 0x00000008
 2967              	.set CYREG_PHUB_TDMEM108_ORIG_TD0, 0x40007b60
 2968              	.set CYREG_PHUB_TDMEM108_ORIG_TD1, 0x40007b64
 2969              	.set CYDEV_PHUB_TDMEM109_BASE, 0x40007b68
 2970              	.set CYDEV_PHUB_TDMEM109_SIZE, 0x00000008
 2971              	.set CYREG_PHUB_TDMEM109_ORIG_TD0, 0x40007b68
 2972              	.set CYREG_PHUB_TDMEM109_ORIG_TD1, 0x40007b6c
 2973              	.set CYDEV_PHUB_TDMEM110_BASE, 0x40007b70
 2974              	.set CYDEV_PHUB_TDMEM110_SIZE, 0x00000008
 2975              	.set CYREG_PHUB_TDMEM110_ORIG_TD0, 0x40007b70
 2976              	.set CYREG_PHUB_TDMEM110_ORIG_TD1, 0x40007b74
 2977              	.set CYDEV_PHUB_TDMEM111_BASE, 0x40007b78
 2978              	.set CYDEV_PHUB_TDMEM111_SIZE, 0x00000008
 2979              	.set CYREG_PHUB_TDMEM111_ORIG_TD0, 0x40007b78
 2980              	.set CYREG_PHUB_TDMEM111_ORIG_TD1, 0x40007b7c
 2981              	.set CYDEV_PHUB_TDMEM112_BASE, 0x40007b80
 2982              	.set CYDEV_PHUB_TDMEM112_SIZE, 0x00000008
 2983              	.set CYREG_PHUB_TDMEM112_ORIG_TD0, 0x40007b80
 2984              	.set CYREG_PHUB_TDMEM112_ORIG_TD1, 0x40007b84
 2985              	.set CYDEV_PHUB_TDMEM113_BASE, 0x40007b88
 2986              	.set CYDEV_PHUB_TDMEM113_SIZE, 0x00000008
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 148


 2987              	.set CYREG_PHUB_TDMEM113_ORIG_TD0, 0x40007b88
 2988              	.set CYREG_PHUB_TDMEM113_ORIG_TD1, 0x40007b8c
 2989              	.set CYDEV_PHUB_TDMEM114_BASE, 0x40007b90
 2990              	.set CYDEV_PHUB_TDMEM114_SIZE, 0x00000008
 2991              	.set CYREG_PHUB_TDMEM114_ORIG_TD0, 0x40007b90
 2992              	.set CYREG_PHUB_TDMEM114_ORIG_TD1, 0x40007b94
 2993              	.set CYDEV_PHUB_TDMEM115_BASE, 0x40007b98
 2994              	.set CYDEV_PHUB_TDMEM115_SIZE, 0x00000008
 2995              	.set CYREG_PHUB_TDMEM115_ORIG_TD0, 0x40007b98
 2996              	.set CYREG_PHUB_TDMEM115_ORIG_TD1, 0x40007b9c
 2997              	.set CYDEV_PHUB_TDMEM116_BASE, 0x40007ba0
 2998              	.set CYDEV_PHUB_TDMEM116_SIZE, 0x00000008
 2999              	.set CYREG_PHUB_TDMEM116_ORIG_TD0, 0x40007ba0
 3000              	.set CYREG_PHUB_TDMEM116_ORIG_TD1, 0x40007ba4
 3001              	.set CYDEV_PHUB_TDMEM117_BASE, 0x40007ba8
 3002              	.set CYDEV_PHUB_TDMEM117_SIZE, 0x00000008
 3003              	.set CYREG_PHUB_TDMEM117_ORIG_TD0, 0x40007ba8
 3004              	.set CYREG_PHUB_TDMEM117_ORIG_TD1, 0x40007bac
 3005              	.set CYDEV_PHUB_TDMEM118_BASE, 0x40007bb0
 3006              	.set CYDEV_PHUB_TDMEM118_SIZE, 0x00000008
 3007              	.set CYREG_PHUB_TDMEM118_ORIG_TD0, 0x40007bb0
 3008              	.set CYREG_PHUB_TDMEM118_ORIG_TD1, 0x40007bb4
 3009              	.set CYDEV_PHUB_TDMEM119_BASE, 0x40007bb8
 3010              	.set CYDEV_PHUB_TDMEM119_SIZE, 0x00000008
 3011              	.set CYREG_PHUB_TDMEM119_ORIG_TD0, 0x40007bb8
 3012              	.set CYREG_PHUB_TDMEM119_ORIG_TD1, 0x40007bbc
 3013              	.set CYDEV_PHUB_TDMEM120_BASE, 0x40007bc0
 3014              	.set CYDEV_PHUB_TDMEM120_SIZE, 0x00000008
 3015              	.set CYREG_PHUB_TDMEM120_ORIG_TD0, 0x40007bc0
 3016              	.set CYREG_PHUB_TDMEM120_ORIG_TD1, 0x40007bc4
 3017              	.set CYDEV_PHUB_TDMEM121_BASE, 0x40007bc8
 3018              	.set CYDEV_PHUB_TDMEM121_SIZE, 0x00000008
 3019              	.set CYREG_PHUB_TDMEM121_ORIG_TD0, 0x40007bc8
 3020              	.set CYREG_PHUB_TDMEM121_ORIG_TD1, 0x40007bcc
 3021              	.set CYDEV_PHUB_TDMEM122_BASE, 0x40007bd0
 3022              	.set CYDEV_PHUB_TDMEM122_SIZE, 0x00000008
 3023              	.set CYREG_PHUB_TDMEM122_ORIG_TD0, 0x40007bd0
 3024              	.set CYREG_PHUB_TDMEM122_ORIG_TD1, 0x40007bd4
 3025              	.set CYDEV_PHUB_TDMEM123_BASE, 0x40007bd8
 3026              	.set CYDEV_PHUB_TDMEM123_SIZE, 0x00000008
 3027              	.set CYREG_PHUB_TDMEM123_ORIG_TD0, 0x40007bd8
 3028              	.set CYREG_PHUB_TDMEM123_ORIG_TD1, 0x40007bdc
 3029              	.set CYDEV_PHUB_TDMEM124_BASE, 0x40007be0
 3030              	.set CYDEV_PHUB_TDMEM124_SIZE, 0x00000008
 3031              	.set CYREG_PHUB_TDMEM124_ORIG_TD0, 0x40007be0
 3032              	.set CYREG_PHUB_TDMEM124_ORIG_TD1, 0x40007be4
 3033              	.set CYDEV_PHUB_TDMEM125_BASE, 0x40007be8
 3034              	.set CYDEV_PHUB_TDMEM125_SIZE, 0x00000008
 3035              	.set CYREG_PHUB_TDMEM125_ORIG_TD0, 0x40007be8
 3036              	.set CYREG_PHUB_TDMEM125_ORIG_TD1, 0x40007bec
 3037              	.set CYDEV_PHUB_TDMEM126_BASE, 0x40007bf0
 3038              	.set CYDEV_PHUB_TDMEM126_SIZE, 0x00000008
 3039              	.set CYREG_PHUB_TDMEM126_ORIG_TD0, 0x40007bf0
 3040              	.set CYREG_PHUB_TDMEM126_ORIG_TD1, 0x40007bf4
 3041              	.set CYDEV_PHUB_TDMEM127_BASE, 0x40007bf8
 3042              	.set CYDEV_PHUB_TDMEM127_SIZE, 0x00000008
 3043              	.set CYREG_PHUB_TDMEM127_ORIG_TD0, 0x40007bf8
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 149


 3044              	.set CYREG_PHUB_TDMEM127_ORIG_TD1, 0x40007bfc
 3045              	.set CYDEV_EE_BASE, 0x40008000
 3046              	.set CYDEV_EE_SIZE, 0x00000800
 3047              	.set CYREG_EE_DATA_MBASE, 0x40008000
 3048              	.set CYREG_EE_DATA_MSIZE, 0x00000800
 3049              	.set CYDEV_CAN0_BASE, 0x4000a000
 3050              	.set CYDEV_CAN0_SIZE, 0x000002a0
 3051              	.set CYDEV_CAN0_CSR_BASE, 0x4000a000
 3052              	.set CYDEV_CAN0_CSR_SIZE, 0x00000018
 3053              	.set CYREG_CAN0_CSR_INT_SR, 0x4000a000
 3054              	.set CYREG_CAN0_CSR_INT_EN, 0x4000a004
 3055              	.set CYREG_CAN0_CSR_BUF_SR, 0x4000a008
 3056              	.set CYREG_CAN0_CSR_ERR_SR, 0x4000a00c
 3057              	.set CYREG_CAN0_CSR_CMD, 0x4000a010
 3058              	.set CYREG_CAN0_CSR_CFG, 0x4000a014
 3059              	.set CYDEV_CAN0_TX0_BASE, 0x4000a020
 3060              	.set CYDEV_CAN0_TX0_SIZE, 0x00000010
 3061              	.set CYREG_CAN0_TX0_CMD, 0x4000a020
 3062              	.set CYREG_CAN0_TX0_ID, 0x4000a024
 3063              	.set CYREG_CAN0_TX0_DH, 0x4000a028
 3064              	.set CYREG_CAN0_TX0_DL, 0x4000a02c
 3065              	.set CYDEV_CAN0_TX1_BASE, 0x4000a030
 3066              	.set CYDEV_CAN0_TX1_SIZE, 0x00000010
 3067              	.set CYREG_CAN0_TX1_CMD, 0x4000a030
 3068              	.set CYREG_CAN0_TX1_ID, 0x4000a034
 3069              	.set CYREG_CAN0_TX1_DH, 0x4000a038
 3070              	.set CYREG_CAN0_TX1_DL, 0x4000a03c
 3071              	.set CYDEV_CAN0_TX2_BASE, 0x4000a040
 3072              	.set CYDEV_CAN0_TX2_SIZE, 0x00000010
 3073              	.set CYREG_CAN0_TX2_CMD, 0x4000a040
 3074              	.set CYREG_CAN0_TX2_ID, 0x4000a044
 3075              	.set CYREG_CAN0_TX2_DH, 0x4000a048
 3076              	.set CYREG_CAN0_TX2_DL, 0x4000a04c
 3077              	.set CYDEV_CAN0_TX3_BASE, 0x4000a050
 3078              	.set CYDEV_CAN0_TX3_SIZE, 0x00000010
 3079              	.set CYREG_CAN0_TX3_CMD, 0x4000a050
 3080              	.set CYREG_CAN0_TX3_ID, 0x4000a054
 3081              	.set CYREG_CAN0_TX3_DH, 0x4000a058
 3082              	.set CYREG_CAN0_TX3_DL, 0x4000a05c
 3083              	.set CYDEV_CAN0_TX4_BASE, 0x4000a060
 3084              	.set CYDEV_CAN0_TX4_SIZE, 0x00000010
 3085              	.set CYREG_CAN0_TX4_CMD, 0x4000a060
 3086              	.set CYREG_CAN0_TX4_ID, 0x4000a064
 3087              	.set CYREG_CAN0_TX4_DH, 0x4000a068
 3088              	.set CYREG_CAN0_TX4_DL, 0x4000a06c
 3089              	.set CYDEV_CAN0_TX5_BASE, 0x4000a070
 3090              	.set CYDEV_CAN0_TX5_SIZE, 0x00000010
 3091              	.set CYREG_CAN0_TX5_CMD, 0x4000a070
 3092              	.set CYREG_CAN0_TX5_ID, 0x4000a074
 3093              	.set CYREG_CAN0_TX5_DH, 0x4000a078
 3094              	.set CYREG_CAN0_TX5_DL, 0x4000a07c
 3095              	.set CYDEV_CAN0_TX6_BASE, 0x4000a080
 3096              	.set CYDEV_CAN0_TX6_SIZE, 0x00000010
 3097              	.set CYREG_CAN0_TX6_CMD, 0x4000a080
 3098              	.set CYREG_CAN0_TX6_ID, 0x4000a084
 3099              	.set CYREG_CAN0_TX6_DH, 0x4000a088
 3100              	.set CYREG_CAN0_TX6_DL, 0x4000a08c
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 150


 3101              	.set CYDEV_CAN0_TX7_BASE, 0x4000a090
 3102              	.set CYDEV_CAN0_TX7_SIZE, 0x00000010
 3103              	.set CYREG_CAN0_TX7_CMD, 0x4000a090
 3104              	.set CYREG_CAN0_TX7_ID, 0x4000a094
 3105              	.set CYREG_CAN0_TX7_DH, 0x4000a098
 3106              	.set CYREG_CAN0_TX7_DL, 0x4000a09c
 3107              	.set CYDEV_CAN0_RX0_BASE, 0x4000a0a0
 3108              	.set CYDEV_CAN0_RX0_SIZE, 0x00000020
 3109              	.set CYREG_CAN0_RX0_CMD, 0x4000a0a0
 3110              	.set CYREG_CAN0_RX0_ID, 0x4000a0a4
 3111              	.set CYREG_CAN0_RX0_DH, 0x4000a0a8
 3112              	.set CYREG_CAN0_RX0_DL, 0x4000a0ac
 3113              	.set CYREG_CAN0_RX0_AMR, 0x4000a0b0
 3114              	.set CYREG_CAN0_RX0_ACR, 0x4000a0b4
 3115              	.set CYREG_CAN0_RX0_AMRD, 0x4000a0b8
 3116              	.set CYREG_CAN0_RX0_ACRD, 0x4000a0bc
 3117              	.set CYDEV_CAN0_RX1_BASE, 0x4000a0c0
 3118              	.set CYDEV_CAN0_RX1_SIZE, 0x00000020
 3119              	.set CYREG_CAN0_RX1_CMD, 0x4000a0c0
 3120              	.set CYREG_CAN0_RX1_ID, 0x4000a0c4
 3121              	.set CYREG_CAN0_RX1_DH, 0x4000a0c8
 3122              	.set CYREG_CAN0_RX1_DL, 0x4000a0cc
 3123              	.set CYREG_CAN0_RX1_AMR, 0x4000a0d0
 3124              	.set CYREG_CAN0_RX1_ACR, 0x4000a0d4
 3125              	.set CYREG_CAN0_RX1_AMRD, 0x4000a0d8
 3126              	.set CYREG_CAN0_RX1_ACRD, 0x4000a0dc
 3127              	.set CYDEV_CAN0_RX2_BASE, 0x4000a0e0
 3128              	.set CYDEV_CAN0_RX2_SIZE, 0x00000020
 3129              	.set CYREG_CAN0_RX2_CMD, 0x4000a0e0
 3130              	.set CYREG_CAN0_RX2_ID, 0x4000a0e4
 3131              	.set CYREG_CAN0_RX2_DH, 0x4000a0e8
 3132              	.set CYREG_CAN0_RX2_DL, 0x4000a0ec
 3133              	.set CYREG_CAN0_RX2_AMR, 0x4000a0f0
 3134              	.set CYREG_CAN0_RX2_ACR, 0x4000a0f4
 3135              	.set CYREG_CAN0_RX2_AMRD, 0x4000a0f8
 3136              	.set CYREG_CAN0_RX2_ACRD, 0x4000a0fc
 3137              	.set CYDEV_CAN0_RX3_BASE, 0x4000a100
 3138              	.set CYDEV_CAN0_RX3_SIZE, 0x00000020
 3139              	.set CYREG_CAN0_RX3_CMD, 0x4000a100
 3140              	.set CYREG_CAN0_RX3_ID, 0x4000a104
 3141              	.set CYREG_CAN0_RX3_DH, 0x4000a108
 3142              	.set CYREG_CAN0_RX3_DL, 0x4000a10c
 3143              	.set CYREG_CAN0_RX3_AMR, 0x4000a110
 3144              	.set CYREG_CAN0_RX3_ACR, 0x4000a114
 3145              	.set CYREG_CAN0_RX3_AMRD, 0x4000a118
 3146              	.set CYREG_CAN0_RX3_ACRD, 0x4000a11c
 3147              	.set CYDEV_CAN0_RX4_BASE, 0x4000a120
 3148              	.set CYDEV_CAN0_RX4_SIZE, 0x00000020
 3149              	.set CYREG_CAN0_RX4_CMD, 0x4000a120
 3150              	.set CYREG_CAN0_RX4_ID, 0x4000a124
 3151              	.set CYREG_CAN0_RX4_DH, 0x4000a128
 3152              	.set CYREG_CAN0_RX4_DL, 0x4000a12c
 3153              	.set CYREG_CAN0_RX4_AMR, 0x4000a130
 3154              	.set CYREG_CAN0_RX4_ACR, 0x4000a134
 3155              	.set CYREG_CAN0_RX4_AMRD, 0x4000a138
 3156              	.set CYREG_CAN0_RX4_ACRD, 0x4000a13c
 3157              	.set CYDEV_CAN0_RX5_BASE, 0x4000a140
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 151


 3158              	.set CYDEV_CAN0_RX5_SIZE, 0x00000020
 3159              	.set CYREG_CAN0_RX5_CMD, 0x4000a140
 3160              	.set CYREG_CAN0_RX5_ID, 0x4000a144
 3161              	.set CYREG_CAN0_RX5_DH, 0x4000a148
 3162              	.set CYREG_CAN0_RX5_DL, 0x4000a14c
 3163              	.set CYREG_CAN0_RX5_AMR, 0x4000a150
 3164              	.set CYREG_CAN0_RX5_ACR, 0x4000a154
 3165              	.set CYREG_CAN0_RX5_AMRD, 0x4000a158
 3166              	.set CYREG_CAN0_RX5_ACRD, 0x4000a15c
 3167              	.set CYDEV_CAN0_RX6_BASE, 0x4000a160
 3168              	.set CYDEV_CAN0_RX6_SIZE, 0x00000020
 3169              	.set CYREG_CAN0_RX6_CMD, 0x4000a160
 3170              	.set CYREG_CAN0_RX6_ID, 0x4000a164
 3171              	.set CYREG_CAN0_RX6_DH, 0x4000a168
 3172              	.set CYREG_CAN0_RX6_DL, 0x4000a16c
 3173              	.set CYREG_CAN0_RX6_AMR, 0x4000a170
 3174              	.set CYREG_CAN0_RX6_ACR, 0x4000a174
 3175              	.set CYREG_CAN0_RX6_AMRD, 0x4000a178
 3176              	.set CYREG_CAN0_RX6_ACRD, 0x4000a17c
 3177              	.set CYDEV_CAN0_RX7_BASE, 0x4000a180
 3178              	.set CYDEV_CAN0_RX7_SIZE, 0x00000020
 3179              	.set CYREG_CAN0_RX7_CMD, 0x4000a180
 3180              	.set CYREG_CAN0_RX7_ID, 0x4000a184
 3181              	.set CYREG_CAN0_RX7_DH, 0x4000a188
 3182              	.set CYREG_CAN0_RX7_DL, 0x4000a18c
 3183              	.set CYREG_CAN0_RX7_AMR, 0x4000a190
 3184              	.set CYREG_CAN0_RX7_ACR, 0x4000a194
 3185              	.set CYREG_CAN0_RX7_AMRD, 0x4000a198
 3186              	.set CYREG_CAN0_RX7_ACRD, 0x4000a19c
 3187              	.set CYDEV_CAN0_RX8_BASE, 0x4000a1a0
 3188              	.set CYDEV_CAN0_RX8_SIZE, 0x00000020
 3189              	.set CYREG_CAN0_RX8_CMD, 0x4000a1a0
 3190              	.set CYREG_CAN0_RX8_ID, 0x4000a1a4
 3191              	.set CYREG_CAN0_RX8_DH, 0x4000a1a8
 3192              	.set CYREG_CAN0_RX8_DL, 0x4000a1ac
 3193              	.set CYREG_CAN0_RX8_AMR, 0x4000a1b0
 3194              	.set CYREG_CAN0_RX8_ACR, 0x4000a1b4
 3195              	.set CYREG_CAN0_RX8_AMRD, 0x4000a1b8
 3196              	.set CYREG_CAN0_RX8_ACRD, 0x4000a1bc
 3197              	.set CYDEV_CAN0_RX9_BASE, 0x4000a1c0
 3198              	.set CYDEV_CAN0_RX9_SIZE, 0x00000020
 3199              	.set CYREG_CAN0_RX9_CMD, 0x4000a1c0
 3200              	.set CYREG_CAN0_RX9_ID, 0x4000a1c4
 3201              	.set CYREG_CAN0_RX9_DH, 0x4000a1c8
 3202              	.set CYREG_CAN0_RX9_DL, 0x4000a1cc
 3203              	.set CYREG_CAN0_RX9_AMR, 0x4000a1d0
 3204              	.set CYREG_CAN0_RX9_ACR, 0x4000a1d4
 3205              	.set CYREG_CAN0_RX9_AMRD, 0x4000a1d8
 3206              	.set CYREG_CAN0_RX9_ACRD, 0x4000a1dc
 3207              	.set CYDEV_CAN0_RX10_BASE, 0x4000a1e0
 3208              	.set CYDEV_CAN0_RX10_SIZE, 0x00000020
 3209              	.set CYREG_CAN0_RX10_CMD, 0x4000a1e0
 3210              	.set CYREG_CAN0_RX10_ID, 0x4000a1e4
 3211              	.set CYREG_CAN0_RX10_DH, 0x4000a1e8
 3212              	.set CYREG_CAN0_RX10_DL, 0x4000a1ec
 3213              	.set CYREG_CAN0_RX10_AMR, 0x4000a1f0
 3214              	.set CYREG_CAN0_RX10_ACR, 0x4000a1f4
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 152


 3215              	.set CYREG_CAN0_RX10_AMRD, 0x4000a1f8
 3216              	.set CYREG_CAN0_RX10_ACRD, 0x4000a1fc
 3217              	.set CYDEV_CAN0_RX11_BASE, 0x4000a200
 3218              	.set CYDEV_CAN0_RX11_SIZE, 0x00000020
 3219              	.set CYREG_CAN0_RX11_CMD, 0x4000a200
 3220              	.set CYREG_CAN0_RX11_ID, 0x4000a204
 3221              	.set CYREG_CAN0_RX11_DH, 0x4000a208
 3222              	.set CYREG_CAN0_RX11_DL, 0x4000a20c
 3223              	.set CYREG_CAN0_RX11_AMR, 0x4000a210
 3224              	.set CYREG_CAN0_RX11_ACR, 0x4000a214
 3225              	.set CYREG_CAN0_RX11_AMRD, 0x4000a218
 3226              	.set CYREG_CAN0_RX11_ACRD, 0x4000a21c
 3227              	.set CYDEV_CAN0_RX12_BASE, 0x4000a220
 3228              	.set CYDEV_CAN0_RX12_SIZE, 0x00000020
 3229              	.set CYREG_CAN0_RX12_CMD, 0x4000a220
 3230              	.set CYREG_CAN0_RX12_ID, 0x4000a224
 3231              	.set CYREG_CAN0_RX12_DH, 0x4000a228
 3232              	.set CYREG_CAN0_RX12_DL, 0x4000a22c
 3233              	.set CYREG_CAN0_RX12_AMR, 0x4000a230
 3234              	.set CYREG_CAN0_RX12_ACR, 0x4000a234
 3235              	.set CYREG_CAN0_RX12_AMRD, 0x4000a238
 3236              	.set CYREG_CAN0_RX12_ACRD, 0x4000a23c
 3237              	.set CYDEV_CAN0_RX13_BASE, 0x4000a240
 3238              	.set CYDEV_CAN0_RX13_SIZE, 0x00000020
 3239              	.set CYREG_CAN0_RX13_CMD, 0x4000a240
 3240              	.set CYREG_CAN0_RX13_ID, 0x4000a244
 3241              	.set CYREG_CAN0_RX13_DH, 0x4000a248
 3242              	.set CYREG_CAN0_RX13_DL, 0x4000a24c
 3243              	.set CYREG_CAN0_RX13_AMR, 0x4000a250
 3244              	.set CYREG_CAN0_RX13_ACR, 0x4000a254
 3245              	.set CYREG_CAN0_RX13_AMRD, 0x4000a258
 3246              	.set CYREG_CAN0_RX13_ACRD, 0x4000a25c
 3247              	.set CYDEV_CAN0_RX14_BASE, 0x4000a260
 3248              	.set CYDEV_CAN0_RX14_SIZE, 0x00000020
 3249              	.set CYREG_CAN0_RX14_CMD, 0x4000a260
 3250              	.set CYREG_CAN0_RX14_ID, 0x4000a264
 3251              	.set CYREG_CAN0_RX14_DH, 0x4000a268
 3252              	.set CYREG_CAN0_RX14_DL, 0x4000a26c
 3253              	.set CYREG_CAN0_RX14_AMR, 0x4000a270
 3254              	.set CYREG_CAN0_RX14_ACR, 0x4000a274
 3255              	.set CYREG_CAN0_RX14_AMRD, 0x4000a278
 3256              	.set CYREG_CAN0_RX14_ACRD, 0x4000a27c
 3257              	.set CYDEV_CAN0_RX15_BASE, 0x4000a280
 3258              	.set CYDEV_CAN0_RX15_SIZE, 0x00000020
 3259              	.set CYREG_CAN0_RX15_CMD, 0x4000a280
 3260              	.set CYREG_CAN0_RX15_ID, 0x4000a284
 3261              	.set CYREG_CAN0_RX15_DH, 0x4000a288
 3262              	.set CYREG_CAN0_RX15_DL, 0x4000a28c
 3263              	.set CYREG_CAN0_RX15_AMR, 0x4000a290
 3264              	.set CYREG_CAN0_RX15_ACR, 0x4000a294
 3265              	.set CYREG_CAN0_RX15_AMRD, 0x4000a298
 3266              	.set CYREG_CAN0_RX15_ACRD, 0x4000a29c
 3267              	.set CYDEV_DFB0_BASE, 0x4000c000
 3268              	.set CYDEV_DFB0_SIZE, 0x000007b5
 3269              	.set CYDEV_DFB0_DPA_SRAM_BASE, 0x4000c000
 3270              	.set CYDEV_DFB0_DPA_SRAM_SIZE, 0x00000200
 3271              	.set CYREG_DFB0_DPA_SRAM_DATA_MBASE, 0x4000c000
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 153


 3272              	.set CYREG_DFB0_DPA_SRAM_DATA_MSIZE, 0x00000200
 3273              	.set CYDEV_DFB0_DPB_SRAM_BASE, 0x4000c200
 3274              	.set CYDEV_DFB0_DPB_SRAM_SIZE, 0x00000200
 3275              	.set CYREG_DFB0_DPB_SRAM_DATA_MBASE, 0x4000c200
 3276              	.set CYREG_DFB0_DPB_SRAM_DATA_MSIZE, 0x00000200
 3277              	.set CYDEV_DFB0_CSA_SRAM_BASE, 0x4000c400
 3278              	.set CYDEV_DFB0_CSA_SRAM_SIZE, 0x00000100
 3279              	.set CYREG_DFB0_CSA_SRAM_DATA_MBASE, 0x4000c400
 3280              	.set CYREG_DFB0_CSA_SRAM_DATA_MSIZE, 0x00000100
 3281              	.set CYDEV_DFB0_CSB_SRAM_BASE, 0x4000c500
 3282              	.set CYDEV_DFB0_CSB_SRAM_SIZE, 0x00000100
 3283              	.set CYREG_DFB0_CSB_SRAM_DATA_MBASE, 0x4000c500
 3284              	.set CYREG_DFB0_CSB_SRAM_DATA_MSIZE, 0x00000100
 3285              	.set CYDEV_DFB0_FSM_SRAM_BASE, 0x4000c600
 3286              	.set CYDEV_DFB0_FSM_SRAM_SIZE, 0x00000100
 3287              	.set CYREG_DFB0_FSM_SRAM_DATA_MBASE, 0x4000c600
 3288              	.set CYREG_DFB0_FSM_SRAM_DATA_MSIZE, 0x00000100
 3289              	.set CYDEV_DFB0_ACU_SRAM_BASE, 0x4000c700
 3290              	.set CYDEV_DFB0_ACU_SRAM_SIZE, 0x00000040
 3291              	.set CYREG_DFB0_ACU_SRAM_DATA_MBASE, 0x4000c700
 3292              	.set CYREG_DFB0_ACU_SRAM_DATA_MSIZE, 0x00000040
 3293              	.set CYREG_DFB0_CR, 0x4000c780
 3294              	.set CYREG_DFB0_SR, 0x4000c784
 3295              	.set CYREG_DFB0_RAM_EN, 0x4000c788
 3296              	.set CYREG_DFB0_RAM_DIR, 0x4000c78c
 3297              	.set CYREG_DFB0_SEMA, 0x4000c790
 3298              	.set CYREG_DFB0_DSI_CTRL, 0x4000c794
 3299              	.set CYREG_DFB0_INT_CTRL, 0x4000c798
 3300              	.set CYREG_DFB0_DMA_CTRL, 0x4000c79c
 3301              	.set CYREG_DFB0_STAGEA, 0x4000c7a0
 3302              	.set CYREG_DFB0_STAGEAM, 0x4000c7a1
 3303              	.set CYREG_DFB0_STAGEAH, 0x4000c7a2
 3304              	.set CYREG_DFB0_STAGEB, 0x4000c7a4
 3305              	.set CYREG_DFB0_STAGEBM, 0x4000c7a5
 3306              	.set CYREG_DFB0_STAGEBH, 0x4000c7a6
 3307              	.set CYREG_DFB0_HOLDA, 0x4000c7a8
 3308              	.set CYREG_DFB0_HOLDAM, 0x4000c7a9
 3309              	.set CYREG_DFB0_HOLDAH, 0x4000c7aa
 3310              	.set CYREG_DFB0_HOLDAS, 0x4000c7ab
 3311              	.set CYREG_DFB0_HOLDB, 0x4000c7ac
 3312              	.set CYREG_DFB0_HOLDBM, 0x4000c7ad
 3313              	.set CYREG_DFB0_HOLDBH, 0x4000c7ae
 3314              	.set CYREG_DFB0_HOLDBS, 0x4000c7af
 3315              	.set CYREG_DFB0_COHER, 0x4000c7b0
 3316              	.set CYREG_DFB0_DALIGN, 0x4000c7b4
 3317              	.set CYDEV_UCFG_BASE, 0x40010000
 3318              	.set CYDEV_UCFG_SIZE, 0x00005040
 3319              	.set CYDEV_UCFG_B0_BASE, 0x40010000
 3320              	.set CYDEV_UCFG_B0_SIZE, 0x00000fef
 3321              	.set CYDEV_UCFG_B0_P0_BASE, 0x40010000
 3322              	.set CYDEV_UCFG_B0_P0_SIZE, 0x000001ef
 3323              	.set CYDEV_UCFG_B0_P0_U0_BASE, 0x40010000
 3324              	.set CYDEV_UCFG_B0_P0_U0_SIZE, 0x00000070
 3325              	.set CYREG_B0_P0_U0_PLD_IT0, 0x40010000
 3326              	.set CYREG_B0_P0_U0_PLD_IT1, 0x40010004
 3327              	.set CYREG_B0_P0_U0_PLD_IT2, 0x40010008
 3328              	.set CYREG_B0_P0_U0_PLD_IT3, 0x4001000c
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 154


 3329              	.set CYREG_B0_P0_U0_PLD_IT4, 0x40010010
 3330              	.set CYREG_B0_P0_U0_PLD_IT5, 0x40010014
 3331              	.set CYREG_B0_P0_U0_PLD_IT6, 0x40010018
 3332              	.set CYREG_B0_P0_U0_PLD_IT7, 0x4001001c
 3333              	.set CYREG_B0_P0_U0_PLD_IT8, 0x40010020
 3334              	.set CYREG_B0_P0_U0_PLD_IT9, 0x40010024
 3335              	.set CYREG_B0_P0_U0_PLD_IT10, 0x40010028
 3336              	.set CYREG_B0_P0_U0_PLD_IT11, 0x4001002c
 3337              	.set CYREG_B0_P0_U0_PLD_ORT0, 0x40010030
 3338              	.set CYREG_B0_P0_U0_PLD_ORT1, 0x40010032
 3339              	.set CYREG_B0_P0_U0_PLD_ORT2, 0x40010034
 3340              	.set CYREG_B0_P0_U0_PLD_ORT3, 0x40010036
 3341              	.set CYREG_B0_P0_U0_MC_CFG_CEN_CONST, 0x40010038
 3342              	.set CYREG_B0_P0_U0_MC_CFG_XORFB, 0x4001003a
 3343              	.set CYREG_B0_P0_U0_MC_CFG_SET_RESET, 0x4001003c
 3344              	.set CYREG_B0_P0_U0_MC_CFG_BYPASS, 0x4001003e
 3345              	.set CYREG_B0_P0_U0_CFG0, 0x40010040
 3346              	.set CYREG_B0_P0_U0_CFG1, 0x40010041
 3347              	.set CYREG_B0_P0_U0_CFG2, 0x40010042
 3348              	.set CYREG_B0_P0_U0_CFG3, 0x40010043
 3349              	.set CYREG_B0_P0_U0_CFG4, 0x40010044
 3350              	.set CYREG_B0_P0_U0_CFG5, 0x40010045
 3351              	.set CYREG_B0_P0_U0_CFG6, 0x40010046
 3352              	.set CYREG_B0_P0_U0_CFG7, 0x40010047
 3353              	.set CYREG_B0_P0_U0_CFG8, 0x40010048
 3354              	.set CYREG_B0_P0_U0_CFG9, 0x40010049
 3355              	.set CYREG_B0_P0_U0_CFG10, 0x4001004a
 3356              	.set CYREG_B0_P0_U0_CFG11, 0x4001004b
 3357              	.set CYREG_B0_P0_U0_CFG12, 0x4001004c
 3358              	.set CYREG_B0_P0_U0_CFG13, 0x4001004d
 3359              	.set CYREG_B0_P0_U0_CFG14, 0x4001004e
 3360              	.set CYREG_B0_P0_U0_CFG15, 0x4001004f
 3361              	.set CYREG_B0_P0_U0_CFG16, 0x40010050
 3362              	.set CYREG_B0_P0_U0_CFG17, 0x40010051
 3363              	.set CYREG_B0_P0_U0_CFG18, 0x40010052
 3364              	.set CYREG_B0_P0_U0_CFG19, 0x40010053
 3365              	.set CYREG_B0_P0_U0_CFG20, 0x40010054
 3366              	.set CYREG_B0_P0_U0_CFG21, 0x40010055
 3367              	.set CYREG_B0_P0_U0_CFG22, 0x40010056
 3368              	.set CYREG_B0_P0_U0_CFG23, 0x40010057
 3369              	.set CYREG_B0_P0_U0_CFG24, 0x40010058
 3370              	.set CYREG_B0_P0_U0_CFG25, 0x40010059
 3371              	.set CYREG_B0_P0_U0_CFG26, 0x4001005a
 3372              	.set CYREG_B0_P0_U0_CFG27, 0x4001005b
 3373              	.set CYREG_B0_P0_U0_CFG28, 0x4001005c
 3374              	.set CYREG_B0_P0_U0_CFG29, 0x4001005d
 3375              	.set CYREG_B0_P0_U0_CFG30, 0x4001005e
 3376              	.set CYREG_B0_P0_U0_CFG31, 0x4001005f
 3377              	.set CYREG_B0_P0_U0_DCFG0, 0x40010060
 3378              	.set CYREG_B0_P0_U0_DCFG1, 0x40010062
 3379              	.set CYREG_B0_P0_U0_DCFG2, 0x40010064
 3380              	.set CYREG_B0_P0_U0_DCFG3, 0x40010066
 3381              	.set CYREG_B0_P0_U0_DCFG4, 0x40010068
 3382              	.set CYREG_B0_P0_U0_DCFG5, 0x4001006a
 3383              	.set CYREG_B0_P0_U0_DCFG6, 0x4001006c
 3384              	.set CYREG_B0_P0_U0_DCFG7, 0x4001006e
 3385              	.set CYDEV_UCFG_B0_P0_U1_BASE, 0x40010080
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 155


 3386              	.set CYDEV_UCFG_B0_P0_U1_SIZE, 0x00000070
 3387              	.set CYREG_B0_P0_U1_PLD_IT0, 0x40010080
 3388              	.set CYREG_B0_P0_U1_PLD_IT1, 0x40010084
 3389              	.set CYREG_B0_P0_U1_PLD_IT2, 0x40010088
 3390              	.set CYREG_B0_P0_U1_PLD_IT3, 0x4001008c
 3391              	.set CYREG_B0_P0_U1_PLD_IT4, 0x40010090
 3392              	.set CYREG_B0_P0_U1_PLD_IT5, 0x40010094
 3393              	.set CYREG_B0_P0_U1_PLD_IT6, 0x40010098
 3394              	.set CYREG_B0_P0_U1_PLD_IT7, 0x4001009c
 3395              	.set CYREG_B0_P0_U1_PLD_IT8, 0x400100a0
 3396              	.set CYREG_B0_P0_U1_PLD_IT9, 0x400100a4
 3397              	.set CYREG_B0_P0_U1_PLD_IT10, 0x400100a8
 3398              	.set CYREG_B0_P0_U1_PLD_IT11, 0x400100ac
 3399              	.set CYREG_B0_P0_U1_PLD_ORT0, 0x400100b0
 3400              	.set CYREG_B0_P0_U1_PLD_ORT1, 0x400100b2
 3401              	.set CYREG_B0_P0_U1_PLD_ORT2, 0x400100b4
 3402              	.set CYREG_B0_P0_U1_PLD_ORT3, 0x400100b6
 3403              	.set CYREG_B0_P0_U1_MC_CFG_CEN_CONST, 0x400100b8
 3404              	.set CYREG_B0_P0_U1_MC_CFG_XORFB, 0x400100ba
 3405              	.set CYREG_B0_P0_U1_MC_CFG_SET_RESET, 0x400100bc
 3406              	.set CYREG_B0_P0_U1_MC_CFG_BYPASS, 0x400100be
 3407              	.set CYREG_B0_P0_U1_CFG0, 0x400100c0
 3408              	.set CYREG_B0_P0_U1_CFG1, 0x400100c1
 3409              	.set CYREG_B0_P0_U1_CFG2, 0x400100c2
 3410              	.set CYREG_B0_P0_U1_CFG3, 0x400100c3
 3411              	.set CYREG_B0_P0_U1_CFG4, 0x400100c4
 3412              	.set CYREG_B0_P0_U1_CFG5, 0x400100c5
 3413              	.set CYREG_B0_P0_U1_CFG6, 0x400100c6
 3414              	.set CYREG_B0_P0_U1_CFG7, 0x400100c7
 3415              	.set CYREG_B0_P0_U1_CFG8, 0x400100c8
 3416              	.set CYREG_B0_P0_U1_CFG9, 0x400100c9
 3417              	.set CYREG_B0_P0_U1_CFG10, 0x400100ca
 3418              	.set CYREG_B0_P0_U1_CFG11, 0x400100cb
 3419              	.set CYREG_B0_P0_U1_CFG12, 0x400100cc
 3420              	.set CYREG_B0_P0_U1_CFG13, 0x400100cd
 3421              	.set CYREG_B0_P0_U1_CFG14, 0x400100ce
 3422              	.set CYREG_B0_P0_U1_CFG15, 0x400100cf
 3423              	.set CYREG_B0_P0_U1_CFG16, 0x400100d0
 3424              	.set CYREG_B0_P0_U1_CFG17, 0x400100d1
 3425              	.set CYREG_B0_P0_U1_CFG18, 0x400100d2
 3426              	.set CYREG_B0_P0_U1_CFG19, 0x400100d3
 3427              	.set CYREG_B0_P0_U1_CFG20, 0x400100d4
 3428              	.set CYREG_B0_P0_U1_CFG21, 0x400100d5
 3429              	.set CYREG_B0_P0_U1_CFG22, 0x400100d6
 3430              	.set CYREG_B0_P0_U1_CFG23, 0x400100d7
 3431              	.set CYREG_B0_P0_U1_CFG24, 0x400100d8
 3432              	.set CYREG_B0_P0_U1_CFG25, 0x400100d9
 3433              	.set CYREG_B0_P0_U1_CFG26, 0x400100da
 3434              	.set CYREG_B0_P0_U1_CFG27, 0x400100db
 3435              	.set CYREG_B0_P0_U1_CFG28, 0x400100dc
 3436              	.set CYREG_B0_P0_U1_CFG29, 0x400100dd
 3437              	.set CYREG_B0_P0_U1_CFG30, 0x400100de
 3438              	.set CYREG_B0_P0_U1_CFG31, 0x400100df
 3439              	.set CYREG_B0_P0_U1_DCFG0, 0x400100e0
 3440              	.set CYREG_B0_P0_U1_DCFG1, 0x400100e2
 3441              	.set CYREG_B0_P0_U1_DCFG2, 0x400100e4
 3442              	.set CYREG_B0_P0_U1_DCFG3, 0x400100e6
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 156


 3443              	.set CYREG_B0_P0_U1_DCFG4, 0x400100e8
 3444              	.set CYREG_B0_P0_U1_DCFG5, 0x400100ea
 3445              	.set CYREG_B0_P0_U1_DCFG6, 0x400100ec
 3446              	.set CYREG_B0_P0_U1_DCFG7, 0x400100ee
 3447              	.set CYDEV_UCFG_B0_P0_ROUTE_BASE, 0x40010100
 3448              	.set CYDEV_UCFG_B0_P0_ROUTE_SIZE, 0x000000ef
 3449              	.set CYDEV_UCFG_B0_P1_BASE, 0x40010200
 3450              	.set CYDEV_UCFG_B0_P1_SIZE, 0x000001ef
 3451              	.set CYDEV_UCFG_B0_P1_U0_BASE, 0x40010200
 3452              	.set CYDEV_UCFG_B0_P1_U0_SIZE, 0x00000070
 3453              	.set CYREG_B0_P1_U0_PLD_IT0, 0x40010200
 3454              	.set CYREG_B0_P1_U0_PLD_IT1, 0x40010204
 3455              	.set CYREG_B0_P1_U0_PLD_IT2, 0x40010208
 3456              	.set CYREG_B0_P1_U0_PLD_IT3, 0x4001020c
 3457              	.set CYREG_B0_P1_U0_PLD_IT4, 0x40010210
 3458              	.set CYREG_B0_P1_U0_PLD_IT5, 0x40010214
 3459              	.set CYREG_B0_P1_U0_PLD_IT6, 0x40010218
 3460              	.set CYREG_B0_P1_U0_PLD_IT7, 0x4001021c
 3461              	.set CYREG_B0_P1_U0_PLD_IT8, 0x40010220
 3462              	.set CYREG_B0_P1_U0_PLD_IT9, 0x40010224
 3463              	.set CYREG_B0_P1_U0_PLD_IT10, 0x40010228
 3464              	.set CYREG_B0_P1_U0_PLD_IT11, 0x4001022c
 3465              	.set CYREG_B0_P1_U0_PLD_ORT0, 0x40010230
 3466              	.set CYREG_B0_P1_U0_PLD_ORT1, 0x40010232
 3467              	.set CYREG_B0_P1_U0_PLD_ORT2, 0x40010234
 3468              	.set CYREG_B0_P1_U0_PLD_ORT3, 0x40010236
 3469              	.set CYREG_B0_P1_U0_MC_CFG_CEN_CONST, 0x40010238
 3470              	.set CYREG_B0_P1_U0_MC_CFG_XORFB, 0x4001023a
 3471              	.set CYREG_B0_P1_U0_MC_CFG_SET_RESET, 0x4001023c
 3472              	.set CYREG_B0_P1_U0_MC_CFG_BYPASS, 0x4001023e
 3473              	.set CYREG_B0_P1_U0_CFG0, 0x40010240
 3474              	.set CYREG_B0_P1_U0_CFG1, 0x40010241
 3475              	.set CYREG_B0_P1_U0_CFG2, 0x40010242
 3476              	.set CYREG_B0_P1_U0_CFG3, 0x40010243
 3477              	.set CYREG_B0_P1_U0_CFG4, 0x40010244
 3478              	.set CYREG_B0_P1_U0_CFG5, 0x40010245
 3479              	.set CYREG_B0_P1_U0_CFG6, 0x40010246
 3480              	.set CYREG_B0_P1_U0_CFG7, 0x40010247
 3481              	.set CYREG_B0_P1_U0_CFG8, 0x40010248
 3482              	.set CYREG_B0_P1_U0_CFG9, 0x40010249
 3483              	.set CYREG_B0_P1_U0_CFG10, 0x4001024a
 3484              	.set CYREG_B0_P1_U0_CFG11, 0x4001024b
 3485              	.set CYREG_B0_P1_U0_CFG12, 0x4001024c
 3486              	.set CYREG_B0_P1_U0_CFG13, 0x4001024d
 3487              	.set CYREG_B0_P1_U0_CFG14, 0x4001024e
 3488              	.set CYREG_B0_P1_U0_CFG15, 0x4001024f
 3489              	.set CYREG_B0_P1_U0_CFG16, 0x40010250
 3490              	.set CYREG_B0_P1_U0_CFG17, 0x40010251
 3491              	.set CYREG_B0_P1_U0_CFG18, 0x40010252
 3492              	.set CYREG_B0_P1_U0_CFG19, 0x40010253
 3493              	.set CYREG_B0_P1_U0_CFG20, 0x40010254
 3494              	.set CYREG_B0_P1_U0_CFG21, 0x40010255
 3495              	.set CYREG_B0_P1_U0_CFG22, 0x40010256
 3496              	.set CYREG_B0_P1_U0_CFG23, 0x40010257
 3497              	.set CYREG_B0_P1_U0_CFG24, 0x40010258
 3498              	.set CYREG_B0_P1_U0_CFG25, 0x40010259
 3499              	.set CYREG_B0_P1_U0_CFG26, 0x4001025a
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 157


 3500              	.set CYREG_B0_P1_U0_CFG27, 0x4001025b
 3501              	.set CYREG_B0_P1_U0_CFG28, 0x4001025c
 3502              	.set CYREG_B0_P1_U0_CFG29, 0x4001025d
 3503              	.set CYREG_B0_P1_U0_CFG30, 0x4001025e
 3504              	.set CYREG_B0_P1_U0_CFG31, 0x4001025f
 3505              	.set CYREG_B0_P1_U0_DCFG0, 0x40010260
 3506              	.set CYREG_B0_P1_U0_DCFG1, 0x40010262
 3507              	.set CYREG_B0_P1_U0_DCFG2, 0x40010264
 3508              	.set CYREG_B0_P1_U0_DCFG3, 0x40010266
 3509              	.set CYREG_B0_P1_U0_DCFG4, 0x40010268
 3510              	.set CYREG_B0_P1_U0_DCFG5, 0x4001026a
 3511              	.set CYREG_B0_P1_U0_DCFG6, 0x4001026c
 3512              	.set CYREG_B0_P1_U0_DCFG7, 0x4001026e
 3513              	.set CYDEV_UCFG_B0_P1_U1_BASE, 0x40010280
 3514              	.set CYDEV_UCFG_B0_P1_U1_SIZE, 0x00000070
 3515              	.set CYREG_B0_P1_U1_PLD_IT0, 0x40010280
 3516              	.set CYREG_B0_P1_U1_PLD_IT1, 0x40010284
 3517              	.set CYREG_B0_P1_U1_PLD_IT2, 0x40010288
 3518              	.set CYREG_B0_P1_U1_PLD_IT3, 0x4001028c
 3519              	.set CYREG_B0_P1_U1_PLD_IT4, 0x40010290
 3520              	.set CYREG_B0_P1_U1_PLD_IT5, 0x40010294
 3521              	.set CYREG_B0_P1_U1_PLD_IT6, 0x40010298
 3522              	.set CYREG_B0_P1_U1_PLD_IT7, 0x4001029c
 3523              	.set CYREG_B0_P1_U1_PLD_IT8, 0x400102a0
 3524              	.set CYREG_B0_P1_U1_PLD_IT9, 0x400102a4
 3525              	.set CYREG_B0_P1_U1_PLD_IT10, 0x400102a8
 3526              	.set CYREG_B0_P1_U1_PLD_IT11, 0x400102ac
 3527              	.set CYREG_B0_P1_U1_PLD_ORT0, 0x400102b0
 3528              	.set CYREG_B0_P1_U1_PLD_ORT1, 0x400102b2
 3529              	.set CYREG_B0_P1_U1_PLD_ORT2, 0x400102b4
 3530              	.set CYREG_B0_P1_U1_PLD_ORT3, 0x400102b6
 3531              	.set CYREG_B0_P1_U1_MC_CFG_CEN_CONST, 0x400102b8
 3532              	.set CYREG_B0_P1_U1_MC_CFG_XORFB, 0x400102ba
 3533              	.set CYREG_B0_P1_U1_MC_CFG_SET_RESET, 0x400102bc
 3534              	.set CYREG_B0_P1_U1_MC_CFG_BYPASS, 0x400102be
 3535              	.set CYREG_B0_P1_U1_CFG0, 0x400102c0
 3536              	.set CYREG_B0_P1_U1_CFG1, 0x400102c1
 3537              	.set CYREG_B0_P1_U1_CFG2, 0x400102c2
 3538              	.set CYREG_B0_P1_U1_CFG3, 0x400102c3
 3539              	.set CYREG_B0_P1_U1_CFG4, 0x400102c4
 3540              	.set CYREG_B0_P1_U1_CFG5, 0x400102c5
 3541              	.set CYREG_B0_P1_U1_CFG6, 0x400102c6
 3542              	.set CYREG_B0_P1_U1_CFG7, 0x400102c7
 3543              	.set CYREG_B0_P1_U1_CFG8, 0x400102c8
 3544              	.set CYREG_B0_P1_U1_CFG9, 0x400102c9
 3545              	.set CYREG_B0_P1_U1_CFG10, 0x400102ca
 3546              	.set CYREG_B0_P1_U1_CFG11, 0x400102cb
 3547              	.set CYREG_B0_P1_U1_CFG12, 0x400102cc
 3548              	.set CYREG_B0_P1_U1_CFG13, 0x400102cd
 3549              	.set CYREG_B0_P1_U1_CFG14, 0x400102ce
 3550              	.set CYREG_B0_P1_U1_CFG15, 0x400102cf
 3551              	.set CYREG_B0_P1_U1_CFG16, 0x400102d0
 3552              	.set CYREG_B0_P1_U1_CFG17, 0x400102d1
 3553              	.set CYREG_B0_P1_U1_CFG18, 0x400102d2
 3554              	.set CYREG_B0_P1_U1_CFG19, 0x400102d3
 3555              	.set CYREG_B0_P1_U1_CFG20, 0x400102d4
 3556              	.set CYREG_B0_P1_U1_CFG21, 0x400102d5
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 158


 3557              	.set CYREG_B0_P1_U1_CFG22, 0x400102d6
 3558              	.set CYREG_B0_P1_U1_CFG23, 0x400102d7
 3559              	.set CYREG_B0_P1_U1_CFG24, 0x400102d8
 3560              	.set CYREG_B0_P1_U1_CFG25, 0x400102d9
 3561              	.set CYREG_B0_P1_U1_CFG26, 0x400102da
 3562              	.set CYREG_B0_P1_U1_CFG27, 0x400102db
 3563              	.set CYREG_B0_P1_U1_CFG28, 0x400102dc
 3564              	.set CYREG_B0_P1_U1_CFG29, 0x400102dd
 3565              	.set CYREG_B0_P1_U1_CFG30, 0x400102de
 3566              	.set CYREG_B0_P1_U1_CFG31, 0x400102df
 3567              	.set CYREG_B0_P1_U1_DCFG0, 0x400102e0
 3568              	.set CYREG_B0_P1_U1_DCFG1, 0x400102e2
 3569              	.set CYREG_B0_P1_U1_DCFG2, 0x400102e4
 3570              	.set CYREG_B0_P1_U1_DCFG3, 0x400102e6
 3571              	.set CYREG_B0_P1_U1_DCFG4, 0x400102e8
 3572              	.set CYREG_B0_P1_U1_DCFG5, 0x400102ea
 3573              	.set CYREG_B0_P1_U1_DCFG6, 0x400102ec
 3574              	.set CYREG_B0_P1_U1_DCFG7, 0x400102ee
 3575              	.set CYDEV_UCFG_B0_P1_ROUTE_BASE, 0x40010300
 3576              	.set CYDEV_UCFG_B0_P1_ROUTE_SIZE, 0x000000ef
 3577              	.set CYDEV_UCFG_B0_P2_BASE, 0x40010400
 3578              	.set CYDEV_UCFG_B0_P2_SIZE, 0x000001ef
 3579              	.set CYDEV_UCFG_B0_P2_U0_BASE, 0x40010400
 3580              	.set CYDEV_UCFG_B0_P2_U0_SIZE, 0x00000070
 3581              	.set CYREG_B0_P2_U0_PLD_IT0, 0x40010400
 3582              	.set CYREG_B0_P2_U0_PLD_IT1, 0x40010404
 3583              	.set CYREG_B0_P2_U0_PLD_IT2, 0x40010408
 3584              	.set CYREG_B0_P2_U0_PLD_IT3, 0x4001040c
 3585              	.set CYREG_B0_P2_U0_PLD_IT4, 0x40010410
 3586              	.set CYREG_B0_P2_U0_PLD_IT5, 0x40010414
 3587              	.set CYREG_B0_P2_U0_PLD_IT6, 0x40010418
 3588              	.set CYREG_B0_P2_U0_PLD_IT7, 0x4001041c
 3589              	.set CYREG_B0_P2_U0_PLD_IT8, 0x40010420
 3590              	.set CYREG_B0_P2_U0_PLD_IT9, 0x40010424
 3591              	.set CYREG_B0_P2_U0_PLD_IT10, 0x40010428
 3592              	.set CYREG_B0_P2_U0_PLD_IT11, 0x4001042c
 3593              	.set CYREG_B0_P2_U0_PLD_ORT0, 0x40010430
 3594              	.set CYREG_B0_P2_U0_PLD_ORT1, 0x40010432
 3595              	.set CYREG_B0_P2_U0_PLD_ORT2, 0x40010434
 3596              	.set CYREG_B0_P2_U0_PLD_ORT3, 0x40010436
 3597              	.set CYREG_B0_P2_U0_MC_CFG_CEN_CONST, 0x40010438
 3598              	.set CYREG_B0_P2_U0_MC_CFG_XORFB, 0x4001043a
 3599              	.set CYREG_B0_P2_U0_MC_CFG_SET_RESET, 0x4001043c
 3600              	.set CYREG_B0_P2_U0_MC_CFG_BYPASS, 0x4001043e
 3601              	.set CYREG_B0_P2_U0_CFG0, 0x40010440
 3602              	.set CYREG_B0_P2_U0_CFG1, 0x40010441
 3603              	.set CYREG_B0_P2_U0_CFG2, 0x40010442
 3604              	.set CYREG_B0_P2_U0_CFG3, 0x40010443
 3605              	.set CYREG_B0_P2_U0_CFG4, 0x40010444
 3606              	.set CYREG_B0_P2_U0_CFG5, 0x40010445
 3607              	.set CYREG_B0_P2_U0_CFG6, 0x40010446
 3608              	.set CYREG_B0_P2_U0_CFG7, 0x40010447
 3609              	.set CYREG_B0_P2_U0_CFG8, 0x40010448
 3610              	.set CYREG_B0_P2_U0_CFG9, 0x40010449
 3611              	.set CYREG_B0_P2_U0_CFG10, 0x4001044a
 3612              	.set CYREG_B0_P2_U0_CFG11, 0x4001044b
 3613              	.set CYREG_B0_P2_U0_CFG12, 0x4001044c
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 159


 3614              	.set CYREG_B0_P2_U0_CFG13, 0x4001044d
 3615              	.set CYREG_B0_P2_U0_CFG14, 0x4001044e
 3616              	.set CYREG_B0_P2_U0_CFG15, 0x4001044f
 3617              	.set CYREG_B0_P2_U0_CFG16, 0x40010450
 3618              	.set CYREG_B0_P2_U0_CFG17, 0x40010451
 3619              	.set CYREG_B0_P2_U0_CFG18, 0x40010452
 3620              	.set CYREG_B0_P2_U0_CFG19, 0x40010453
 3621              	.set CYREG_B0_P2_U0_CFG20, 0x40010454
 3622              	.set CYREG_B0_P2_U0_CFG21, 0x40010455
 3623              	.set CYREG_B0_P2_U0_CFG22, 0x40010456
 3624              	.set CYREG_B0_P2_U0_CFG23, 0x40010457
 3625              	.set CYREG_B0_P2_U0_CFG24, 0x40010458
 3626              	.set CYREG_B0_P2_U0_CFG25, 0x40010459
 3627              	.set CYREG_B0_P2_U0_CFG26, 0x4001045a
 3628              	.set CYREG_B0_P2_U0_CFG27, 0x4001045b
 3629              	.set CYREG_B0_P2_U0_CFG28, 0x4001045c
 3630              	.set CYREG_B0_P2_U0_CFG29, 0x4001045d
 3631              	.set CYREG_B0_P2_U0_CFG30, 0x4001045e
 3632              	.set CYREG_B0_P2_U0_CFG31, 0x4001045f
 3633              	.set CYREG_B0_P2_U0_DCFG0, 0x40010460
 3634              	.set CYREG_B0_P2_U0_DCFG1, 0x40010462
 3635              	.set CYREG_B0_P2_U0_DCFG2, 0x40010464
 3636              	.set CYREG_B0_P2_U0_DCFG3, 0x40010466
 3637              	.set CYREG_B0_P2_U0_DCFG4, 0x40010468
 3638              	.set CYREG_B0_P2_U0_DCFG5, 0x4001046a
 3639              	.set CYREG_B0_P2_U0_DCFG6, 0x4001046c
 3640              	.set CYREG_B0_P2_U0_DCFG7, 0x4001046e
 3641              	.set CYDEV_UCFG_B0_P2_U1_BASE, 0x40010480
 3642              	.set CYDEV_UCFG_B0_P2_U1_SIZE, 0x00000070
 3643              	.set CYREG_B0_P2_U1_PLD_IT0, 0x40010480
 3644              	.set CYREG_B0_P2_U1_PLD_IT1, 0x40010484
 3645              	.set CYREG_B0_P2_U1_PLD_IT2, 0x40010488
 3646              	.set CYREG_B0_P2_U1_PLD_IT3, 0x4001048c
 3647              	.set CYREG_B0_P2_U1_PLD_IT4, 0x40010490
 3648              	.set CYREG_B0_P2_U1_PLD_IT5, 0x40010494
 3649              	.set CYREG_B0_P2_U1_PLD_IT6, 0x40010498
 3650              	.set CYREG_B0_P2_U1_PLD_IT7, 0x4001049c
 3651              	.set CYREG_B0_P2_U1_PLD_IT8, 0x400104a0
 3652              	.set CYREG_B0_P2_U1_PLD_IT9, 0x400104a4
 3653              	.set CYREG_B0_P2_U1_PLD_IT10, 0x400104a8
 3654              	.set CYREG_B0_P2_U1_PLD_IT11, 0x400104ac
 3655              	.set CYREG_B0_P2_U1_PLD_ORT0, 0x400104b0
 3656              	.set CYREG_B0_P2_U1_PLD_ORT1, 0x400104b2
 3657              	.set CYREG_B0_P2_U1_PLD_ORT2, 0x400104b4
 3658              	.set CYREG_B0_P2_U1_PLD_ORT3, 0x400104b6
 3659              	.set CYREG_B0_P2_U1_MC_CFG_CEN_CONST, 0x400104b8
 3660              	.set CYREG_B0_P2_U1_MC_CFG_XORFB, 0x400104ba
 3661              	.set CYREG_B0_P2_U1_MC_CFG_SET_RESET, 0x400104bc
 3662              	.set CYREG_B0_P2_U1_MC_CFG_BYPASS, 0x400104be
 3663              	.set CYREG_B0_P2_U1_CFG0, 0x400104c0
 3664              	.set CYREG_B0_P2_U1_CFG1, 0x400104c1
 3665              	.set CYREG_B0_P2_U1_CFG2, 0x400104c2
 3666              	.set CYREG_B0_P2_U1_CFG3, 0x400104c3
 3667              	.set CYREG_B0_P2_U1_CFG4, 0x400104c4
 3668              	.set CYREG_B0_P2_U1_CFG5, 0x400104c5
 3669              	.set CYREG_B0_P2_U1_CFG6, 0x400104c6
 3670              	.set CYREG_B0_P2_U1_CFG7, 0x400104c7
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 160


 3671              	.set CYREG_B0_P2_U1_CFG8, 0x400104c8
 3672              	.set CYREG_B0_P2_U1_CFG9, 0x400104c9
 3673              	.set CYREG_B0_P2_U1_CFG10, 0x400104ca
 3674              	.set CYREG_B0_P2_U1_CFG11, 0x400104cb
 3675              	.set CYREG_B0_P2_U1_CFG12, 0x400104cc
 3676              	.set CYREG_B0_P2_U1_CFG13, 0x400104cd
 3677              	.set CYREG_B0_P2_U1_CFG14, 0x400104ce
 3678              	.set CYREG_B0_P2_U1_CFG15, 0x400104cf
 3679              	.set CYREG_B0_P2_U1_CFG16, 0x400104d0
 3680              	.set CYREG_B0_P2_U1_CFG17, 0x400104d1
 3681              	.set CYREG_B0_P2_U1_CFG18, 0x400104d2
 3682              	.set CYREG_B0_P2_U1_CFG19, 0x400104d3
 3683              	.set CYREG_B0_P2_U1_CFG20, 0x400104d4
 3684              	.set CYREG_B0_P2_U1_CFG21, 0x400104d5
 3685              	.set CYREG_B0_P2_U1_CFG22, 0x400104d6
 3686              	.set CYREG_B0_P2_U1_CFG23, 0x400104d7
 3687              	.set CYREG_B0_P2_U1_CFG24, 0x400104d8
 3688              	.set CYREG_B0_P2_U1_CFG25, 0x400104d9
 3689              	.set CYREG_B0_P2_U1_CFG26, 0x400104da
 3690              	.set CYREG_B0_P2_U1_CFG27, 0x400104db
 3691              	.set CYREG_B0_P2_U1_CFG28, 0x400104dc
 3692              	.set CYREG_B0_P2_U1_CFG29, 0x400104dd
 3693              	.set CYREG_B0_P2_U1_CFG30, 0x400104de
 3694              	.set CYREG_B0_P2_U1_CFG31, 0x400104df
 3695              	.set CYREG_B0_P2_U1_DCFG0, 0x400104e0
 3696              	.set CYREG_B0_P2_U1_DCFG1, 0x400104e2
 3697              	.set CYREG_B0_P2_U1_DCFG2, 0x400104e4
 3698              	.set CYREG_B0_P2_U1_DCFG3, 0x400104e6
 3699              	.set CYREG_B0_P2_U1_DCFG4, 0x400104e8
 3700              	.set CYREG_B0_P2_U1_DCFG5, 0x400104ea
 3701              	.set CYREG_B0_P2_U1_DCFG6, 0x400104ec
 3702              	.set CYREG_B0_P2_U1_DCFG7, 0x400104ee
 3703              	.set CYDEV_UCFG_B0_P2_ROUTE_BASE, 0x40010500
 3704              	.set CYDEV_UCFG_B0_P2_ROUTE_SIZE, 0x000000ef
 3705              	.set CYDEV_UCFG_B0_P3_BASE, 0x40010600
 3706              	.set CYDEV_UCFG_B0_P3_SIZE, 0x000001ef
 3707              	.set CYDEV_UCFG_B0_P3_U0_BASE, 0x40010600
 3708              	.set CYDEV_UCFG_B0_P3_U0_SIZE, 0x00000070
 3709              	.set CYREG_B0_P3_U0_PLD_IT0, 0x40010600
 3710              	.set CYREG_B0_P3_U0_PLD_IT1, 0x40010604
 3711              	.set CYREG_B0_P3_U0_PLD_IT2, 0x40010608
 3712              	.set CYREG_B0_P3_U0_PLD_IT3, 0x4001060c
 3713              	.set CYREG_B0_P3_U0_PLD_IT4, 0x40010610
 3714              	.set CYREG_B0_P3_U0_PLD_IT5, 0x40010614
 3715              	.set CYREG_B0_P3_U0_PLD_IT6, 0x40010618
 3716              	.set CYREG_B0_P3_U0_PLD_IT7, 0x4001061c
 3717              	.set CYREG_B0_P3_U0_PLD_IT8, 0x40010620
 3718              	.set CYREG_B0_P3_U0_PLD_IT9, 0x40010624
 3719              	.set CYREG_B0_P3_U0_PLD_IT10, 0x40010628
 3720              	.set CYREG_B0_P3_U0_PLD_IT11, 0x4001062c
 3721              	.set CYREG_B0_P3_U0_PLD_ORT0, 0x40010630
 3722              	.set CYREG_B0_P3_U0_PLD_ORT1, 0x40010632
 3723              	.set CYREG_B0_P3_U0_PLD_ORT2, 0x40010634
 3724              	.set CYREG_B0_P3_U0_PLD_ORT3, 0x40010636
 3725              	.set CYREG_B0_P3_U0_MC_CFG_CEN_CONST, 0x40010638
 3726              	.set CYREG_B0_P3_U0_MC_CFG_XORFB, 0x4001063a
 3727              	.set CYREG_B0_P3_U0_MC_CFG_SET_RESET, 0x4001063c
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 161


 3728              	.set CYREG_B0_P3_U0_MC_CFG_BYPASS, 0x4001063e
 3729              	.set CYREG_B0_P3_U0_CFG0, 0x40010640
 3730              	.set CYREG_B0_P3_U0_CFG1, 0x40010641
 3731              	.set CYREG_B0_P3_U0_CFG2, 0x40010642
 3732              	.set CYREG_B0_P3_U0_CFG3, 0x40010643
 3733              	.set CYREG_B0_P3_U0_CFG4, 0x40010644
 3734              	.set CYREG_B0_P3_U0_CFG5, 0x40010645
 3735              	.set CYREG_B0_P3_U0_CFG6, 0x40010646
 3736              	.set CYREG_B0_P3_U0_CFG7, 0x40010647
 3737              	.set CYREG_B0_P3_U0_CFG8, 0x40010648
 3738              	.set CYREG_B0_P3_U0_CFG9, 0x40010649
 3739              	.set CYREG_B0_P3_U0_CFG10, 0x4001064a
 3740              	.set CYREG_B0_P3_U0_CFG11, 0x4001064b
 3741              	.set CYREG_B0_P3_U0_CFG12, 0x4001064c
 3742              	.set CYREG_B0_P3_U0_CFG13, 0x4001064d
 3743              	.set CYREG_B0_P3_U0_CFG14, 0x4001064e
 3744              	.set CYREG_B0_P3_U0_CFG15, 0x4001064f
 3745              	.set CYREG_B0_P3_U0_CFG16, 0x40010650
 3746              	.set CYREG_B0_P3_U0_CFG17, 0x40010651
 3747              	.set CYREG_B0_P3_U0_CFG18, 0x40010652
 3748              	.set CYREG_B0_P3_U0_CFG19, 0x40010653
 3749              	.set CYREG_B0_P3_U0_CFG20, 0x40010654
 3750              	.set CYREG_B0_P3_U0_CFG21, 0x40010655
 3751              	.set CYREG_B0_P3_U0_CFG22, 0x40010656
 3752              	.set CYREG_B0_P3_U0_CFG23, 0x40010657
 3753              	.set CYREG_B0_P3_U0_CFG24, 0x40010658
 3754              	.set CYREG_B0_P3_U0_CFG25, 0x40010659
 3755              	.set CYREG_B0_P3_U0_CFG26, 0x4001065a
 3756              	.set CYREG_B0_P3_U0_CFG27, 0x4001065b
 3757              	.set CYREG_B0_P3_U0_CFG28, 0x4001065c
 3758              	.set CYREG_B0_P3_U0_CFG29, 0x4001065d
 3759              	.set CYREG_B0_P3_U0_CFG30, 0x4001065e
 3760              	.set CYREG_B0_P3_U0_CFG31, 0x4001065f
 3761              	.set CYREG_B0_P3_U0_DCFG0, 0x40010660
 3762              	.set CYREG_B0_P3_U0_DCFG1, 0x40010662
 3763              	.set CYREG_B0_P3_U0_DCFG2, 0x40010664
 3764              	.set CYREG_B0_P3_U0_DCFG3, 0x40010666
 3765              	.set CYREG_B0_P3_U0_DCFG4, 0x40010668
 3766              	.set CYREG_B0_P3_U0_DCFG5, 0x4001066a
 3767              	.set CYREG_B0_P3_U0_DCFG6, 0x4001066c
 3768              	.set CYREG_B0_P3_U0_DCFG7, 0x4001066e
 3769              	.set CYDEV_UCFG_B0_P3_U1_BASE, 0x40010680
 3770              	.set CYDEV_UCFG_B0_P3_U1_SIZE, 0x00000070
 3771              	.set CYREG_B0_P3_U1_PLD_IT0, 0x40010680
 3772              	.set CYREG_B0_P3_U1_PLD_IT1, 0x40010684
 3773              	.set CYREG_B0_P3_U1_PLD_IT2, 0x40010688
 3774              	.set CYREG_B0_P3_U1_PLD_IT3, 0x4001068c
 3775              	.set CYREG_B0_P3_U1_PLD_IT4, 0x40010690
 3776              	.set CYREG_B0_P3_U1_PLD_IT5, 0x40010694
 3777              	.set CYREG_B0_P3_U1_PLD_IT6, 0x40010698
 3778              	.set CYREG_B0_P3_U1_PLD_IT7, 0x4001069c
 3779              	.set CYREG_B0_P3_U1_PLD_IT8, 0x400106a0
 3780              	.set CYREG_B0_P3_U1_PLD_IT9, 0x400106a4
 3781              	.set CYREG_B0_P3_U1_PLD_IT10, 0x400106a8
 3782              	.set CYREG_B0_P3_U1_PLD_IT11, 0x400106ac
 3783              	.set CYREG_B0_P3_U1_PLD_ORT0, 0x400106b0
 3784              	.set CYREG_B0_P3_U1_PLD_ORT1, 0x400106b2
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 162


 3785              	.set CYREG_B0_P3_U1_PLD_ORT2, 0x400106b4
 3786              	.set CYREG_B0_P3_U1_PLD_ORT3, 0x400106b6
 3787              	.set CYREG_B0_P3_U1_MC_CFG_CEN_CONST, 0x400106b8
 3788              	.set CYREG_B0_P3_U1_MC_CFG_XORFB, 0x400106ba
 3789              	.set CYREG_B0_P3_U1_MC_CFG_SET_RESET, 0x400106bc
 3790              	.set CYREG_B0_P3_U1_MC_CFG_BYPASS, 0x400106be
 3791              	.set CYREG_B0_P3_U1_CFG0, 0x400106c0
 3792              	.set CYREG_B0_P3_U1_CFG1, 0x400106c1
 3793              	.set CYREG_B0_P3_U1_CFG2, 0x400106c2
 3794              	.set CYREG_B0_P3_U1_CFG3, 0x400106c3
 3795              	.set CYREG_B0_P3_U1_CFG4, 0x400106c4
 3796              	.set CYREG_B0_P3_U1_CFG5, 0x400106c5
 3797              	.set CYREG_B0_P3_U1_CFG6, 0x400106c6
 3798              	.set CYREG_B0_P3_U1_CFG7, 0x400106c7
 3799              	.set CYREG_B0_P3_U1_CFG8, 0x400106c8
 3800              	.set CYREG_B0_P3_U1_CFG9, 0x400106c9
 3801              	.set CYREG_B0_P3_U1_CFG10, 0x400106ca
 3802              	.set CYREG_B0_P3_U1_CFG11, 0x400106cb
 3803              	.set CYREG_B0_P3_U1_CFG12, 0x400106cc
 3804              	.set CYREG_B0_P3_U1_CFG13, 0x400106cd
 3805              	.set CYREG_B0_P3_U1_CFG14, 0x400106ce
 3806              	.set CYREG_B0_P3_U1_CFG15, 0x400106cf
 3807              	.set CYREG_B0_P3_U1_CFG16, 0x400106d0
 3808              	.set CYREG_B0_P3_U1_CFG17, 0x400106d1
 3809              	.set CYREG_B0_P3_U1_CFG18, 0x400106d2
 3810              	.set CYREG_B0_P3_U1_CFG19, 0x400106d3
 3811              	.set CYREG_B0_P3_U1_CFG20, 0x400106d4
 3812              	.set CYREG_B0_P3_U1_CFG21, 0x400106d5
 3813              	.set CYREG_B0_P3_U1_CFG22, 0x400106d6
 3814              	.set CYREG_B0_P3_U1_CFG23, 0x400106d7
 3815              	.set CYREG_B0_P3_U1_CFG24, 0x400106d8
 3816              	.set CYREG_B0_P3_U1_CFG25, 0x400106d9
 3817              	.set CYREG_B0_P3_U1_CFG26, 0x400106da
 3818              	.set CYREG_B0_P3_U1_CFG27, 0x400106db
 3819              	.set CYREG_B0_P3_U1_CFG28, 0x400106dc
 3820              	.set CYREG_B0_P3_U1_CFG29, 0x400106dd
 3821              	.set CYREG_B0_P3_U1_CFG30, 0x400106de
 3822              	.set CYREG_B0_P3_U1_CFG31, 0x400106df
 3823              	.set CYREG_B0_P3_U1_DCFG0, 0x400106e0
 3824              	.set CYREG_B0_P3_U1_DCFG1, 0x400106e2
 3825              	.set CYREG_B0_P3_U1_DCFG2, 0x400106e4
 3826              	.set CYREG_B0_P3_U1_DCFG3, 0x400106e6
 3827              	.set CYREG_B0_P3_U1_DCFG4, 0x400106e8
 3828              	.set CYREG_B0_P3_U1_DCFG5, 0x400106ea
 3829              	.set CYREG_B0_P3_U1_DCFG6, 0x400106ec
 3830              	.set CYREG_B0_P3_U1_DCFG7, 0x400106ee
 3831              	.set CYDEV_UCFG_B0_P3_ROUTE_BASE, 0x40010700
 3832              	.set CYDEV_UCFG_B0_P3_ROUTE_SIZE, 0x000000ef
 3833              	.set CYDEV_UCFG_B0_P4_BASE, 0x40010800
 3834              	.set CYDEV_UCFG_B0_P4_SIZE, 0x000001ef
 3835              	.set CYDEV_UCFG_B0_P4_U0_BASE, 0x40010800
 3836              	.set CYDEV_UCFG_B0_P4_U0_SIZE, 0x00000070
 3837              	.set CYREG_B0_P4_U0_PLD_IT0, 0x40010800
 3838              	.set CYREG_B0_P4_U0_PLD_IT1, 0x40010804
 3839              	.set CYREG_B0_P4_U0_PLD_IT2, 0x40010808
 3840              	.set CYREG_B0_P4_U0_PLD_IT3, 0x4001080c
 3841              	.set CYREG_B0_P4_U0_PLD_IT4, 0x40010810
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 163


 3842              	.set CYREG_B0_P4_U0_PLD_IT5, 0x40010814
 3843              	.set CYREG_B0_P4_U0_PLD_IT6, 0x40010818
 3844              	.set CYREG_B0_P4_U0_PLD_IT7, 0x4001081c
 3845              	.set CYREG_B0_P4_U0_PLD_IT8, 0x40010820
 3846              	.set CYREG_B0_P4_U0_PLD_IT9, 0x40010824
 3847              	.set CYREG_B0_P4_U0_PLD_IT10, 0x40010828
 3848              	.set CYREG_B0_P4_U0_PLD_IT11, 0x4001082c
 3849              	.set CYREG_B0_P4_U0_PLD_ORT0, 0x40010830
 3850              	.set CYREG_B0_P4_U0_PLD_ORT1, 0x40010832
 3851              	.set CYREG_B0_P4_U0_PLD_ORT2, 0x40010834
 3852              	.set CYREG_B0_P4_U0_PLD_ORT3, 0x40010836
 3853              	.set CYREG_B0_P4_U0_MC_CFG_CEN_CONST, 0x40010838
 3854              	.set CYREG_B0_P4_U0_MC_CFG_XORFB, 0x4001083a
 3855              	.set CYREG_B0_P4_U0_MC_CFG_SET_RESET, 0x4001083c
 3856              	.set CYREG_B0_P4_U0_MC_CFG_BYPASS, 0x4001083e
 3857              	.set CYREG_B0_P4_U0_CFG0, 0x40010840
 3858              	.set CYREG_B0_P4_U0_CFG1, 0x40010841
 3859              	.set CYREG_B0_P4_U0_CFG2, 0x40010842
 3860              	.set CYREG_B0_P4_U0_CFG3, 0x40010843
 3861              	.set CYREG_B0_P4_U0_CFG4, 0x40010844
 3862              	.set CYREG_B0_P4_U0_CFG5, 0x40010845
 3863              	.set CYREG_B0_P4_U0_CFG6, 0x40010846
 3864              	.set CYREG_B0_P4_U0_CFG7, 0x40010847
 3865              	.set CYREG_B0_P4_U0_CFG8, 0x40010848
 3866              	.set CYREG_B0_P4_U0_CFG9, 0x40010849
 3867              	.set CYREG_B0_P4_U0_CFG10, 0x4001084a
 3868              	.set CYREG_B0_P4_U0_CFG11, 0x4001084b
 3869              	.set CYREG_B0_P4_U0_CFG12, 0x4001084c
 3870              	.set CYREG_B0_P4_U0_CFG13, 0x4001084d
 3871              	.set CYREG_B0_P4_U0_CFG14, 0x4001084e
 3872              	.set CYREG_B0_P4_U0_CFG15, 0x4001084f
 3873              	.set CYREG_B0_P4_U0_CFG16, 0x40010850
 3874              	.set CYREG_B0_P4_U0_CFG17, 0x40010851
 3875              	.set CYREG_B0_P4_U0_CFG18, 0x40010852
 3876              	.set CYREG_B0_P4_U0_CFG19, 0x40010853
 3877              	.set CYREG_B0_P4_U0_CFG20, 0x40010854
 3878              	.set CYREG_B0_P4_U0_CFG21, 0x40010855
 3879              	.set CYREG_B0_P4_U0_CFG22, 0x40010856
 3880              	.set CYREG_B0_P4_U0_CFG23, 0x40010857
 3881              	.set CYREG_B0_P4_U0_CFG24, 0x40010858
 3882              	.set CYREG_B0_P4_U0_CFG25, 0x40010859
 3883              	.set CYREG_B0_P4_U0_CFG26, 0x4001085a
 3884              	.set CYREG_B0_P4_U0_CFG27, 0x4001085b
 3885              	.set CYREG_B0_P4_U0_CFG28, 0x4001085c
 3886              	.set CYREG_B0_P4_U0_CFG29, 0x4001085d
 3887              	.set CYREG_B0_P4_U0_CFG30, 0x4001085e
 3888              	.set CYREG_B0_P4_U0_CFG31, 0x4001085f
 3889              	.set CYREG_B0_P4_U0_DCFG0, 0x40010860
 3890              	.set CYREG_B0_P4_U0_DCFG1, 0x40010862
 3891              	.set CYREG_B0_P4_U0_DCFG2, 0x40010864
 3892              	.set CYREG_B0_P4_U0_DCFG3, 0x40010866
 3893              	.set CYREG_B0_P4_U0_DCFG4, 0x40010868
 3894              	.set CYREG_B0_P4_U0_DCFG5, 0x4001086a
 3895              	.set CYREG_B0_P4_U0_DCFG6, 0x4001086c
 3896              	.set CYREG_B0_P4_U0_DCFG7, 0x4001086e
 3897              	.set CYDEV_UCFG_B0_P4_U1_BASE, 0x40010880
 3898              	.set CYDEV_UCFG_B0_P4_U1_SIZE, 0x00000070
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 164


 3899              	.set CYREG_B0_P4_U1_PLD_IT0, 0x40010880
 3900              	.set CYREG_B0_P4_U1_PLD_IT1, 0x40010884
 3901              	.set CYREG_B0_P4_U1_PLD_IT2, 0x40010888
 3902              	.set CYREG_B0_P4_U1_PLD_IT3, 0x4001088c
 3903              	.set CYREG_B0_P4_U1_PLD_IT4, 0x40010890
 3904              	.set CYREG_B0_P4_U1_PLD_IT5, 0x40010894
 3905              	.set CYREG_B0_P4_U1_PLD_IT6, 0x40010898
 3906              	.set CYREG_B0_P4_U1_PLD_IT7, 0x4001089c
 3907              	.set CYREG_B0_P4_U1_PLD_IT8, 0x400108a0
 3908              	.set CYREG_B0_P4_U1_PLD_IT9, 0x400108a4
 3909              	.set CYREG_B0_P4_U1_PLD_IT10, 0x400108a8
 3910              	.set CYREG_B0_P4_U1_PLD_IT11, 0x400108ac
 3911              	.set CYREG_B0_P4_U1_PLD_ORT0, 0x400108b0
 3912              	.set CYREG_B0_P4_U1_PLD_ORT1, 0x400108b2
 3913              	.set CYREG_B0_P4_U1_PLD_ORT2, 0x400108b4
 3914              	.set CYREG_B0_P4_U1_PLD_ORT3, 0x400108b6
 3915              	.set CYREG_B0_P4_U1_MC_CFG_CEN_CONST, 0x400108b8
 3916              	.set CYREG_B0_P4_U1_MC_CFG_XORFB, 0x400108ba
 3917              	.set CYREG_B0_P4_U1_MC_CFG_SET_RESET, 0x400108bc
 3918              	.set CYREG_B0_P4_U1_MC_CFG_BYPASS, 0x400108be
 3919              	.set CYREG_B0_P4_U1_CFG0, 0x400108c0
 3920              	.set CYREG_B0_P4_U1_CFG1, 0x400108c1
 3921              	.set CYREG_B0_P4_U1_CFG2, 0x400108c2
 3922              	.set CYREG_B0_P4_U1_CFG3, 0x400108c3
 3923              	.set CYREG_B0_P4_U1_CFG4, 0x400108c4
 3924              	.set CYREG_B0_P4_U1_CFG5, 0x400108c5
 3925              	.set CYREG_B0_P4_U1_CFG6, 0x400108c6
 3926              	.set CYREG_B0_P4_U1_CFG7, 0x400108c7
 3927              	.set CYREG_B0_P4_U1_CFG8, 0x400108c8
 3928              	.set CYREG_B0_P4_U1_CFG9, 0x400108c9
 3929              	.set CYREG_B0_P4_U1_CFG10, 0x400108ca
 3930              	.set CYREG_B0_P4_U1_CFG11, 0x400108cb
 3931              	.set CYREG_B0_P4_U1_CFG12, 0x400108cc
 3932              	.set CYREG_B0_P4_U1_CFG13, 0x400108cd
 3933              	.set CYREG_B0_P4_U1_CFG14, 0x400108ce
 3934              	.set CYREG_B0_P4_U1_CFG15, 0x400108cf
 3935              	.set CYREG_B0_P4_U1_CFG16, 0x400108d0
 3936              	.set CYREG_B0_P4_U1_CFG17, 0x400108d1
 3937              	.set CYREG_B0_P4_U1_CFG18, 0x400108d2
 3938              	.set CYREG_B0_P4_U1_CFG19, 0x400108d3
 3939              	.set CYREG_B0_P4_U1_CFG20, 0x400108d4
 3940              	.set CYREG_B0_P4_U1_CFG21, 0x400108d5
 3941              	.set CYREG_B0_P4_U1_CFG22, 0x400108d6
 3942              	.set CYREG_B0_P4_U1_CFG23, 0x400108d7
 3943              	.set CYREG_B0_P4_U1_CFG24, 0x400108d8
 3944              	.set CYREG_B0_P4_U1_CFG25, 0x400108d9
 3945              	.set CYREG_B0_P4_U1_CFG26, 0x400108da
 3946              	.set CYREG_B0_P4_U1_CFG27, 0x400108db
 3947              	.set CYREG_B0_P4_U1_CFG28, 0x400108dc
 3948              	.set CYREG_B0_P4_U1_CFG29, 0x400108dd
 3949              	.set CYREG_B0_P4_U1_CFG30, 0x400108de
 3950              	.set CYREG_B0_P4_U1_CFG31, 0x400108df
 3951              	.set CYREG_B0_P4_U1_DCFG0, 0x400108e0
 3952              	.set CYREG_B0_P4_U1_DCFG1, 0x400108e2
 3953              	.set CYREG_B0_P4_U1_DCFG2, 0x400108e4
 3954              	.set CYREG_B0_P4_U1_DCFG3, 0x400108e6
 3955              	.set CYREG_B0_P4_U1_DCFG4, 0x400108e8
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 165


 3956              	.set CYREG_B0_P4_U1_DCFG5, 0x400108ea
 3957              	.set CYREG_B0_P4_U1_DCFG6, 0x400108ec
 3958              	.set CYREG_B0_P4_U1_DCFG7, 0x400108ee
 3959              	.set CYDEV_UCFG_B0_P4_ROUTE_BASE, 0x40010900
 3960              	.set CYDEV_UCFG_B0_P4_ROUTE_SIZE, 0x000000ef
 3961              	.set CYDEV_UCFG_B0_P5_BASE, 0x40010a00
 3962              	.set CYDEV_UCFG_B0_P5_SIZE, 0x000001ef
 3963              	.set CYDEV_UCFG_B0_P5_U0_BASE, 0x40010a00
 3964              	.set CYDEV_UCFG_B0_P5_U0_SIZE, 0x00000070
 3965              	.set CYREG_B0_P5_U0_PLD_IT0, 0x40010a00
 3966              	.set CYREG_B0_P5_U0_PLD_IT1, 0x40010a04
 3967              	.set CYREG_B0_P5_U0_PLD_IT2, 0x40010a08
 3968              	.set CYREG_B0_P5_U0_PLD_IT3, 0x40010a0c
 3969              	.set CYREG_B0_P5_U0_PLD_IT4, 0x40010a10
 3970              	.set CYREG_B0_P5_U0_PLD_IT5, 0x40010a14
 3971              	.set CYREG_B0_P5_U0_PLD_IT6, 0x40010a18
 3972              	.set CYREG_B0_P5_U0_PLD_IT7, 0x40010a1c
 3973              	.set CYREG_B0_P5_U0_PLD_IT8, 0x40010a20
 3974              	.set CYREG_B0_P5_U0_PLD_IT9, 0x40010a24
 3975              	.set CYREG_B0_P5_U0_PLD_IT10, 0x40010a28
 3976              	.set CYREG_B0_P5_U0_PLD_IT11, 0x40010a2c
 3977              	.set CYREG_B0_P5_U0_PLD_ORT0, 0x40010a30
 3978              	.set CYREG_B0_P5_U0_PLD_ORT1, 0x40010a32
 3979              	.set CYREG_B0_P5_U0_PLD_ORT2, 0x40010a34
 3980              	.set CYREG_B0_P5_U0_PLD_ORT3, 0x40010a36
 3981              	.set CYREG_B0_P5_U0_MC_CFG_CEN_CONST, 0x40010a38
 3982              	.set CYREG_B0_P5_U0_MC_CFG_XORFB, 0x40010a3a
 3983              	.set CYREG_B0_P5_U0_MC_CFG_SET_RESET, 0x40010a3c
 3984              	.set CYREG_B0_P5_U0_MC_CFG_BYPASS, 0x40010a3e
 3985              	.set CYREG_B0_P5_U0_CFG0, 0x40010a40
 3986              	.set CYREG_B0_P5_U0_CFG1, 0x40010a41
 3987              	.set CYREG_B0_P5_U0_CFG2, 0x40010a42
 3988              	.set CYREG_B0_P5_U0_CFG3, 0x40010a43
 3989              	.set CYREG_B0_P5_U0_CFG4, 0x40010a44
 3990              	.set CYREG_B0_P5_U0_CFG5, 0x40010a45
 3991              	.set CYREG_B0_P5_U0_CFG6, 0x40010a46
 3992              	.set CYREG_B0_P5_U0_CFG7, 0x40010a47
 3993              	.set CYREG_B0_P5_U0_CFG8, 0x40010a48
 3994              	.set CYREG_B0_P5_U0_CFG9, 0x40010a49
 3995              	.set CYREG_B0_P5_U0_CFG10, 0x40010a4a
 3996              	.set CYREG_B0_P5_U0_CFG11, 0x40010a4b
 3997              	.set CYREG_B0_P5_U0_CFG12, 0x40010a4c
 3998              	.set CYREG_B0_P5_U0_CFG13, 0x40010a4d
 3999              	.set CYREG_B0_P5_U0_CFG14, 0x40010a4e
 4000              	.set CYREG_B0_P5_U0_CFG15, 0x40010a4f
 4001              	.set CYREG_B0_P5_U0_CFG16, 0x40010a50
 4002              	.set CYREG_B0_P5_U0_CFG17, 0x40010a51
 4003              	.set CYREG_B0_P5_U0_CFG18, 0x40010a52
 4004              	.set CYREG_B0_P5_U0_CFG19, 0x40010a53
 4005              	.set CYREG_B0_P5_U0_CFG20, 0x40010a54
 4006              	.set CYREG_B0_P5_U0_CFG21, 0x40010a55
 4007              	.set CYREG_B0_P5_U0_CFG22, 0x40010a56
 4008              	.set CYREG_B0_P5_U0_CFG23, 0x40010a57
 4009              	.set CYREG_B0_P5_U0_CFG24, 0x40010a58
 4010              	.set CYREG_B0_P5_U0_CFG25, 0x40010a59
 4011              	.set CYREG_B0_P5_U0_CFG26, 0x40010a5a
 4012              	.set CYREG_B0_P5_U0_CFG27, 0x40010a5b
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 166


 4013              	.set CYREG_B0_P5_U0_CFG28, 0x40010a5c
 4014              	.set CYREG_B0_P5_U0_CFG29, 0x40010a5d
 4015              	.set CYREG_B0_P5_U0_CFG30, 0x40010a5e
 4016              	.set CYREG_B0_P5_U0_CFG31, 0x40010a5f
 4017              	.set CYREG_B0_P5_U0_DCFG0, 0x40010a60
 4018              	.set CYREG_B0_P5_U0_DCFG1, 0x40010a62
 4019              	.set CYREG_B0_P5_U0_DCFG2, 0x40010a64
 4020              	.set CYREG_B0_P5_U0_DCFG3, 0x40010a66
 4021              	.set CYREG_B0_P5_U0_DCFG4, 0x40010a68
 4022              	.set CYREG_B0_P5_U0_DCFG5, 0x40010a6a
 4023              	.set CYREG_B0_P5_U0_DCFG6, 0x40010a6c
 4024              	.set CYREG_B0_P5_U0_DCFG7, 0x40010a6e
 4025              	.set CYDEV_UCFG_B0_P5_U1_BASE, 0x40010a80
 4026              	.set CYDEV_UCFG_B0_P5_U1_SIZE, 0x00000070
 4027              	.set CYREG_B0_P5_U1_PLD_IT0, 0x40010a80
 4028              	.set CYREG_B0_P5_U1_PLD_IT1, 0x40010a84
 4029              	.set CYREG_B0_P5_U1_PLD_IT2, 0x40010a88
 4030              	.set CYREG_B0_P5_U1_PLD_IT3, 0x40010a8c
 4031              	.set CYREG_B0_P5_U1_PLD_IT4, 0x40010a90
 4032              	.set CYREG_B0_P5_U1_PLD_IT5, 0x40010a94
 4033              	.set CYREG_B0_P5_U1_PLD_IT6, 0x40010a98
 4034              	.set CYREG_B0_P5_U1_PLD_IT7, 0x40010a9c
 4035              	.set CYREG_B0_P5_U1_PLD_IT8, 0x40010aa0
 4036              	.set CYREG_B0_P5_U1_PLD_IT9, 0x40010aa4
 4037              	.set CYREG_B0_P5_U1_PLD_IT10, 0x40010aa8
 4038              	.set CYREG_B0_P5_U1_PLD_IT11, 0x40010aac
 4039              	.set CYREG_B0_P5_U1_PLD_ORT0, 0x40010ab0
 4040              	.set CYREG_B0_P5_U1_PLD_ORT1, 0x40010ab2
 4041              	.set CYREG_B0_P5_U1_PLD_ORT2, 0x40010ab4
 4042              	.set CYREG_B0_P5_U1_PLD_ORT3, 0x40010ab6
 4043              	.set CYREG_B0_P5_U1_MC_CFG_CEN_CONST, 0x40010ab8
 4044              	.set CYREG_B0_P5_U1_MC_CFG_XORFB, 0x40010aba
 4045              	.set CYREG_B0_P5_U1_MC_CFG_SET_RESET, 0x40010abc
 4046              	.set CYREG_B0_P5_U1_MC_CFG_BYPASS, 0x40010abe
 4047              	.set CYREG_B0_P5_U1_CFG0, 0x40010ac0
 4048              	.set CYREG_B0_P5_U1_CFG1, 0x40010ac1
 4049              	.set CYREG_B0_P5_U1_CFG2, 0x40010ac2
 4050              	.set CYREG_B0_P5_U1_CFG3, 0x40010ac3
 4051              	.set CYREG_B0_P5_U1_CFG4, 0x40010ac4
 4052              	.set CYREG_B0_P5_U1_CFG5, 0x40010ac5
 4053              	.set CYREG_B0_P5_U1_CFG6, 0x40010ac6
 4054              	.set CYREG_B0_P5_U1_CFG7, 0x40010ac7
 4055              	.set CYREG_B0_P5_U1_CFG8, 0x40010ac8
 4056              	.set CYREG_B0_P5_U1_CFG9, 0x40010ac9
 4057              	.set CYREG_B0_P5_U1_CFG10, 0x40010aca
 4058              	.set CYREG_B0_P5_U1_CFG11, 0x40010acb
 4059              	.set CYREG_B0_P5_U1_CFG12, 0x40010acc
 4060              	.set CYREG_B0_P5_U1_CFG13, 0x40010acd
 4061              	.set CYREG_B0_P5_U1_CFG14, 0x40010ace
 4062              	.set CYREG_B0_P5_U1_CFG15, 0x40010acf
 4063              	.set CYREG_B0_P5_U1_CFG16, 0x40010ad0
 4064              	.set CYREG_B0_P5_U1_CFG17, 0x40010ad1
 4065              	.set CYREG_B0_P5_U1_CFG18, 0x40010ad2
 4066              	.set CYREG_B0_P5_U1_CFG19, 0x40010ad3
 4067              	.set CYREG_B0_P5_U1_CFG20, 0x40010ad4
 4068              	.set CYREG_B0_P5_U1_CFG21, 0x40010ad5
 4069              	.set CYREG_B0_P5_U1_CFG22, 0x40010ad6
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 167


 4070              	.set CYREG_B0_P5_U1_CFG23, 0x40010ad7
 4071              	.set CYREG_B0_P5_U1_CFG24, 0x40010ad8
 4072              	.set CYREG_B0_P5_U1_CFG25, 0x40010ad9
 4073              	.set CYREG_B0_P5_U1_CFG26, 0x40010ada
 4074              	.set CYREG_B0_P5_U1_CFG27, 0x40010adb
 4075              	.set CYREG_B0_P5_U1_CFG28, 0x40010adc
 4076              	.set CYREG_B0_P5_U1_CFG29, 0x40010add
 4077              	.set CYREG_B0_P5_U1_CFG30, 0x40010ade
 4078              	.set CYREG_B0_P5_U1_CFG31, 0x40010adf
 4079              	.set CYREG_B0_P5_U1_DCFG0, 0x40010ae0
 4080              	.set CYREG_B0_P5_U1_DCFG1, 0x40010ae2
 4081              	.set CYREG_B0_P5_U1_DCFG2, 0x40010ae4
 4082              	.set CYREG_B0_P5_U1_DCFG3, 0x40010ae6
 4083              	.set CYREG_B0_P5_U1_DCFG4, 0x40010ae8
 4084              	.set CYREG_B0_P5_U1_DCFG5, 0x40010aea
 4085              	.set CYREG_B0_P5_U1_DCFG6, 0x40010aec
 4086              	.set CYREG_B0_P5_U1_DCFG7, 0x40010aee
 4087              	.set CYDEV_UCFG_B0_P5_ROUTE_BASE, 0x40010b00
 4088              	.set CYDEV_UCFG_B0_P5_ROUTE_SIZE, 0x000000ef
 4089              	.set CYDEV_UCFG_B0_P6_BASE, 0x40010c00
 4090              	.set CYDEV_UCFG_B0_P6_SIZE, 0x000001ef
 4091              	.set CYDEV_UCFG_B0_P6_U0_BASE, 0x40010c00
 4092              	.set CYDEV_UCFG_B0_P6_U0_SIZE, 0x00000070
 4093              	.set CYREG_B0_P6_U0_PLD_IT0, 0x40010c00
 4094              	.set CYREG_B0_P6_U0_PLD_IT1, 0x40010c04
 4095              	.set CYREG_B0_P6_U0_PLD_IT2, 0x40010c08
 4096              	.set CYREG_B0_P6_U0_PLD_IT3, 0x40010c0c
 4097              	.set CYREG_B0_P6_U0_PLD_IT4, 0x40010c10
 4098              	.set CYREG_B0_P6_U0_PLD_IT5, 0x40010c14
 4099              	.set CYREG_B0_P6_U0_PLD_IT6, 0x40010c18
 4100              	.set CYREG_B0_P6_U0_PLD_IT7, 0x40010c1c
 4101              	.set CYREG_B0_P6_U0_PLD_IT8, 0x40010c20
 4102              	.set CYREG_B0_P6_U0_PLD_IT9, 0x40010c24
 4103              	.set CYREG_B0_P6_U0_PLD_IT10, 0x40010c28
 4104              	.set CYREG_B0_P6_U0_PLD_IT11, 0x40010c2c
 4105              	.set CYREG_B0_P6_U0_PLD_ORT0, 0x40010c30
 4106              	.set CYREG_B0_P6_U0_PLD_ORT1, 0x40010c32
 4107              	.set CYREG_B0_P6_U0_PLD_ORT2, 0x40010c34
 4108              	.set CYREG_B0_P6_U0_PLD_ORT3, 0x40010c36
 4109              	.set CYREG_B0_P6_U0_MC_CFG_CEN_CONST, 0x40010c38
 4110              	.set CYREG_B0_P6_U0_MC_CFG_XORFB, 0x40010c3a
 4111              	.set CYREG_B0_P6_U0_MC_CFG_SET_RESET, 0x40010c3c
 4112              	.set CYREG_B0_P6_U0_MC_CFG_BYPASS, 0x40010c3e
 4113              	.set CYREG_B0_P6_U0_CFG0, 0x40010c40
 4114              	.set CYREG_B0_P6_U0_CFG1, 0x40010c41
 4115              	.set CYREG_B0_P6_U0_CFG2, 0x40010c42
 4116              	.set CYREG_B0_P6_U0_CFG3, 0x40010c43
 4117              	.set CYREG_B0_P6_U0_CFG4, 0x40010c44
 4118              	.set CYREG_B0_P6_U0_CFG5, 0x40010c45
 4119              	.set CYREG_B0_P6_U0_CFG6, 0x40010c46
 4120              	.set CYREG_B0_P6_U0_CFG7, 0x40010c47
 4121              	.set CYREG_B0_P6_U0_CFG8, 0x40010c48
 4122              	.set CYREG_B0_P6_U0_CFG9, 0x40010c49
 4123              	.set CYREG_B0_P6_U0_CFG10, 0x40010c4a
 4124              	.set CYREG_B0_P6_U0_CFG11, 0x40010c4b
 4125              	.set CYREG_B0_P6_U0_CFG12, 0x40010c4c
 4126              	.set CYREG_B0_P6_U0_CFG13, 0x40010c4d
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 168


 4127              	.set CYREG_B0_P6_U0_CFG14, 0x40010c4e
 4128              	.set CYREG_B0_P6_U0_CFG15, 0x40010c4f
 4129              	.set CYREG_B0_P6_U0_CFG16, 0x40010c50
 4130              	.set CYREG_B0_P6_U0_CFG17, 0x40010c51
 4131              	.set CYREG_B0_P6_U0_CFG18, 0x40010c52
 4132              	.set CYREG_B0_P6_U0_CFG19, 0x40010c53
 4133              	.set CYREG_B0_P6_U0_CFG20, 0x40010c54
 4134              	.set CYREG_B0_P6_U0_CFG21, 0x40010c55
 4135              	.set CYREG_B0_P6_U0_CFG22, 0x40010c56
 4136              	.set CYREG_B0_P6_U0_CFG23, 0x40010c57
 4137              	.set CYREG_B0_P6_U0_CFG24, 0x40010c58
 4138              	.set CYREG_B0_P6_U0_CFG25, 0x40010c59
 4139              	.set CYREG_B0_P6_U0_CFG26, 0x40010c5a
 4140              	.set CYREG_B0_P6_U0_CFG27, 0x40010c5b
 4141              	.set CYREG_B0_P6_U0_CFG28, 0x40010c5c
 4142              	.set CYREG_B0_P6_U0_CFG29, 0x40010c5d
 4143              	.set CYREG_B0_P6_U0_CFG30, 0x40010c5e
 4144              	.set CYREG_B0_P6_U0_CFG31, 0x40010c5f
 4145              	.set CYREG_B0_P6_U0_DCFG0, 0x40010c60
 4146              	.set CYREG_B0_P6_U0_DCFG1, 0x40010c62
 4147              	.set CYREG_B0_P6_U0_DCFG2, 0x40010c64
 4148              	.set CYREG_B0_P6_U0_DCFG3, 0x40010c66
 4149              	.set CYREG_B0_P6_U0_DCFG4, 0x40010c68
 4150              	.set CYREG_B0_P6_U0_DCFG5, 0x40010c6a
 4151              	.set CYREG_B0_P6_U0_DCFG6, 0x40010c6c
 4152              	.set CYREG_B0_P6_U0_DCFG7, 0x40010c6e
 4153              	.set CYDEV_UCFG_B0_P6_U1_BASE, 0x40010c80
 4154              	.set CYDEV_UCFG_B0_P6_U1_SIZE, 0x00000070
 4155              	.set CYREG_B0_P6_U1_PLD_IT0, 0x40010c80
 4156              	.set CYREG_B0_P6_U1_PLD_IT1, 0x40010c84
 4157              	.set CYREG_B0_P6_U1_PLD_IT2, 0x40010c88
 4158              	.set CYREG_B0_P6_U1_PLD_IT3, 0x40010c8c
 4159              	.set CYREG_B0_P6_U1_PLD_IT4, 0x40010c90
 4160              	.set CYREG_B0_P6_U1_PLD_IT5, 0x40010c94
 4161              	.set CYREG_B0_P6_U1_PLD_IT6, 0x40010c98
 4162              	.set CYREG_B0_P6_U1_PLD_IT7, 0x40010c9c
 4163              	.set CYREG_B0_P6_U1_PLD_IT8, 0x40010ca0
 4164              	.set CYREG_B0_P6_U1_PLD_IT9, 0x40010ca4
 4165              	.set CYREG_B0_P6_U1_PLD_IT10, 0x40010ca8
 4166              	.set CYREG_B0_P6_U1_PLD_IT11, 0x40010cac
 4167              	.set CYREG_B0_P6_U1_PLD_ORT0, 0x40010cb0
 4168              	.set CYREG_B0_P6_U1_PLD_ORT1, 0x40010cb2
 4169              	.set CYREG_B0_P6_U1_PLD_ORT2, 0x40010cb4
 4170              	.set CYREG_B0_P6_U1_PLD_ORT3, 0x40010cb6
 4171              	.set CYREG_B0_P6_U1_MC_CFG_CEN_CONST, 0x40010cb8
 4172              	.set CYREG_B0_P6_U1_MC_CFG_XORFB, 0x40010cba
 4173              	.set CYREG_B0_P6_U1_MC_CFG_SET_RESET, 0x40010cbc
 4174              	.set CYREG_B0_P6_U1_MC_CFG_BYPASS, 0x40010cbe
 4175              	.set CYREG_B0_P6_U1_CFG0, 0x40010cc0
 4176              	.set CYREG_B0_P6_U1_CFG1, 0x40010cc1
 4177              	.set CYREG_B0_P6_U1_CFG2, 0x40010cc2
 4178              	.set CYREG_B0_P6_U1_CFG3, 0x40010cc3
 4179              	.set CYREG_B0_P6_U1_CFG4, 0x40010cc4
 4180              	.set CYREG_B0_P6_U1_CFG5, 0x40010cc5
 4181              	.set CYREG_B0_P6_U1_CFG6, 0x40010cc6
 4182              	.set CYREG_B0_P6_U1_CFG7, 0x40010cc7
 4183              	.set CYREG_B0_P6_U1_CFG8, 0x40010cc8
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 169


 4184              	.set CYREG_B0_P6_U1_CFG9, 0x40010cc9
 4185              	.set CYREG_B0_P6_U1_CFG10, 0x40010cca
 4186              	.set CYREG_B0_P6_U1_CFG11, 0x40010ccb
 4187              	.set CYREG_B0_P6_U1_CFG12, 0x40010ccc
 4188              	.set CYREG_B0_P6_U1_CFG13, 0x40010ccd
 4189              	.set CYREG_B0_P6_U1_CFG14, 0x40010cce
 4190              	.set CYREG_B0_P6_U1_CFG15, 0x40010ccf
 4191              	.set CYREG_B0_P6_U1_CFG16, 0x40010cd0
 4192              	.set CYREG_B0_P6_U1_CFG17, 0x40010cd1
 4193              	.set CYREG_B0_P6_U1_CFG18, 0x40010cd2
 4194              	.set CYREG_B0_P6_U1_CFG19, 0x40010cd3
 4195              	.set CYREG_B0_P6_U1_CFG20, 0x40010cd4
 4196              	.set CYREG_B0_P6_U1_CFG21, 0x40010cd5
 4197              	.set CYREG_B0_P6_U1_CFG22, 0x40010cd6
 4198              	.set CYREG_B0_P6_U1_CFG23, 0x40010cd7
 4199              	.set CYREG_B0_P6_U1_CFG24, 0x40010cd8
 4200              	.set CYREG_B0_P6_U1_CFG25, 0x40010cd9
 4201              	.set CYREG_B0_P6_U1_CFG26, 0x40010cda
 4202              	.set CYREG_B0_P6_U1_CFG27, 0x40010cdb
 4203              	.set CYREG_B0_P6_U1_CFG28, 0x40010cdc
 4204              	.set CYREG_B0_P6_U1_CFG29, 0x40010cdd
 4205              	.set CYREG_B0_P6_U1_CFG30, 0x40010cde
 4206              	.set CYREG_B0_P6_U1_CFG31, 0x40010cdf
 4207              	.set CYREG_B0_P6_U1_DCFG0, 0x40010ce0
 4208              	.set CYREG_B0_P6_U1_DCFG1, 0x40010ce2
 4209              	.set CYREG_B0_P6_U1_DCFG2, 0x40010ce4
 4210              	.set CYREG_B0_P6_U1_DCFG3, 0x40010ce6
 4211              	.set CYREG_B0_P6_U1_DCFG4, 0x40010ce8
 4212              	.set CYREG_B0_P6_U1_DCFG5, 0x40010cea
 4213              	.set CYREG_B0_P6_U1_DCFG6, 0x40010cec
 4214              	.set CYREG_B0_P6_U1_DCFG7, 0x40010cee
 4215              	.set CYDEV_UCFG_B0_P6_ROUTE_BASE, 0x40010d00
 4216              	.set CYDEV_UCFG_B0_P6_ROUTE_SIZE, 0x000000ef
 4217              	.set CYDEV_UCFG_B0_P7_BASE, 0x40010e00
 4218              	.set CYDEV_UCFG_B0_P7_SIZE, 0x000001ef
 4219              	.set CYDEV_UCFG_B0_P7_U0_BASE, 0x40010e00
 4220              	.set CYDEV_UCFG_B0_P7_U0_SIZE, 0x00000070
 4221              	.set CYREG_B0_P7_U0_PLD_IT0, 0x40010e00
 4222              	.set CYREG_B0_P7_U0_PLD_IT1, 0x40010e04
 4223              	.set CYREG_B0_P7_U0_PLD_IT2, 0x40010e08
 4224              	.set CYREG_B0_P7_U0_PLD_IT3, 0x40010e0c
 4225              	.set CYREG_B0_P7_U0_PLD_IT4, 0x40010e10
 4226              	.set CYREG_B0_P7_U0_PLD_IT5, 0x40010e14
 4227              	.set CYREG_B0_P7_U0_PLD_IT6, 0x40010e18
 4228              	.set CYREG_B0_P7_U0_PLD_IT7, 0x40010e1c
 4229              	.set CYREG_B0_P7_U0_PLD_IT8, 0x40010e20
 4230              	.set CYREG_B0_P7_U0_PLD_IT9, 0x40010e24
 4231              	.set CYREG_B0_P7_U0_PLD_IT10, 0x40010e28
 4232              	.set CYREG_B0_P7_U0_PLD_IT11, 0x40010e2c
 4233              	.set CYREG_B0_P7_U0_PLD_ORT0, 0x40010e30
 4234              	.set CYREG_B0_P7_U0_PLD_ORT1, 0x40010e32
 4235              	.set CYREG_B0_P7_U0_PLD_ORT2, 0x40010e34
 4236              	.set CYREG_B0_P7_U0_PLD_ORT3, 0x40010e36
 4237              	.set CYREG_B0_P7_U0_MC_CFG_CEN_CONST, 0x40010e38
 4238              	.set CYREG_B0_P7_U0_MC_CFG_XORFB, 0x40010e3a
 4239              	.set CYREG_B0_P7_U0_MC_CFG_SET_RESET, 0x40010e3c
 4240              	.set CYREG_B0_P7_U0_MC_CFG_BYPASS, 0x40010e3e
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 170


 4241              	.set CYREG_B0_P7_U0_CFG0, 0x40010e40
 4242              	.set CYREG_B0_P7_U0_CFG1, 0x40010e41
 4243              	.set CYREG_B0_P7_U0_CFG2, 0x40010e42
 4244              	.set CYREG_B0_P7_U0_CFG3, 0x40010e43
 4245              	.set CYREG_B0_P7_U0_CFG4, 0x40010e44
 4246              	.set CYREG_B0_P7_U0_CFG5, 0x40010e45
 4247              	.set CYREG_B0_P7_U0_CFG6, 0x40010e46
 4248              	.set CYREG_B0_P7_U0_CFG7, 0x40010e47
 4249              	.set CYREG_B0_P7_U0_CFG8, 0x40010e48
 4250              	.set CYREG_B0_P7_U0_CFG9, 0x40010e49
 4251              	.set CYREG_B0_P7_U0_CFG10, 0x40010e4a
 4252              	.set CYREG_B0_P7_U0_CFG11, 0x40010e4b
 4253              	.set CYREG_B0_P7_U0_CFG12, 0x40010e4c
 4254              	.set CYREG_B0_P7_U0_CFG13, 0x40010e4d
 4255              	.set CYREG_B0_P7_U0_CFG14, 0x40010e4e
 4256              	.set CYREG_B0_P7_U0_CFG15, 0x40010e4f
 4257              	.set CYREG_B0_P7_U0_CFG16, 0x40010e50
 4258              	.set CYREG_B0_P7_U0_CFG17, 0x40010e51
 4259              	.set CYREG_B0_P7_U0_CFG18, 0x40010e52
 4260              	.set CYREG_B0_P7_U0_CFG19, 0x40010e53
 4261              	.set CYREG_B0_P7_U0_CFG20, 0x40010e54
 4262              	.set CYREG_B0_P7_U0_CFG21, 0x40010e55
 4263              	.set CYREG_B0_P7_U0_CFG22, 0x40010e56
 4264              	.set CYREG_B0_P7_U0_CFG23, 0x40010e57
 4265              	.set CYREG_B0_P7_U0_CFG24, 0x40010e58
 4266              	.set CYREG_B0_P7_U0_CFG25, 0x40010e59
 4267              	.set CYREG_B0_P7_U0_CFG26, 0x40010e5a
 4268              	.set CYREG_B0_P7_U0_CFG27, 0x40010e5b
 4269              	.set CYREG_B0_P7_U0_CFG28, 0x40010e5c
 4270              	.set CYREG_B0_P7_U0_CFG29, 0x40010e5d
 4271              	.set CYREG_B0_P7_U0_CFG30, 0x40010e5e
 4272              	.set CYREG_B0_P7_U0_CFG31, 0x40010e5f
 4273              	.set CYREG_B0_P7_U0_DCFG0, 0x40010e60
 4274              	.set CYREG_B0_P7_U0_DCFG1, 0x40010e62
 4275              	.set CYREG_B0_P7_U0_DCFG2, 0x40010e64
 4276              	.set CYREG_B0_P7_U0_DCFG3, 0x40010e66
 4277              	.set CYREG_B0_P7_U0_DCFG4, 0x40010e68
 4278              	.set CYREG_B0_P7_U0_DCFG5, 0x40010e6a
 4279              	.set CYREG_B0_P7_U0_DCFG6, 0x40010e6c
 4280              	.set CYREG_B0_P7_U0_DCFG7, 0x40010e6e
 4281              	.set CYDEV_UCFG_B0_P7_U1_BASE, 0x40010e80
 4282              	.set CYDEV_UCFG_B0_P7_U1_SIZE, 0x00000070
 4283              	.set CYREG_B0_P7_U1_PLD_IT0, 0x40010e80
 4284              	.set CYREG_B0_P7_U1_PLD_IT1, 0x40010e84
 4285              	.set CYREG_B0_P7_U1_PLD_IT2, 0x40010e88
 4286              	.set CYREG_B0_P7_U1_PLD_IT3, 0x40010e8c
 4287              	.set CYREG_B0_P7_U1_PLD_IT4, 0x40010e90
 4288              	.set CYREG_B0_P7_U1_PLD_IT5, 0x40010e94
 4289              	.set CYREG_B0_P7_U1_PLD_IT6, 0x40010e98
 4290              	.set CYREG_B0_P7_U1_PLD_IT7, 0x40010e9c
 4291              	.set CYREG_B0_P7_U1_PLD_IT8, 0x40010ea0
 4292              	.set CYREG_B0_P7_U1_PLD_IT9, 0x40010ea4
 4293              	.set CYREG_B0_P7_U1_PLD_IT10, 0x40010ea8
 4294              	.set CYREG_B0_P7_U1_PLD_IT11, 0x40010eac
 4295              	.set CYREG_B0_P7_U1_PLD_ORT0, 0x40010eb0
 4296              	.set CYREG_B0_P7_U1_PLD_ORT1, 0x40010eb2
 4297              	.set CYREG_B0_P7_U1_PLD_ORT2, 0x40010eb4
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 171


 4298              	.set CYREG_B0_P7_U1_PLD_ORT3, 0x40010eb6
 4299              	.set CYREG_B0_P7_U1_MC_CFG_CEN_CONST, 0x40010eb8
 4300              	.set CYREG_B0_P7_U1_MC_CFG_XORFB, 0x40010eba
 4301              	.set CYREG_B0_P7_U1_MC_CFG_SET_RESET, 0x40010ebc
 4302              	.set CYREG_B0_P7_U1_MC_CFG_BYPASS, 0x40010ebe
 4303              	.set CYREG_B0_P7_U1_CFG0, 0x40010ec0
 4304              	.set CYREG_B0_P7_U1_CFG1, 0x40010ec1
 4305              	.set CYREG_B0_P7_U1_CFG2, 0x40010ec2
 4306              	.set CYREG_B0_P7_U1_CFG3, 0x40010ec3
 4307              	.set CYREG_B0_P7_U1_CFG4, 0x40010ec4
 4308              	.set CYREG_B0_P7_U1_CFG5, 0x40010ec5
 4309              	.set CYREG_B0_P7_U1_CFG6, 0x40010ec6
 4310              	.set CYREG_B0_P7_U1_CFG7, 0x40010ec7
 4311              	.set CYREG_B0_P7_U1_CFG8, 0x40010ec8
 4312              	.set CYREG_B0_P7_U1_CFG9, 0x40010ec9
 4313              	.set CYREG_B0_P7_U1_CFG10, 0x40010eca
 4314              	.set CYREG_B0_P7_U1_CFG11, 0x40010ecb
 4315              	.set CYREG_B0_P7_U1_CFG12, 0x40010ecc
 4316              	.set CYREG_B0_P7_U1_CFG13, 0x40010ecd
 4317              	.set CYREG_B0_P7_U1_CFG14, 0x40010ece
 4318              	.set CYREG_B0_P7_U1_CFG15, 0x40010ecf
 4319              	.set CYREG_B0_P7_U1_CFG16, 0x40010ed0
 4320              	.set CYREG_B0_P7_U1_CFG17, 0x40010ed1
 4321              	.set CYREG_B0_P7_U1_CFG18, 0x40010ed2
 4322              	.set CYREG_B0_P7_U1_CFG19, 0x40010ed3
 4323              	.set CYREG_B0_P7_U1_CFG20, 0x40010ed4
 4324              	.set CYREG_B0_P7_U1_CFG21, 0x40010ed5
 4325              	.set CYREG_B0_P7_U1_CFG22, 0x40010ed6
 4326              	.set CYREG_B0_P7_U1_CFG23, 0x40010ed7
 4327              	.set CYREG_B0_P7_U1_CFG24, 0x40010ed8
 4328              	.set CYREG_B0_P7_U1_CFG25, 0x40010ed9
 4329              	.set CYREG_B0_P7_U1_CFG26, 0x40010eda
 4330              	.set CYREG_B0_P7_U1_CFG27, 0x40010edb
 4331              	.set CYREG_B0_P7_U1_CFG28, 0x40010edc
 4332              	.set CYREG_B0_P7_U1_CFG29, 0x40010edd
 4333              	.set CYREG_B0_P7_U1_CFG30, 0x40010ede
 4334              	.set CYREG_B0_P7_U1_CFG31, 0x40010edf
 4335              	.set CYREG_B0_P7_U1_DCFG0, 0x40010ee0
 4336              	.set CYREG_B0_P7_U1_DCFG1, 0x40010ee2
 4337              	.set CYREG_B0_P7_U1_DCFG2, 0x40010ee4
 4338              	.set CYREG_B0_P7_U1_DCFG3, 0x40010ee6
 4339              	.set CYREG_B0_P7_U1_DCFG4, 0x40010ee8
 4340              	.set CYREG_B0_P7_U1_DCFG5, 0x40010eea
 4341              	.set CYREG_B0_P7_U1_DCFG6, 0x40010eec
 4342              	.set CYREG_B0_P7_U1_DCFG7, 0x40010eee
 4343              	.set CYDEV_UCFG_B0_P7_ROUTE_BASE, 0x40010f00
 4344              	.set CYDEV_UCFG_B0_P7_ROUTE_SIZE, 0x000000ef
 4345              	.set CYDEV_UCFG_B1_BASE, 0x40011000
 4346              	.set CYDEV_UCFG_B1_SIZE, 0x00000fef
 4347              	.set CYDEV_UCFG_B1_P2_BASE, 0x40011400
 4348              	.set CYDEV_UCFG_B1_P2_SIZE, 0x000001ef
 4349              	.set CYDEV_UCFG_B1_P2_U0_BASE, 0x40011400
 4350              	.set CYDEV_UCFG_B1_P2_U0_SIZE, 0x00000070
 4351              	.set CYREG_B1_P2_U0_PLD_IT0, 0x40011400
 4352              	.set CYREG_B1_P2_U0_PLD_IT1, 0x40011404
 4353              	.set CYREG_B1_P2_U0_PLD_IT2, 0x40011408
 4354              	.set CYREG_B1_P2_U0_PLD_IT3, 0x4001140c
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 172


 4355              	.set CYREG_B1_P2_U0_PLD_IT4, 0x40011410
 4356              	.set CYREG_B1_P2_U0_PLD_IT5, 0x40011414
 4357              	.set CYREG_B1_P2_U0_PLD_IT6, 0x40011418
 4358              	.set CYREG_B1_P2_U0_PLD_IT7, 0x4001141c
 4359              	.set CYREG_B1_P2_U0_PLD_IT8, 0x40011420
 4360              	.set CYREG_B1_P2_U0_PLD_IT9, 0x40011424
 4361              	.set CYREG_B1_P2_U0_PLD_IT10, 0x40011428
 4362              	.set CYREG_B1_P2_U0_PLD_IT11, 0x4001142c
 4363              	.set CYREG_B1_P2_U0_PLD_ORT0, 0x40011430
 4364              	.set CYREG_B1_P2_U0_PLD_ORT1, 0x40011432
 4365              	.set CYREG_B1_P2_U0_PLD_ORT2, 0x40011434
 4366              	.set CYREG_B1_P2_U0_PLD_ORT3, 0x40011436
 4367              	.set CYREG_B1_P2_U0_MC_CFG_CEN_CONST, 0x40011438
 4368              	.set CYREG_B1_P2_U0_MC_CFG_XORFB, 0x4001143a
 4369              	.set CYREG_B1_P2_U0_MC_CFG_SET_RESET, 0x4001143c
 4370              	.set CYREG_B1_P2_U0_MC_CFG_BYPASS, 0x4001143e
 4371              	.set CYREG_B1_P2_U0_CFG0, 0x40011440
 4372              	.set CYREG_B1_P2_U0_CFG1, 0x40011441
 4373              	.set CYREG_B1_P2_U0_CFG2, 0x40011442
 4374              	.set CYREG_B1_P2_U0_CFG3, 0x40011443
 4375              	.set CYREG_B1_P2_U0_CFG4, 0x40011444
 4376              	.set CYREG_B1_P2_U0_CFG5, 0x40011445
 4377              	.set CYREG_B1_P2_U0_CFG6, 0x40011446
 4378              	.set CYREG_B1_P2_U0_CFG7, 0x40011447
 4379              	.set CYREG_B1_P2_U0_CFG8, 0x40011448
 4380              	.set CYREG_B1_P2_U0_CFG9, 0x40011449
 4381              	.set CYREG_B1_P2_U0_CFG10, 0x4001144a
 4382              	.set CYREG_B1_P2_U0_CFG11, 0x4001144b
 4383              	.set CYREG_B1_P2_U0_CFG12, 0x4001144c
 4384              	.set CYREG_B1_P2_U0_CFG13, 0x4001144d
 4385              	.set CYREG_B1_P2_U0_CFG14, 0x4001144e
 4386              	.set CYREG_B1_P2_U0_CFG15, 0x4001144f
 4387              	.set CYREG_B1_P2_U0_CFG16, 0x40011450
 4388              	.set CYREG_B1_P2_U0_CFG17, 0x40011451
 4389              	.set CYREG_B1_P2_U0_CFG18, 0x40011452
 4390              	.set CYREG_B1_P2_U0_CFG19, 0x40011453
 4391              	.set CYREG_B1_P2_U0_CFG20, 0x40011454
 4392              	.set CYREG_B1_P2_U0_CFG21, 0x40011455
 4393              	.set CYREG_B1_P2_U0_CFG22, 0x40011456
 4394              	.set CYREG_B1_P2_U0_CFG23, 0x40011457
 4395              	.set CYREG_B1_P2_U0_CFG24, 0x40011458
 4396              	.set CYREG_B1_P2_U0_CFG25, 0x40011459
 4397              	.set CYREG_B1_P2_U0_CFG26, 0x4001145a
 4398              	.set CYREG_B1_P2_U0_CFG27, 0x4001145b
 4399              	.set CYREG_B1_P2_U0_CFG28, 0x4001145c
 4400              	.set CYREG_B1_P2_U0_CFG29, 0x4001145d
 4401              	.set CYREG_B1_P2_U0_CFG30, 0x4001145e
 4402              	.set CYREG_B1_P2_U0_CFG31, 0x4001145f
 4403              	.set CYREG_B1_P2_U0_DCFG0, 0x40011460
 4404              	.set CYREG_B1_P2_U0_DCFG1, 0x40011462
 4405              	.set CYREG_B1_P2_U0_DCFG2, 0x40011464
 4406              	.set CYREG_B1_P2_U0_DCFG3, 0x40011466
 4407              	.set CYREG_B1_P2_U0_DCFG4, 0x40011468
 4408              	.set CYREG_B1_P2_U0_DCFG5, 0x4001146a
 4409              	.set CYREG_B1_P2_U0_DCFG6, 0x4001146c
 4410              	.set CYREG_B1_P2_U0_DCFG7, 0x4001146e
 4411              	.set CYDEV_UCFG_B1_P2_U1_BASE, 0x40011480
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 173


 4412              	.set CYDEV_UCFG_B1_P2_U1_SIZE, 0x00000070
 4413              	.set CYREG_B1_P2_U1_PLD_IT0, 0x40011480
 4414              	.set CYREG_B1_P2_U1_PLD_IT1, 0x40011484
 4415              	.set CYREG_B1_P2_U1_PLD_IT2, 0x40011488
 4416              	.set CYREG_B1_P2_U1_PLD_IT3, 0x4001148c
 4417              	.set CYREG_B1_P2_U1_PLD_IT4, 0x40011490
 4418              	.set CYREG_B1_P2_U1_PLD_IT5, 0x40011494
 4419              	.set CYREG_B1_P2_U1_PLD_IT6, 0x40011498
 4420              	.set CYREG_B1_P2_U1_PLD_IT7, 0x4001149c
 4421              	.set CYREG_B1_P2_U1_PLD_IT8, 0x400114a0
 4422              	.set CYREG_B1_P2_U1_PLD_IT9, 0x400114a4
 4423              	.set CYREG_B1_P2_U1_PLD_IT10, 0x400114a8
 4424              	.set CYREG_B1_P2_U1_PLD_IT11, 0x400114ac
 4425              	.set CYREG_B1_P2_U1_PLD_ORT0, 0x400114b0
 4426              	.set CYREG_B1_P2_U1_PLD_ORT1, 0x400114b2
 4427              	.set CYREG_B1_P2_U1_PLD_ORT2, 0x400114b4
 4428              	.set CYREG_B1_P2_U1_PLD_ORT3, 0x400114b6
 4429              	.set CYREG_B1_P2_U1_MC_CFG_CEN_CONST, 0x400114b8
 4430              	.set CYREG_B1_P2_U1_MC_CFG_XORFB, 0x400114ba
 4431              	.set CYREG_B1_P2_U1_MC_CFG_SET_RESET, 0x400114bc
 4432              	.set CYREG_B1_P2_U1_MC_CFG_BYPASS, 0x400114be
 4433              	.set CYREG_B1_P2_U1_CFG0, 0x400114c0
 4434              	.set CYREG_B1_P2_U1_CFG1, 0x400114c1
 4435              	.set CYREG_B1_P2_U1_CFG2, 0x400114c2
 4436              	.set CYREG_B1_P2_U1_CFG3, 0x400114c3
 4437              	.set CYREG_B1_P2_U1_CFG4, 0x400114c4
 4438              	.set CYREG_B1_P2_U1_CFG5, 0x400114c5
 4439              	.set CYREG_B1_P2_U1_CFG6, 0x400114c6
 4440              	.set CYREG_B1_P2_U1_CFG7, 0x400114c7
 4441              	.set CYREG_B1_P2_U1_CFG8, 0x400114c8
 4442              	.set CYREG_B1_P2_U1_CFG9, 0x400114c9
 4443              	.set CYREG_B1_P2_U1_CFG10, 0x400114ca
 4444              	.set CYREG_B1_P2_U1_CFG11, 0x400114cb
 4445              	.set CYREG_B1_P2_U1_CFG12, 0x400114cc
 4446              	.set CYREG_B1_P2_U1_CFG13, 0x400114cd
 4447              	.set CYREG_B1_P2_U1_CFG14, 0x400114ce
 4448              	.set CYREG_B1_P2_U1_CFG15, 0x400114cf
 4449              	.set CYREG_B1_P2_U1_CFG16, 0x400114d0
 4450              	.set CYREG_B1_P2_U1_CFG17, 0x400114d1
 4451              	.set CYREG_B1_P2_U1_CFG18, 0x400114d2
 4452              	.set CYREG_B1_P2_U1_CFG19, 0x400114d3
 4453              	.set CYREG_B1_P2_U1_CFG20, 0x400114d4
 4454              	.set CYREG_B1_P2_U1_CFG21, 0x400114d5
 4455              	.set CYREG_B1_P2_U1_CFG22, 0x400114d6
 4456              	.set CYREG_B1_P2_U1_CFG23, 0x400114d7
 4457              	.set CYREG_B1_P2_U1_CFG24, 0x400114d8
 4458              	.set CYREG_B1_P2_U1_CFG25, 0x400114d9
 4459              	.set CYREG_B1_P2_U1_CFG26, 0x400114da
 4460              	.set CYREG_B1_P2_U1_CFG27, 0x400114db
 4461              	.set CYREG_B1_P2_U1_CFG28, 0x400114dc
 4462              	.set CYREG_B1_P2_U1_CFG29, 0x400114dd
 4463              	.set CYREG_B1_P2_U1_CFG30, 0x400114de
 4464              	.set CYREG_B1_P2_U1_CFG31, 0x400114df
 4465              	.set CYREG_B1_P2_U1_DCFG0, 0x400114e0
 4466              	.set CYREG_B1_P2_U1_DCFG1, 0x400114e2
 4467              	.set CYREG_B1_P2_U1_DCFG2, 0x400114e4
 4468              	.set CYREG_B1_P2_U1_DCFG3, 0x400114e6
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 174


 4469              	.set CYREG_B1_P2_U1_DCFG4, 0x400114e8
 4470              	.set CYREG_B1_P2_U1_DCFG5, 0x400114ea
 4471              	.set CYREG_B1_P2_U1_DCFG6, 0x400114ec
 4472              	.set CYREG_B1_P2_U1_DCFG7, 0x400114ee
 4473              	.set CYDEV_UCFG_B1_P2_ROUTE_BASE, 0x40011500
 4474              	.set CYDEV_UCFG_B1_P2_ROUTE_SIZE, 0x000000ef
 4475              	.set CYDEV_UCFG_B1_P3_BASE, 0x40011600
 4476              	.set CYDEV_UCFG_B1_P3_SIZE, 0x000001ef
 4477              	.set CYDEV_UCFG_B1_P3_U0_BASE, 0x40011600
 4478              	.set CYDEV_UCFG_B1_P3_U0_SIZE, 0x00000070
 4479              	.set CYREG_B1_P3_U0_PLD_IT0, 0x40011600
 4480              	.set CYREG_B1_P3_U0_PLD_IT1, 0x40011604
 4481              	.set CYREG_B1_P3_U0_PLD_IT2, 0x40011608
 4482              	.set CYREG_B1_P3_U0_PLD_IT3, 0x4001160c
 4483              	.set CYREG_B1_P3_U0_PLD_IT4, 0x40011610
 4484              	.set CYREG_B1_P3_U0_PLD_IT5, 0x40011614
 4485              	.set CYREG_B1_P3_U0_PLD_IT6, 0x40011618
 4486              	.set CYREG_B1_P3_U0_PLD_IT7, 0x4001161c
 4487              	.set CYREG_B1_P3_U0_PLD_IT8, 0x40011620
 4488              	.set CYREG_B1_P3_U0_PLD_IT9, 0x40011624
 4489              	.set CYREG_B1_P3_U0_PLD_IT10, 0x40011628
 4490              	.set CYREG_B1_P3_U0_PLD_IT11, 0x4001162c
 4491              	.set CYREG_B1_P3_U0_PLD_ORT0, 0x40011630
 4492              	.set CYREG_B1_P3_U0_PLD_ORT1, 0x40011632
 4493              	.set CYREG_B1_P3_U0_PLD_ORT2, 0x40011634
 4494              	.set CYREG_B1_P3_U0_PLD_ORT3, 0x40011636
 4495              	.set CYREG_B1_P3_U0_MC_CFG_CEN_CONST, 0x40011638
 4496              	.set CYREG_B1_P3_U0_MC_CFG_XORFB, 0x4001163a
 4497              	.set CYREG_B1_P3_U0_MC_CFG_SET_RESET, 0x4001163c
 4498              	.set CYREG_B1_P3_U0_MC_CFG_BYPASS, 0x4001163e
 4499              	.set CYREG_B1_P3_U0_CFG0, 0x40011640
 4500              	.set CYREG_B1_P3_U0_CFG1, 0x40011641
 4501              	.set CYREG_B1_P3_U0_CFG2, 0x40011642
 4502              	.set CYREG_B1_P3_U0_CFG3, 0x40011643
 4503              	.set CYREG_B1_P3_U0_CFG4, 0x40011644
 4504              	.set CYREG_B1_P3_U0_CFG5, 0x40011645
 4505              	.set CYREG_B1_P3_U0_CFG6, 0x40011646
 4506              	.set CYREG_B1_P3_U0_CFG7, 0x40011647
 4507              	.set CYREG_B1_P3_U0_CFG8, 0x40011648
 4508              	.set CYREG_B1_P3_U0_CFG9, 0x40011649
 4509              	.set CYREG_B1_P3_U0_CFG10, 0x4001164a
 4510              	.set CYREG_B1_P3_U0_CFG11, 0x4001164b
 4511              	.set CYREG_B1_P3_U0_CFG12, 0x4001164c
 4512              	.set CYREG_B1_P3_U0_CFG13, 0x4001164d
 4513              	.set CYREG_B1_P3_U0_CFG14, 0x4001164e
 4514              	.set CYREG_B1_P3_U0_CFG15, 0x4001164f
 4515              	.set CYREG_B1_P3_U0_CFG16, 0x40011650
 4516              	.set CYREG_B1_P3_U0_CFG17, 0x40011651
 4517              	.set CYREG_B1_P3_U0_CFG18, 0x40011652
 4518              	.set CYREG_B1_P3_U0_CFG19, 0x40011653
 4519              	.set CYREG_B1_P3_U0_CFG20, 0x40011654
 4520              	.set CYREG_B1_P3_U0_CFG21, 0x40011655
 4521              	.set CYREG_B1_P3_U0_CFG22, 0x40011656
 4522              	.set CYREG_B1_P3_U0_CFG23, 0x40011657
 4523              	.set CYREG_B1_P3_U0_CFG24, 0x40011658
 4524              	.set CYREG_B1_P3_U0_CFG25, 0x40011659
 4525              	.set CYREG_B1_P3_U0_CFG26, 0x4001165a
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 175


 4526              	.set CYREG_B1_P3_U0_CFG27, 0x4001165b
 4527              	.set CYREG_B1_P3_U0_CFG28, 0x4001165c
 4528              	.set CYREG_B1_P3_U0_CFG29, 0x4001165d
 4529              	.set CYREG_B1_P3_U0_CFG30, 0x4001165e
 4530              	.set CYREG_B1_P3_U0_CFG31, 0x4001165f
 4531              	.set CYREG_B1_P3_U0_DCFG0, 0x40011660
 4532              	.set CYREG_B1_P3_U0_DCFG1, 0x40011662
 4533              	.set CYREG_B1_P3_U0_DCFG2, 0x40011664
 4534              	.set CYREG_B1_P3_U0_DCFG3, 0x40011666
 4535              	.set CYREG_B1_P3_U0_DCFG4, 0x40011668
 4536              	.set CYREG_B1_P3_U0_DCFG5, 0x4001166a
 4537              	.set CYREG_B1_P3_U0_DCFG6, 0x4001166c
 4538              	.set CYREG_B1_P3_U0_DCFG7, 0x4001166e
 4539              	.set CYDEV_UCFG_B1_P3_U1_BASE, 0x40011680
 4540              	.set CYDEV_UCFG_B1_P3_U1_SIZE, 0x00000070
 4541              	.set CYREG_B1_P3_U1_PLD_IT0, 0x40011680
 4542              	.set CYREG_B1_P3_U1_PLD_IT1, 0x40011684
 4543              	.set CYREG_B1_P3_U1_PLD_IT2, 0x40011688
 4544              	.set CYREG_B1_P3_U1_PLD_IT3, 0x4001168c
 4545              	.set CYREG_B1_P3_U1_PLD_IT4, 0x40011690
 4546              	.set CYREG_B1_P3_U1_PLD_IT5, 0x40011694
 4547              	.set CYREG_B1_P3_U1_PLD_IT6, 0x40011698
 4548              	.set CYREG_B1_P3_U1_PLD_IT7, 0x4001169c
 4549              	.set CYREG_B1_P3_U1_PLD_IT8, 0x400116a0
 4550              	.set CYREG_B1_P3_U1_PLD_IT9, 0x400116a4
 4551              	.set CYREG_B1_P3_U1_PLD_IT10, 0x400116a8
 4552              	.set CYREG_B1_P3_U1_PLD_IT11, 0x400116ac
 4553              	.set CYREG_B1_P3_U1_PLD_ORT0, 0x400116b0
 4554              	.set CYREG_B1_P3_U1_PLD_ORT1, 0x400116b2
 4555              	.set CYREG_B1_P3_U1_PLD_ORT2, 0x400116b4
 4556              	.set CYREG_B1_P3_U1_PLD_ORT3, 0x400116b6
 4557              	.set CYREG_B1_P3_U1_MC_CFG_CEN_CONST, 0x400116b8
 4558              	.set CYREG_B1_P3_U1_MC_CFG_XORFB, 0x400116ba
 4559              	.set CYREG_B1_P3_U1_MC_CFG_SET_RESET, 0x400116bc
 4560              	.set CYREG_B1_P3_U1_MC_CFG_BYPASS, 0x400116be
 4561              	.set CYREG_B1_P3_U1_CFG0, 0x400116c0
 4562              	.set CYREG_B1_P3_U1_CFG1, 0x400116c1
 4563              	.set CYREG_B1_P3_U1_CFG2, 0x400116c2
 4564              	.set CYREG_B1_P3_U1_CFG3, 0x400116c3
 4565              	.set CYREG_B1_P3_U1_CFG4, 0x400116c4
 4566              	.set CYREG_B1_P3_U1_CFG5, 0x400116c5
 4567              	.set CYREG_B1_P3_U1_CFG6, 0x400116c6
 4568              	.set CYREG_B1_P3_U1_CFG7, 0x400116c7
 4569              	.set CYREG_B1_P3_U1_CFG8, 0x400116c8
 4570              	.set CYREG_B1_P3_U1_CFG9, 0x400116c9
 4571              	.set CYREG_B1_P3_U1_CFG10, 0x400116ca
 4572              	.set CYREG_B1_P3_U1_CFG11, 0x400116cb
 4573              	.set CYREG_B1_P3_U1_CFG12, 0x400116cc
 4574              	.set CYREG_B1_P3_U1_CFG13, 0x400116cd
 4575              	.set CYREG_B1_P3_U1_CFG14, 0x400116ce
 4576              	.set CYREG_B1_P3_U1_CFG15, 0x400116cf
 4577              	.set CYREG_B1_P3_U1_CFG16, 0x400116d0
 4578              	.set CYREG_B1_P3_U1_CFG17, 0x400116d1
 4579              	.set CYREG_B1_P3_U1_CFG18, 0x400116d2
 4580              	.set CYREG_B1_P3_U1_CFG19, 0x400116d3
 4581              	.set CYREG_B1_P3_U1_CFG20, 0x400116d4
 4582              	.set CYREG_B1_P3_U1_CFG21, 0x400116d5
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 176


 4583              	.set CYREG_B1_P3_U1_CFG22, 0x400116d6
 4584              	.set CYREG_B1_P3_U1_CFG23, 0x400116d7
 4585              	.set CYREG_B1_P3_U1_CFG24, 0x400116d8
 4586              	.set CYREG_B1_P3_U1_CFG25, 0x400116d9
 4587              	.set CYREG_B1_P3_U1_CFG26, 0x400116da
 4588              	.set CYREG_B1_P3_U1_CFG27, 0x400116db
 4589              	.set CYREG_B1_P3_U1_CFG28, 0x400116dc
 4590              	.set CYREG_B1_P3_U1_CFG29, 0x400116dd
 4591              	.set CYREG_B1_P3_U1_CFG30, 0x400116de
 4592              	.set CYREG_B1_P3_U1_CFG31, 0x400116df
 4593              	.set CYREG_B1_P3_U1_DCFG0, 0x400116e0
 4594              	.set CYREG_B1_P3_U1_DCFG1, 0x400116e2
 4595              	.set CYREG_B1_P3_U1_DCFG2, 0x400116e4
 4596              	.set CYREG_B1_P3_U1_DCFG3, 0x400116e6
 4597              	.set CYREG_B1_P3_U1_DCFG4, 0x400116e8
 4598              	.set CYREG_B1_P3_U1_DCFG5, 0x400116ea
 4599              	.set CYREG_B1_P3_U1_DCFG6, 0x400116ec
 4600              	.set CYREG_B1_P3_U1_DCFG7, 0x400116ee
 4601              	.set CYDEV_UCFG_B1_P3_ROUTE_BASE, 0x40011700
 4602              	.set CYDEV_UCFG_B1_P3_ROUTE_SIZE, 0x000000ef
 4603              	.set CYDEV_UCFG_B1_P4_BASE, 0x40011800
 4604              	.set CYDEV_UCFG_B1_P4_SIZE, 0x000001ef
 4605              	.set CYDEV_UCFG_B1_P4_U0_BASE, 0x40011800
 4606              	.set CYDEV_UCFG_B1_P4_U0_SIZE, 0x00000070
 4607              	.set CYREG_B1_P4_U0_PLD_IT0, 0x40011800
 4608              	.set CYREG_B1_P4_U0_PLD_IT1, 0x40011804
 4609              	.set CYREG_B1_P4_U0_PLD_IT2, 0x40011808
 4610              	.set CYREG_B1_P4_U0_PLD_IT3, 0x4001180c
 4611              	.set CYREG_B1_P4_U0_PLD_IT4, 0x40011810
 4612              	.set CYREG_B1_P4_U0_PLD_IT5, 0x40011814
 4613              	.set CYREG_B1_P4_U0_PLD_IT6, 0x40011818
 4614              	.set CYREG_B1_P4_U0_PLD_IT7, 0x4001181c
 4615              	.set CYREG_B1_P4_U0_PLD_IT8, 0x40011820
 4616              	.set CYREG_B1_P4_U0_PLD_IT9, 0x40011824
 4617              	.set CYREG_B1_P4_U0_PLD_IT10, 0x40011828
 4618              	.set CYREG_B1_P4_U0_PLD_IT11, 0x4001182c
 4619              	.set CYREG_B1_P4_U0_PLD_ORT0, 0x40011830
 4620              	.set CYREG_B1_P4_U0_PLD_ORT1, 0x40011832
 4621              	.set CYREG_B1_P4_U0_PLD_ORT2, 0x40011834
 4622              	.set CYREG_B1_P4_U0_PLD_ORT3, 0x40011836
 4623              	.set CYREG_B1_P4_U0_MC_CFG_CEN_CONST, 0x40011838
 4624              	.set CYREG_B1_P4_U0_MC_CFG_XORFB, 0x4001183a
 4625              	.set CYREG_B1_P4_U0_MC_CFG_SET_RESET, 0x4001183c
 4626              	.set CYREG_B1_P4_U0_MC_CFG_BYPASS, 0x4001183e
 4627              	.set CYREG_B1_P4_U0_CFG0, 0x40011840
 4628              	.set CYREG_B1_P4_U0_CFG1, 0x40011841
 4629              	.set CYREG_B1_P4_U0_CFG2, 0x40011842
 4630              	.set CYREG_B1_P4_U0_CFG3, 0x40011843
 4631              	.set CYREG_B1_P4_U0_CFG4, 0x40011844
 4632              	.set CYREG_B1_P4_U0_CFG5, 0x40011845
 4633              	.set CYREG_B1_P4_U0_CFG6, 0x40011846
 4634              	.set CYREG_B1_P4_U0_CFG7, 0x40011847
 4635              	.set CYREG_B1_P4_U0_CFG8, 0x40011848
 4636              	.set CYREG_B1_P4_U0_CFG9, 0x40011849
 4637              	.set CYREG_B1_P4_U0_CFG10, 0x4001184a
 4638              	.set CYREG_B1_P4_U0_CFG11, 0x4001184b
 4639              	.set CYREG_B1_P4_U0_CFG12, 0x4001184c
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 177


 4640              	.set CYREG_B1_P4_U0_CFG13, 0x4001184d
 4641              	.set CYREG_B1_P4_U0_CFG14, 0x4001184e
 4642              	.set CYREG_B1_P4_U0_CFG15, 0x4001184f
 4643              	.set CYREG_B1_P4_U0_CFG16, 0x40011850
 4644              	.set CYREG_B1_P4_U0_CFG17, 0x40011851
 4645              	.set CYREG_B1_P4_U0_CFG18, 0x40011852
 4646              	.set CYREG_B1_P4_U0_CFG19, 0x40011853
 4647              	.set CYREG_B1_P4_U0_CFG20, 0x40011854
 4648              	.set CYREG_B1_P4_U0_CFG21, 0x40011855
 4649              	.set CYREG_B1_P4_U0_CFG22, 0x40011856
 4650              	.set CYREG_B1_P4_U0_CFG23, 0x40011857
 4651              	.set CYREG_B1_P4_U0_CFG24, 0x40011858
 4652              	.set CYREG_B1_P4_U0_CFG25, 0x40011859
 4653              	.set CYREG_B1_P4_U0_CFG26, 0x4001185a
 4654              	.set CYREG_B1_P4_U0_CFG27, 0x4001185b
 4655              	.set CYREG_B1_P4_U0_CFG28, 0x4001185c
 4656              	.set CYREG_B1_P4_U0_CFG29, 0x4001185d
 4657              	.set CYREG_B1_P4_U0_CFG30, 0x4001185e
 4658              	.set CYREG_B1_P4_U0_CFG31, 0x4001185f
 4659              	.set CYREG_B1_P4_U0_DCFG0, 0x40011860
 4660              	.set CYREG_B1_P4_U0_DCFG1, 0x40011862
 4661              	.set CYREG_B1_P4_U0_DCFG2, 0x40011864
 4662              	.set CYREG_B1_P4_U0_DCFG3, 0x40011866
 4663              	.set CYREG_B1_P4_U0_DCFG4, 0x40011868
 4664              	.set CYREG_B1_P4_U0_DCFG5, 0x4001186a
 4665              	.set CYREG_B1_P4_U0_DCFG6, 0x4001186c
 4666              	.set CYREG_B1_P4_U0_DCFG7, 0x4001186e
 4667              	.set CYDEV_UCFG_B1_P4_U1_BASE, 0x40011880
 4668              	.set CYDEV_UCFG_B1_P4_U1_SIZE, 0x00000070
 4669              	.set CYREG_B1_P4_U1_PLD_IT0, 0x40011880
 4670              	.set CYREG_B1_P4_U1_PLD_IT1, 0x40011884
 4671              	.set CYREG_B1_P4_U1_PLD_IT2, 0x40011888
 4672              	.set CYREG_B1_P4_U1_PLD_IT3, 0x4001188c
 4673              	.set CYREG_B1_P4_U1_PLD_IT4, 0x40011890
 4674              	.set CYREG_B1_P4_U1_PLD_IT5, 0x40011894
 4675              	.set CYREG_B1_P4_U1_PLD_IT6, 0x40011898
 4676              	.set CYREG_B1_P4_U1_PLD_IT7, 0x4001189c
 4677              	.set CYREG_B1_P4_U1_PLD_IT8, 0x400118a0
 4678              	.set CYREG_B1_P4_U1_PLD_IT9, 0x400118a4
 4679              	.set CYREG_B1_P4_U1_PLD_IT10, 0x400118a8
 4680              	.set CYREG_B1_P4_U1_PLD_IT11, 0x400118ac
 4681              	.set CYREG_B1_P4_U1_PLD_ORT0, 0x400118b0
 4682              	.set CYREG_B1_P4_U1_PLD_ORT1, 0x400118b2
 4683              	.set CYREG_B1_P4_U1_PLD_ORT2, 0x400118b4
 4684              	.set CYREG_B1_P4_U1_PLD_ORT3, 0x400118b6
 4685              	.set CYREG_B1_P4_U1_MC_CFG_CEN_CONST, 0x400118b8
 4686              	.set CYREG_B1_P4_U1_MC_CFG_XORFB, 0x400118ba
 4687              	.set CYREG_B1_P4_U1_MC_CFG_SET_RESET, 0x400118bc
 4688              	.set CYREG_B1_P4_U1_MC_CFG_BYPASS, 0x400118be
 4689              	.set CYREG_B1_P4_U1_CFG0, 0x400118c0
 4690              	.set CYREG_B1_P4_U1_CFG1, 0x400118c1
 4691              	.set CYREG_B1_P4_U1_CFG2, 0x400118c2
 4692              	.set CYREG_B1_P4_U1_CFG3, 0x400118c3
 4693              	.set CYREG_B1_P4_U1_CFG4, 0x400118c4
 4694              	.set CYREG_B1_P4_U1_CFG5, 0x400118c5
 4695              	.set CYREG_B1_P4_U1_CFG6, 0x400118c6
 4696              	.set CYREG_B1_P4_U1_CFG7, 0x400118c7
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 178


 4697              	.set CYREG_B1_P4_U1_CFG8, 0x400118c8
 4698              	.set CYREG_B1_P4_U1_CFG9, 0x400118c9
 4699              	.set CYREG_B1_P4_U1_CFG10, 0x400118ca
 4700              	.set CYREG_B1_P4_U1_CFG11, 0x400118cb
 4701              	.set CYREG_B1_P4_U1_CFG12, 0x400118cc
 4702              	.set CYREG_B1_P4_U1_CFG13, 0x400118cd
 4703              	.set CYREG_B1_P4_U1_CFG14, 0x400118ce
 4704              	.set CYREG_B1_P4_U1_CFG15, 0x400118cf
 4705              	.set CYREG_B1_P4_U1_CFG16, 0x400118d0
 4706              	.set CYREG_B1_P4_U1_CFG17, 0x400118d1
 4707              	.set CYREG_B1_P4_U1_CFG18, 0x400118d2
 4708              	.set CYREG_B1_P4_U1_CFG19, 0x400118d3
 4709              	.set CYREG_B1_P4_U1_CFG20, 0x400118d4
 4710              	.set CYREG_B1_P4_U1_CFG21, 0x400118d5
 4711              	.set CYREG_B1_P4_U1_CFG22, 0x400118d6
 4712              	.set CYREG_B1_P4_U1_CFG23, 0x400118d7
 4713              	.set CYREG_B1_P4_U1_CFG24, 0x400118d8
 4714              	.set CYREG_B1_P4_U1_CFG25, 0x400118d9
 4715              	.set CYREG_B1_P4_U1_CFG26, 0x400118da
 4716              	.set CYREG_B1_P4_U1_CFG27, 0x400118db
 4717              	.set CYREG_B1_P4_U1_CFG28, 0x400118dc
 4718              	.set CYREG_B1_P4_U1_CFG29, 0x400118dd
 4719              	.set CYREG_B1_P4_U1_CFG30, 0x400118de
 4720              	.set CYREG_B1_P4_U1_CFG31, 0x400118df
 4721              	.set CYREG_B1_P4_U1_DCFG0, 0x400118e0
 4722              	.set CYREG_B1_P4_U1_DCFG1, 0x400118e2
 4723              	.set CYREG_B1_P4_U1_DCFG2, 0x400118e4
 4724              	.set CYREG_B1_P4_U1_DCFG3, 0x400118e6
 4725              	.set CYREG_B1_P4_U1_DCFG4, 0x400118e8
 4726              	.set CYREG_B1_P4_U1_DCFG5, 0x400118ea
 4727              	.set CYREG_B1_P4_U1_DCFG6, 0x400118ec
 4728              	.set CYREG_B1_P4_U1_DCFG7, 0x400118ee
 4729              	.set CYDEV_UCFG_B1_P4_ROUTE_BASE, 0x40011900
 4730              	.set CYDEV_UCFG_B1_P4_ROUTE_SIZE, 0x000000ef
 4731              	.set CYDEV_UCFG_B1_P5_BASE, 0x40011a00
 4732              	.set CYDEV_UCFG_B1_P5_SIZE, 0x000001ef
 4733              	.set CYDEV_UCFG_B1_P5_U0_BASE, 0x40011a00
 4734              	.set CYDEV_UCFG_B1_P5_U0_SIZE, 0x00000070
 4735              	.set CYREG_B1_P5_U0_PLD_IT0, 0x40011a00
 4736              	.set CYREG_B1_P5_U0_PLD_IT1, 0x40011a04
 4737              	.set CYREG_B1_P5_U0_PLD_IT2, 0x40011a08
 4738              	.set CYREG_B1_P5_U0_PLD_IT3, 0x40011a0c
 4739              	.set CYREG_B1_P5_U0_PLD_IT4, 0x40011a10
 4740              	.set CYREG_B1_P5_U0_PLD_IT5, 0x40011a14
 4741              	.set CYREG_B1_P5_U0_PLD_IT6, 0x40011a18
 4742              	.set CYREG_B1_P5_U0_PLD_IT7, 0x40011a1c
 4743              	.set CYREG_B1_P5_U0_PLD_IT8, 0x40011a20
 4744              	.set CYREG_B1_P5_U0_PLD_IT9, 0x40011a24
 4745              	.set CYREG_B1_P5_U0_PLD_IT10, 0x40011a28
 4746              	.set CYREG_B1_P5_U0_PLD_IT11, 0x40011a2c
 4747              	.set CYREG_B1_P5_U0_PLD_ORT0, 0x40011a30
 4748              	.set CYREG_B1_P5_U0_PLD_ORT1, 0x40011a32
 4749              	.set CYREG_B1_P5_U0_PLD_ORT2, 0x40011a34
 4750              	.set CYREG_B1_P5_U0_PLD_ORT3, 0x40011a36
 4751              	.set CYREG_B1_P5_U0_MC_CFG_CEN_CONST, 0x40011a38
 4752              	.set CYREG_B1_P5_U0_MC_CFG_XORFB, 0x40011a3a
 4753              	.set CYREG_B1_P5_U0_MC_CFG_SET_RESET, 0x40011a3c
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 179


 4754              	.set CYREG_B1_P5_U0_MC_CFG_BYPASS, 0x40011a3e
 4755              	.set CYREG_B1_P5_U0_CFG0, 0x40011a40
 4756              	.set CYREG_B1_P5_U0_CFG1, 0x40011a41
 4757              	.set CYREG_B1_P5_U0_CFG2, 0x40011a42
 4758              	.set CYREG_B1_P5_U0_CFG3, 0x40011a43
 4759              	.set CYREG_B1_P5_U0_CFG4, 0x40011a44
 4760              	.set CYREG_B1_P5_U0_CFG5, 0x40011a45
 4761              	.set CYREG_B1_P5_U0_CFG6, 0x40011a46
 4762              	.set CYREG_B1_P5_U0_CFG7, 0x40011a47
 4763              	.set CYREG_B1_P5_U0_CFG8, 0x40011a48
 4764              	.set CYREG_B1_P5_U0_CFG9, 0x40011a49
 4765              	.set CYREG_B1_P5_U0_CFG10, 0x40011a4a
 4766              	.set CYREG_B1_P5_U0_CFG11, 0x40011a4b
 4767              	.set CYREG_B1_P5_U0_CFG12, 0x40011a4c
 4768              	.set CYREG_B1_P5_U0_CFG13, 0x40011a4d
 4769              	.set CYREG_B1_P5_U0_CFG14, 0x40011a4e
 4770              	.set CYREG_B1_P5_U0_CFG15, 0x40011a4f
 4771              	.set CYREG_B1_P5_U0_CFG16, 0x40011a50
 4772              	.set CYREG_B1_P5_U0_CFG17, 0x40011a51
 4773              	.set CYREG_B1_P5_U0_CFG18, 0x40011a52
 4774              	.set CYREG_B1_P5_U0_CFG19, 0x40011a53
 4775              	.set CYREG_B1_P5_U0_CFG20, 0x40011a54
 4776              	.set CYREG_B1_P5_U0_CFG21, 0x40011a55
 4777              	.set CYREG_B1_P5_U0_CFG22, 0x40011a56
 4778              	.set CYREG_B1_P5_U0_CFG23, 0x40011a57
 4779              	.set CYREG_B1_P5_U0_CFG24, 0x40011a58
 4780              	.set CYREG_B1_P5_U0_CFG25, 0x40011a59
 4781              	.set CYREG_B1_P5_U0_CFG26, 0x40011a5a
 4782              	.set CYREG_B1_P5_U0_CFG27, 0x40011a5b
 4783              	.set CYREG_B1_P5_U0_CFG28, 0x40011a5c
 4784              	.set CYREG_B1_P5_U0_CFG29, 0x40011a5d
 4785              	.set CYREG_B1_P5_U0_CFG30, 0x40011a5e
 4786              	.set CYREG_B1_P5_U0_CFG31, 0x40011a5f
 4787              	.set CYREG_B1_P5_U0_DCFG0, 0x40011a60
 4788              	.set CYREG_B1_P5_U0_DCFG1, 0x40011a62
 4789              	.set CYREG_B1_P5_U0_DCFG2, 0x40011a64
 4790              	.set CYREG_B1_P5_U0_DCFG3, 0x40011a66
 4791              	.set CYREG_B1_P5_U0_DCFG4, 0x40011a68
 4792              	.set CYREG_B1_P5_U0_DCFG5, 0x40011a6a
 4793              	.set CYREG_B1_P5_U0_DCFG6, 0x40011a6c
 4794              	.set CYREG_B1_P5_U0_DCFG7, 0x40011a6e
 4795              	.set CYDEV_UCFG_B1_P5_U1_BASE, 0x40011a80
 4796              	.set CYDEV_UCFG_B1_P5_U1_SIZE, 0x00000070
 4797              	.set CYREG_B1_P5_U1_PLD_IT0, 0x40011a80
 4798              	.set CYREG_B1_P5_U1_PLD_IT1, 0x40011a84
 4799              	.set CYREG_B1_P5_U1_PLD_IT2, 0x40011a88
 4800              	.set CYREG_B1_P5_U1_PLD_IT3, 0x40011a8c
 4801              	.set CYREG_B1_P5_U1_PLD_IT4, 0x40011a90
 4802              	.set CYREG_B1_P5_U1_PLD_IT5, 0x40011a94
 4803              	.set CYREG_B1_P5_U1_PLD_IT6, 0x40011a98
 4804              	.set CYREG_B1_P5_U1_PLD_IT7, 0x40011a9c
 4805              	.set CYREG_B1_P5_U1_PLD_IT8, 0x40011aa0
 4806              	.set CYREG_B1_P5_U1_PLD_IT9, 0x40011aa4
 4807              	.set CYREG_B1_P5_U1_PLD_IT10, 0x40011aa8
 4808              	.set CYREG_B1_P5_U1_PLD_IT11, 0x40011aac
 4809              	.set CYREG_B1_P5_U1_PLD_ORT0, 0x40011ab0
 4810              	.set CYREG_B1_P5_U1_PLD_ORT1, 0x40011ab2
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 180


 4811              	.set CYREG_B1_P5_U1_PLD_ORT2, 0x40011ab4
 4812              	.set CYREG_B1_P5_U1_PLD_ORT3, 0x40011ab6
 4813              	.set CYREG_B1_P5_U1_MC_CFG_CEN_CONST, 0x40011ab8
 4814              	.set CYREG_B1_P5_U1_MC_CFG_XORFB, 0x40011aba
 4815              	.set CYREG_B1_P5_U1_MC_CFG_SET_RESET, 0x40011abc
 4816              	.set CYREG_B1_P5_U1_MC_CFG_BYPASS, 0x40011abe
 4817              	.set CYREG_B1_P5_U1_CFG0, 0x40011ac0
 4818              	.set CYREG_B1_P5_U1_CFG1, 0x40011ac1
 4819              	.set CYREG_B1_P5_U1_CFG2, 0x40011ac2
 4820              	.set CYREG_B1_P5_U1_CFG3, 0x40011ac3
 4821              	.set CYREG_B1_P5_U1_CFG4, 0x40011ac4
 4822              	.set CYREG_B1_P5_U1_CFG5, 0x40011ac5
 4823              	.set CYREG_B1_P5_U1_CFG6, 0x40011ac6
 4824              	.set CYREG_B1_P5_U1_CFG7, 0x40011ac7
 4825              	.set CYREG_B1_P5_U1_CFG8, 0x40011ac8
 4826              	.set CYREG_B1_P5_U1_CFG9, 0x40011ac9
 4827              	.set CYREG_B1_P5_U1_CFG10, 0x40011aca
 4828              	.set CYREG_B1_P5_U1_CFG11, 0x40011acb
 4829              	.set CYREG_B1_P5_U1_CFG12, 0x40011acc
 4830              	.set CYREG_B1_P5_U1_CFG13, 0x40011acd
 4831              	.set CYREG_B1_P5_U1_CFG14, 0x40011ace
 4832              	.set CYREG_B1_P5_U1_CFG15, 0x40011acf
 4833              	.set CYREG_B1_P5_U1_CFG16, 0x40011ad0
 4834              	.set CYREG_B1_P5_U1_CFG17, 0x40011ad1
 4835              	.set CYREG_B1_P5_U1_CFG18, 0x40011ad2
 4836              	.set CYREG_B1_P5_U1_CFG19, 0x40011ad3
 4837              	.set CYREG_B1_P5_U1_CFG20, 0x40011ad4
 4838              	.set CYREG_B1_P5_U1_CFG21, 0x40011ad5
 4839              	.set CYREG_B1_P5_U1_CFG22, 0x40011ad6
 4840              	.set CYREG_B1_P5_U1_CFG23, 0x40011ad7
 4841              	.set CYREG_B1_P5_U1_CFG24, 0x40011ad8
 4842              	.set CYREG_B1_P5_U1_CFG25, 0x40011ad9
 4843              	.set CYREG_B1_P5_U1_CFG26, 0x40011ada
 4844              	.set CYREG_B1_P5_U1_CFG27, 0x40011adb
 4845              	.set CYREG_B1_P5_U1_CFG28, 0x40011adc
 4846              	.set CYREG_B1_P5_U1_CFG29, 0x40011add
 4847              	.set CYREG_B1_P5_U1_CFG30, 0x40011ade
 4848              	.set CYREG_B1_P5_U1_CFG31, 0x40011adf
 4849              	.set CYREG_B1_P5_U1_DCFG0, 0x40011ae0
 4850              	.set CYREG_B1_P5_U1_DCFG1, 0x40011ae2
 4851              	.set CYREG_B1_P5_U1_DCFG2, 0x40011ae4
 4852              	.set CYREG_B1_P5_U1_DCFG3, 0x40011ae6
 4853              	.set CYREG_B1_P5_U1_DCFG4, 0x40011ae8
 4854              	.set CYREG_B1_P5_U1_DCFG5, 0x40011aea
 4855              	.set CYREG_B1_P5_U1_DCFG6, 0x40011aec
 4856              	.set CYREG_B1_P5_U1_DCFG7, 0x40011aee
 4857              	.set CYDEV_UCFG_B1_P5_ROUTE_BASE, 0x40011b00
 4858              	.set CYDEV_UCFG_B1_P5_ROUTE_SIZE, 0x000000ef
 4859              	.set CYDEV_UCFG_DSI0_BASE, 0x40014000
 4860              	.set CYDEV_UCFG_DSI0_SIZE, 0x000000ef
 4861              	.set CYDEV_UCFG_DSI1_BASE, 0x40014100
 4862              	.set CYDEV_UCFG_DSI1_SIZE, 0x000000ef
 4863              	.set CYDEV_UCFG_DSI2_BASE, 0x40014200
 4864              	.set CYDEV_UCFG_DSI2_SIZE, 0x000000ef
 4865              	.set CYDEV_UCFG_DSI3_BASE, 0x40014300
 4866              	.set CYDEV_UCFG_DSI3_SIZE, 0x000000ef
 4867              	.set CYDEV_UCFG_DSI4_BASE, 0x40014400
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 181


 4868              	.set CYDEV_UCFG_DSI4_SIZE, 0x000000ef
 4869              	.set CYDEV_UCFG_DSI5_BASE, 0x40014500
 4870              	.set CYDEV_UCFG_DSI5_SIZE, 0x000000ef
 4871              	.set CYDEV_UCFG_DSI6_BASE, 0x40014600
 4872              	.set CYDEV_UCFG_DSI6_SIZE, 0x000000ef
 4873              	.set CYDEV_UCFG_DSI7_BASE, 0x40014700
 4874              	.set CYDEV_UCFG_DSI7_SIZE, 0x000000ef
 4875              	.set CYDEV_UCFG_DSI8_BASE, 0x40014800
 4876              	.set CYDEV_UCFG_DSI8_SIZE, 0x000000ef
 4877              	.set CYDEV_UCFG_DSI9_BASE, 0x40014900
 4878              	.set CYDEV_UCFG_DSI9_SIZE, 0x000000ef
 4879              	.set CYDEV_UCFG_DSI12_BASE, 0x40014c00
 4880              	.set CYDEV_UCFG_DSI12_SIZE, 0x000000ef
 4881              	.set CYDEV_UCFG_DSI13_BASE, 0x40014d00
 4882              	.set CYDEV_UCFG_DSI13_SIZE, 0x000000ef
 4883              	.set CYDEV_UCFG_BCTL0_BASE, 0x40015000
 4884              	.set CYDEV_UCFG_BCTL0_SIZE, 0x00000010
 4885              	.set CYREG_BCTL0_MDCLK_EN, 0x40015000
 4886              	.set CYREG_BCTL0_MBCLK_EN, 0x40015001
 4887              	.set CYREG_BCTL0_WAIT_CFG, 0x40015002
 4888              	.set CYREG_BCTL0_BANK_CTL, 0x40015003
 4889              	.set CYREG_BCTL0_UDB_TEST_3, 0x40015007
 4890              	.set CYREG_BCTL0_DCLK_EN0, 0x40015008
 4891              	.set CYREG_BCTL0_BCLK_EN0, 0x40015009
 4892              	.set CYREG_BCTL0_DCLK_EN1, 0x4001500a
 4893              	.set CYREG_BCTL0_BCLK_EN1, 0x4001500b
 4894              	.set CYREG_BCTL0_DCLK_EN2, 0x4001500c
 4895              	.set CYREG_BCTL0_BCLK_EN2, 0x4001500d
 4896              	.set CYREG_BCTL0_DCLK_EN3, 0x4001500e
 4897              	.set CYREG_BCTL0_BCLK_EN3, 0x4001500f
 4898              	.set CYDEV_UCFG_BCTL1_BASE, 0x40015010
 4899              	.set CYDEV_UCFG_BCTL1_SIZE, 0x00000010
 4900              	.set CYREG_BCTL1_MDCLK_EN, 0x40015010
 4901              	.set CYREG_BCTL1_MBCLK_EN, 0x40015011
 4902              	.set CYREG_BCTL1_WAIT_CFG, 0x40015012
 4903              	.set CYREG_BCTL1_BANK_CTL, 0x40015013
 4904              	.set CYREG_BCTL1_UDB_TEST_3, 0x40015017
 4905              	.set CYREG_BCTL1_DCLK_EN0, 0x40015018
 4906              	.set CYREG_BCTL1_BCLK_EN0, 0x40015019
 4907              	.set CYREG_BCTL1_DCLK_EN1, 0x4001501a
 4908              	.set CYREG_BCTL1_BCLK_EN1, 0x4001501b
 4909              	.set CYREG_BCTL1_DCLK_EN2, 0x4001501c
 4910              	.set CYREG_BCTL1_BCLK_EN2, 0x4001501d
 4911              	.set CYREG_BCTL1_DCLK_EN3, 0x4001501e
 4912              	.set CYREG_BCTL1_BCLK_EN3, 0x4001501f
 4913              	.set CYDEV_IDMUX_BASE, 0x40015100
 4914              	.set CYDEV_IDMUX_SIZE, 0x00000016
 4915              	.set CYREG_IDMUX_IRQ_CTL0, 0x40015100
 4916              	.set CYREG_IDMUX_IRQ_CTL1, 0x40015101
 4917              	.set CYREG_IDMUX_IRQ_CTL2, 0x40015102
 4918              	.set CYREG_IDMUX_IRQ_CTL3, 0x40015103
 4919              	.set CYREG_IDMUX_IRQ_CTL4, 0x40015104
 4920              	.set CYREG_IDMUX_IRQ_CTL5, 0x40015105
 4921              	.set CYREG_IDMUX_IRQ_CTL6, 0x40015106
 4922              	.set CYREG_IDMUX_IRQ_CTL7, 0x40015107
 4923              	.set CYREG_IDMUX_DRQ_CTL0, 0x40015110
 4924              	.set CYREG_IDMUX_DRQ_CTL1, 0x40015111
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 182


 4925              	.set CYREG_IDMUX_DRQ_CTL2, 0x40015112
 4926              	.set CYREG_IDMUX_DRQ_CTL3, 0x40015113
 4927              	.set CYREG_IDMUX_DRQ_CTL4, 0x40015114
 4928              	.set CYREG_IDMUX_DRQ_CTL5, 0x40015115
 4929              	.set CYDEV_CACHERAM_BASE, 0x40030000
 4930              	.set CYDEV_CACHERAM_SIZE, 0x00000400
 4931              	.set CYREG_CACHERAM_DATA_MBASE, 0x40030000
 4932              	.set CYREG_CACHERAM_DATA_MSIZE, 0x00000400
 4933              	.set CYDEV_SFR_BASE, 0x40050100
 4934              	.set CYDEV_SFR_SIZE, 0x000000fb
 4935              	.set CYREG_SFR_GPIO0, 0x40050180
 4936              	.set CYREG_SFR_GPIRD0, 0x40050189
 4937              	.set CYREG_SFR_GPIO0_SEL, 0x4005018a
 4938              	.set CYREG_SFR_GPIO1, 0x40050190
 4939              	.set CYREG_SFR_GPIRD1, 0x40050191
 4940              	.set CYREG_SFR_GPIO2, 0x40050198
 4941              	.set CYREG_SFR_GPIRD2, 0x40050199
 4942              	.set CYREG_SFR_GPIO2_SEL, 0x4005019a
 4943              	.set CYREG_SFR_GPIO1_SEL, 0x400501a2
 4944              	.set CYREG_SFR_GPIO3, 0x400501b0
 4945              	.set CYREG_SFR_GPIRD3, 0x400501b1
 4946              	.set CYREG_SFR_GPIO3_SEL, 0x400501b2
 4947              	.set CYREG_SFR_GPIO4, 0x400501c0
 4948              	.set CYREG_SFR_GPIRD4, 0x400501c1
 4949              	.set CYREG_SFR_GPIO4_SEL, 0x400501c2
 4950              	.set CYREG_SFR_GPIO5, 0x400501c8
 4951              	.set CYREG_SFR_GPIRD5, 0x400501c9
 4952              	.set CYREG_SFR_GPIO5_SEL, 0x400501ca
 4953              	.set CYREG_SFR_GPIO6, 0x400501d8
 4954              	.set CYREG_SFR_GPIRD6, 0x400501d9
 4955              	.set CYREG_SFR_GPIO6_SEL, 0x400501da
 4956              	.set CYREG_SFR_GPIO12, 0x400501e8
 4957              	.set CYREG_SFR_GPIRD12, 0x400501e9
 4958              	.set CYREG_SFR_GPIO12_SEL, 0x400501f2
 4959              	.set CYREG_SFR_GPIO15, 0x400501f8
 4960              	.set CYREG_SFR_GPIRD15, 0x400501f9
 4961              	.set CYREG_SFR_GPIO15_SEL, 0x400501fa
 4962              	.set CYDEV_P3BA_BASE, 0x40050300
 4963              	.set CYDEV_P3BA_SIZE, 0x0000002b
 4964              	.set CYREG_P3BA_Y_START, 0x40050300
 4965              	.set CYREG_P3BA_YROLL, 0x40050301
 4966              	.set CYREG_P3BA_YCFG, 0x40050302
 4967              	.set CYREG_P3BA_X_START1, 0x40050303
 4968              	.set CYREG_P3BA_X_START2, 0x40050304
 4969              	.set CYREG_P3BA_XROLL1, 0x40050305
 4970              	.set CYREG_P3BA_XROLL2, 0x40050306
 4971              	.set CYREG_P3BA_XINC, 0x40050307
 4972              	.set CYREG_P3BA_XCFG, 0x40050308
 4973              	.set CYREG_P3BA_OFFSETADDR1, 0x40050309
 4974              	.set CYREG_P3BA_OFFSETADDR2, 0x4005030a
 4975              	.set CYREG_P3BA_OFFSETADDR3, 0x4005030b
 4976              	.set CYREG_P3BA_ABSADDR1, 0x4005030c
 4977              	.set CYREG_P3BA_ABSADDR2, 0x4005030d
 4978              	.set CYREG_P3BA_ABSADDR3, 0x4005030e
 4979              	.set CYREG_P3BA_ABSADDR4, 0x4005030f
 4980              	.set CYREG_P3BA_DATCFG1, 0x40050310
 4981              	.set CYREG_P3BA_DATCFG2, 0x40050311
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 183


 4982              	.set CYREG_P3BA_CMP_RSLT1, 0x40050314
 4983              	.set CYREG_P3BA_CMP_RSLT2, 0x40050315
 4984              	.set CYREG_P3BA_CMP_RSLT3, 0x40050316
 4985              	.set CYREG_P3BA_CMP_RSLT4, 0x40050317
 4986              	.set CYREG_P3BA_DATA_REG1, 0x40050318
 4987              	.set CYREG_P3BA_DATA_REG2, 0x40050319
 4988              	.set CYREG_P3BA_DATA_REG3, 0x4005031a
 4989              	.set CYREG_P3BA_DATA_REG4, 0x4005031b
 4990              	.set CYREG_P3BA_EXP_DATA1, 0x4005031c
 4991              	.set CYREG_P3BA_EXP_DATA2, 0x4005031d
 4992              	.set CYREG_P3BA_EXP_DATA3, 0x4005031e
 4993              	.set CYREG_P3BA_EXP_DATA4, 0x4005031f
 4994              	.set CYREG_P3BA_MSTR_HRDATA1, 0x40050320
 4995              	.set CYREG_P3BA_MSTR_HRDATA2, 0x40050321
 4996              	.set CYREG_P3BA_MSTR_HRDATA3, 0x40050322
 4997              	.set CYREG_P3BA_MSTR_HRDATA4, 0x40050323
 4998              	.set CYREG_P3BA_BIST_EN, 0x40050324
 4999              	.set CYREG_P3BA_PHUB_MASTER_SSR, 0x40050325
 5000              	.set CYREG_P3BA_SEQCFG1, 0x40050326
 5001              	.set CYREG_P3BA_SEQCFG2, 0x40050327
 5002              	.set CYREG_P3BA_Y_CURR, 0x40050328
 5003              	.set CYREG_P3BA_X_CURR1, 0x40050329
 5004              	.set CYREG_P3BA_X_CURR2, 0x4005032a
 5005              	.set CYDEV_PANTHER_BASE, 0x40080000
 5006              	.set CYDEV_PANTHER_SIZE, 0x00000020
 5007              	.set CYREG_PANTHER_STCALIB_CFG, 0x40080000
 5008              	.set CYREG_PANTHER_WAITPIPE, 0x40080004
 5009              	.set CYREG_PANTHER_TRACE_CFG, 0x40080008
 5010              	.set CYREG_PANTHER_DBG_CFG, 0x4008000c
 5011              	.set CYREG_PANTHER_CM3_LCKRST_STAT, 0x40080018
 5012              	.set CYREG_PANTHER_DEVICE_ID, 0x4008001c
 5013              	.set CYDEV_FLSECC_BASE, 0x48000000
 5014              	.set CYDEV_FLSECC_SIZE, 0x00008000
 5015              	.set CYREG_FLSECC_DATA_MBASE, 0x48000000
 5016              	.set CYREG_FLSECC_DATA_MSIZE, 0x00008000
 5017              	.set CYDEV_FLSHID_BASE, 0x49000000
 5018              	.set CYDEV_FLSHID_SIZE, 0x00000200
 5019              	.set CYREG_FLSHID_RSVD_MBASE, 0x49000000
 5020              	.set CYREG_FLSHID_RSVD_MSIZE, 0x00000080
 5021              	.set CYREG_FLSHID_CUST_MDATA_MBASE, 0x49000080
 5022              	.set CYREG_FLSHID_CUST_MDATA_MSIZE, 0x00000080
 5023              	.set CYDEV_FLSHID_CUST_TABLES_BASE, 0x49000100
 5024              	.set CYDEV_FLSHID_CUST_TABLES_SIZE, 0x00000040
 5025              	.set CYREG_FLSHID_CUST_TABLES_Y_LOC, 0x49000100
 5026              	.set CYREG_FLSHID_CUST_TABLES_X_LOC, 0x49000101
 5027              	.set CYREG_FLSHID_CUST_TABLES_WAFER_NUM, 0x49000102
 5028              	.set CYREG_FLSHID_CUST_TABLES_LOT_LSB, 0x49000103
 5029              	.set CYREG_FLSHID_CUST_TABLES_LOT_MSB, 0x49000104
 5030              	.set CYREG_FLSHID_CUST_TABLES_WRK_WK, 0x49000105
 5031              	.set CYREG_FLSHID_CUST_TABLES_FAB_YR, 0x49000106
 5032              	.set CYREG_FLSHID_CUST_TABLES_MINOR, 0x49000107
 5033              	.set CYREG_FLSHID_CUST_TABLES_IMO_3MHZ, 0x49000108
 5034              	.set CYREG_FLSHID_CUST_TABLES_IMO_6MHZ, 0x49000109
 5035              	.set CYREG_FLSHID_CUST_TABLES_IMO_12MHZ, 0x4900010a
 5036              	.set CYREG_FLSHID_CUST_TABLES_IMO_24MHZ, 0x4900010b
 5037              	.set CYREG_FLSHID_CUST_TABLES_IMO_67MHZ, 0x4900010c
 5038              	.set CYREG_FLSHID_CUST_TABLES_IMO_80MHZ, 0x4900010d
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 184


 5039              	.set CYREG_FLSHID_CUST_TABLES_IMO_92MHZ, 0x4900010e
 5040              	.set CYREG_FLSHID_CUST_TABLES_IMO_USB, 0x4900010f
 5041              	.set CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS, 0x49000110
 5042              	.set CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS, 0x49000111
 5043              	.set CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS, 0x49000112
 5044              	.set CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS, 0x49000113
 5045              	.set CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS, 0x49000114
 5046              	.set CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS, 0x49000115
 5047              	.set CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS, 0x49000116
 5048              	.set CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS, 0x49000117
 5049              	.set CYREG_FLSHID_CUST_TABLES_DEC_M1, 0x49000118
 5050              	.set CYREG_FLSHID_CUST_TABLES_DEC_M2, 0x49000119
 5051              	.set CYREG_FLSHID_CUST_TABLES_DEC_M3, 0x4900011a
 5052              	.set CYREG_FLSHID_CUST_TABLES_DEC_M4, 0x4900011b
 5053              	.set CYREG_FLSHID_CUST_TABLES_DEC_M5, 0x4900011c
 5054              	.set CYREG_FLSHID_CUST_TABLES_DEC_M6, 0x4900011d
 5055              	.set CYREG_FLSHID_CUST_TABLES_DEC_M7, 0x4900011e
 5056              	.set CYREG_FLSHID_CUST_TABLES_DEC_M8, 0x4900011f
 5057              	.set CYREG_FLSHID_CUST_TABLES_DAC0_M1, 0x49000120
 5058              	.set CYREG_FLSHID_CUST_TABLES_DAC0_M2, 0x49000121
 5059              	.set CYREG_FLSHID_CUST_TABLES_DAC0_M3, 0x49000122
 5060              	.set CYREG_FLSHID_CUST_TABLES_DAC0_M4, 0x49000123
 5061              	.set CYREG_FLSHID_CUST_TABLES_DAC0_M5, 0x49000124
 5062              	.set CYREG_FLSHID_CUST_TABLES_DAC0_M6, 0x49000125
 5063              	.set CYREG_FLSHID_CUST_TABLES_DAC0_M7, 0x49000126
 5064              	.set CYREG_FLSHID_CUST_TABLES_DAC0_M8, 0x49000127
 5065              	.set CYREG_FLSHID_CUST_TABLES_DAC2_M1, 0x49000128
 5066              	.set CYREG_FLSHID_CUST_TABLES_DAC2_M2, 0x49000129
 5067              	.set CYREG_FLSHID_CUST_TABLES_DAC2_M3, 0x4900012a
 5068              	.set CYREG_FLSHID_CUST_TABLES_DAC2_M4, 0x4900012b
 5069              	.set CYREG_FLSHID_CUST_TABLES_DAC2_M5, 0x4900012c
 5070              	.set CYREG_FLSHID_CUST_TABLES_DAC2_M6, 0x4900012d
 5071              	.set CYREG_FLSHID_CUST_TABLES_DAC2_M7, 0x4900012e
 5072              	.set CYREG_FLSHID_CUST_TABLES_DAC2_M8, 0x4900012f
 5073              	.set CYREG_FLSHID_CUST_TABLES_DAC1_M1, 0x49000130
 5074              	.set CYREG_FLSHID_CUST_TABLES_DAC1_M2, 0x49000131
 5075              	.set CYREG_FLSHID_CUST_TABLES_DAC1_M3, 0x49000132
 5076              	.set CYREG_FLSHID_CUST_TABLES_DAC1_M4, 0x49000133
 5077              	.set CYREG_FLSHID_CUST_TABLES_DAC1_M5, 0x49000134
 5078              	.set CYREG_FLSHID_CUST_TABLES_DAC1_M6, 0x49000135
 5079              	.set CYREG_FLSHID_CUST_TABLES_DAC1_M7, 0x49000136
 5080              	.set CYREG_FLSHID_CUST_TABLES_DAC1_M8, 0x49000137
 5081              	.set CYREG_FLSHID_CUST_TABLES_DAC3_M1, 0x49000138
 5082              	.set CYREG_FLSHID_CUST_TABLES_DAC3_M2, 0x49000139
 5083              	.set CYREG_FLSHID_CUST_TABLES_DAC3_M3, 0x4900013a
 5084              	.set CYREG_FLSHID_CUST_TABLES_DAC3_M4, 0x4900013b
 5085              	.set CYREG_FLSHID_CUST_TABLES_DAC3_M5, 0x4900013c
 5086              	.set CYREG_FLSHID_CUST_TABLES_DAC3_M6, 0x4900013d
 5087              	.set CYREG_FLSHID_CUST_TABLES_DAC3_M7, 0x4900013e
 5088              	.set CYREG_FLSHID_CUST_TABLES_DAC3_M8, 0x4900013f
 5089              	.set CYDEV_FLSHID_MFG_CFG_BASE, 0x49000180
 5090              	.set CYDEV_FLSHID_MFG_CFG_SIZE, 0x00000080
 5091              	.set CYREG_FLSHID_MFG_CFG_IMO_TR1, 0x49000188
 5092              	.set CYREG_FLSHID_MFG_CFG_CMP0_TR0, 0x490001ac
 5093              	.set CYREG_FLSHID_MFG_CFG_CMP1_TR0, 0x490001ae
 5094              	.set CYREG_FLSHID_MFG_CFG_CMP2_TR0, 0x490001b0
 5095              	.set CYREG_FLSHID_MFG_CFG_CMP3_TR0, 0x490001b2
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 185


 5096              	.set CYREG_FLSHID_MFG_CFG_CMP0_TR1, 0x490001b4
 5097              	.set CYREG_FLSHID_MFG_CFG_CMP1_TR1, 0x490001b6
 5098              	.set CYREG_FLSHID_MFG_CFG_CMP2_TR1, 0x490001b8
 5099              	.set CYREG_FLSHID_MFG_CFG_CMP3_TR1, 0x490001ba
 5100              	.set CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM, 0x490001ce
 5101              	.set CYDEV_EXTMEM_BASE, 0x60000000
 5102              	.set CYDEV_EXTMEM_SIZE, 0x00800000
 5103              	.set CYREG_EXTMEM_DATA_MBASE, 0x60000000
 5104              	.set CYREG_EXTMEM_DATA_MSIZE, 0x00800000
 5105              	.set CYDEV_ITM_BASE, 0xe0000000
 5106              	.set CYDEV_ITM_SIZE, 0x00001000
 5107              	.set CYREG_ITM_TRACE_EN, 0xe0000e00
 5108              	.set CYREG_ITM_TRACE_PRIVILEGE, 0xe0000e40
 5109              	.set CYREG_ITM_TRACE_CTRL, 0xe0000e80
 5110              	.set CYREG_ITM_LOCK_ACCESS, 0xe0000fb0
 5111              	.set CYREG_ITM_LOCK_STATUS, 0xe0000fb4
 5112              	.set CYREG_ITM_PID4, 0xe0000fd0
 5113              	.set CYREG_ITM_PID5, 0xe0000fd4
 5114              	.set CYREG_ITM_PID6, 0xe0000fd8
 5115              	.set CYREG_ITM_PID7, 0xe0000fdc
 5116              	.set CYREG_ITM_PID0, 0xe0000fe0
 5117              	.set CYREG_ITM_PID1, 0xe0000fe4
 5118              	.set CYREG_ITM_PID2, 0xe0000fe8
 5119              	.set CYREG_ITM_PID3, 0xe0000fec
 5120              	.set CYREG_ITM_CID0, 0xe0000ff0
 5121              	.set CYREG_ITM_CID1, 0xe0000ff4
 5122              	.set CYREG_ITM_CID2, 0xe0000ff8
 5123              	.set CYREG_ITM_CID3, 0xe0000ffc
 5124              	.set CYDEV_DWT_BASE, 0xe0001000
 5125              	.set CYDEV_DWT_SIZE, 0x0000005c
 5126              	.set CYREG_DWT_CTRL, 0xe0001000
 5127              	.set CYREG_DWT_CYCLE_COUNT, 0xe0001004
 5128              	.set CYREG_DWT_CPI_COUNT, 0xe0001008
 5129              	.set CYREG_DWT_EXC_OVHD_COUNT, 0xe000100c
 5130              	.set CYREG_DWT_SLEEP_COUNT, 0xe0001010
 5131              	.set CYREG_DWT_LSU_COUNT, 0xe0001014
 5132              	.set CYREG_DWT_FOLD_COUNT, 0xe0001018
 5133              	.set CYREG_DWT_PC_SAMPLE, 0xe000101c
 5134              	.set CYREG_DWT_COMP_0, 0xe0001020
 5135              	.set CYREG_DWT_MASK_0, 0xe0001024
 5136              	.set CYREG_DWT_FUNCTION_0, 0xe0001028
 5137              	.set CYREG_DWT_COMP_1, 0xe0001030
 5138              	.set CYREG_DWT_MASK_1, 0xe0001034
 5139              	.set CYREG_DWT_FUNCTION_1, 0xe0001038
 5140              	.set CYREG_DWT_COMP_2, 0xe0001040
 5141              	.set CYREG_DWT_MASK_2, 0xe0001044
 5142              	.set CYREG_DWT_FUNCTION_2, 0xe0001048
 5143              	.set CYREG_DWT_COMP_3, 0xe0001050
 5144              	.set CYREG_DWT_MASK_3, 0xe0001054
 5145              	.set CYREG_DWT_FUNCTION_3, 0xe0001058
 5146              	.set CYDEV_FPB_BASE, 0xe0002000
 5147              	.set CYDEV_FPB_SIZE, 0x00001000
 5148              	.set CYREG_FPB_CTRL, 0xe0002000
 5149              	.set CYREG_FPB_REMAP, 0xe0002004
 5150              	.set CYREG_FPB_FP_COMP_0, 0xe0002008
 5151              	.set CYREG_FPB_FP_COMP_1, 0xe000200c
 5152              	.set CYREG_FPB_FP_COMP_2, 0xe0002010
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 186


 5153              	.set CYREG_FPB_FP_COMP_3, 0xe0002014
 5154              	.set CYREG_FPB_FP_COMP_4, 0xe0002018
 5155              	.set CYREG_FPB_FP_COMP_5, 0xe000201c
 5156              	.set CYREG_FPB_FP_COMP_6, 0xe0002020
 5157              	.set CYREG_FPB_FP_COMP_7, 0xe0002024
 5158              	.set CYREG_FPB_PID4, 0xe0002fd0
 5159              	.set CYREG_FPB_PID5, 0xe0002fd4
 5160              	.set CYREG_FPB_PID6, 0xe0002fd8
 5161              	.set CYREG_FPB_PID7, 0xe0002fdc
 5162              	.set CYREG_FPB_PID0, 0xe0002fe0
 5163              	.set CYREG_FPB_PID1, 0xe0002fe4
 5164              	.set CYREG_FPB_PID2, 0xe0002fe8
 5165              	.set CYREG_FPB_PID3, 0xe0002fec
 5166              	.set CYREG_FPB_CID0, 0xe0002ff0
 5167              	.set CYREG_FPB_CID1, 0xe0002ff4
 5168              	.set CYREG_FPB_CID2, 0xe0002ff8
 5169              	.set CYREG_FPB_CID3, 0xe0002ffc
 5170              	.set CYDEV_NVIC_BASE, 0xe000e000
 5171              	.set CYDEV_NVIC_SIZE, 0x00000d3c
 5172              	.set CYREG_NVIC_INT_CTL_TYPE, 0xe000e004
 5173              	.set CYREG_NVIC_SYSTICK_CTL, 0xe000e010
 5174              	.set CYREG_NVIC_SYSTICK_RELOAD, 0xe000e014
 5175              	.set CYREG_NVIC_SYSTICK_CURRENT, 0xe000e018
 5176              	.set CYREG_NVIC_SYSTICK_CAL, 0xe000e01c
 5177              	.set CYREG_NVIC_SETENA0, 0xe000e100
 5178              	.set CYREG_NVIC_CLRENA0, 0xe000e180
 5179              	.set CYREG_NVIC_SETPEND0, 0xe000e200
 5180              	.set CYREG_NVIC_CLRPEND0, 0xe000e280
 5181              	.set CYREG_NVIC_ACTIVE0, 0xe000e300
 5182              	.set CYREG_NVIC_PRI_0, 0xe000e400
 5183              	.set CYREG_NVIC_PRI_1, 0xe000e401
 5184              	.set CYREG_NVIC_PRI_2, 0xe000e402
 5185              	.set CYREG_NVIC_PRI_3, 0xe000e403
 5186              	.set CYREG_NVIC_PRI_4, 0xe000e404
 5187              	.set CYREG_NVIC_PRI_5, 0xe000e405
 5188              	.set CYREG_NVIC_PRI_6, 0xe000e406
 5189              	.set CYREG_NVIC_PRI_7, 0xe000e407
 5190              	.set CYREG_NVIC_PRI_8, 0xe000e408
 5191              	.set CYREG_NVIC_PRI_9, 0xe000e409
 5192              	.set CYREG_NVIC_PRI_10, 0xe000e40a
 5193              	.set CYREG_NVIC_PRI_11, 0xe000e40b
 5194              	.set CYREG_NVIC_PRI_12, 0xe000e40c
 5195              	.set CYREG_NVIC_PRI_13, 0xe000e40d
 5196              	.set CYREG_NVIC_PRI_14, 0xe000e40e
 5197              	.set CYREG_NVIC_PRI_15, 0xe000e40f
 5198              	.set CYREG_NVIC_PRI_16, 0xe000e410
 5199              	.set CYREG_NVIC_PRI_17, 0xe000e411
 5200              	.set CYREG_NVIC_PRI_18, 0xe000e412
 5201              	.set CYREG_NVIC_PRI_19, 0xe000e413
 5202              	.set CYREG_NVIC_PRI_20, 0xe000e414
 5203              	.set CYREG_NVIC_PRI_21, 0xe000e415
 5204              	.set CYREG_NVIC_PRI_22, 0xe000e416
 5205              	.set CYREG_NVIC_PRI_23, 0xe000e417
 5206              	.set CYREG_NVIC_PRI_24, 0xe000e418
 5207              	.set CYREG_NVIC_PRI_25, 0xe000e419
 5208              	.set CYREG_NVIC_PRI_26, 0xe000e41a
 5209              	.set CYREG_NVIC_PRI_27, 0xe000e41b
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 187


 5210              	.set CYREG_NVIC_PRI_28, 0xe000e41c
 5211              	.set CYREG_NVIC_PRI_29, 0xe000e41d
 5212              	.set CYREG_NVIC_PRI_30, 0xe000e41e
 5213              	.set CYREG_NVIC_PRI_31, 0xe000e41f
 5214              	.set CYREG_NVIC_CPUID_BASE, 0xe000ed00
 5215              	.set CYREG_NVIC_INTR_CTRL_STATE, 0xe000ed04
 5216              	.set CYREG_NVIC_VECT_OFFSET, 0xe000ed08
 5217              	.set CYREG_NVIC_APPLN_INTR, 0xe000ed0c
 5218              	.set CYREG_NVIC_SYSTEM_CONTROL, 0xe000ed10
 5219              	.set CYREG_NVIC_CFG_CONTROL, 0xe000ed14
 5220              	.set CYREG_NVIC_SYS_PRIO_HANDLER_4_7, 0xe000ed18
 5221              	.set CYREG_NVIC_SYS_PRIO_HANDLER_8_11, 0xe000ed1c
 5222              	.set CYREG_NVIC_SYS_PRIO_HANDLER_12_15, 0xe000ed20
 5223              	.set CYREG_NVIC_SYS_HANDLER_CSR, 0xe000ed24
 5224              	.set CYREG_NVIC_MEMMAN_FAULT_STATUS, 0xe000ed28
 5225              	.set CYREG_NVIC_BUS_FAULT_STATUS, 0xe000ed29
 5226              	.set CYREG_NVIC_USAGE_FAULT_STATUS, 0xe000ed2a
 5227              	.set CYREG_NVIC_HARD_FAULT_STATUS, 0xe000ed2c
 5228              	.set CYREG_NVIC_DEBUG_FAULT_STATUS, 0xe000ed30
 5229              	.set CYREG_NVIC_MEMMAN_FAULT_ADD, 0xe000ed34
 5230              	.set CYREG_NVIC_BUS_FAULT_ADD, 0xe000ed38
 5231              	.set CYDEV_CORE_DBG_BASE, 0xe000edf0
 5232              	.set CYDEV_CORE_DBG_SIZE, 0x00000010
 5233              	.set CYREG_CORE_DBG_DBG_HLT_CS, 0xe000edf0
 5234              	.set CYREG_CORE_DBG_DBG_REG_SEL, 0xe000edf4
 5235              	.set CYREG_CORE_DBG_DBG_REG_DATA, 0xe000edf8
 5236              	.set CYREG_CORE_DBG_EXC_MON_CTL, 0xe000edfc
 5237              	.set CYDEV_TPIU_BASE, 0xe0040000
 5238              	.set CYDEV_TPIU_SIZE, 0x00001000
 5239              	.set CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ, 0xe0040000
 5240              	.set CYREG_TPIU_CURRENT_SYNC_PRT_SZ, 0xe0040004
 5241              	.set CYREG_TPIU_ASYNC_CLK_PRESCALER, 0xe0040010
 5242              	.set CYREG_TPIU_PROTOCOL, 0xe00400f0
 5243              	.set CYREG_TPIU_FORM_FLUSH_STAT, 0xe0040300
 5244              	.set CYREG_TPIU_FORM_FLUSH_CTRL, 0xe0040304
 5245              	.set CYREG_TPIU_TRIGGER, 0xe0040ee8
 5246              	.set CYREG_TPIU_ITETMDATA, 0xe0040eec
 5247              	.set CYREG_TPIU_ITATBCTR2, 0xe0040ef0
 5248              	.set CYREG_TPIU_ITATBCTR0, 0xe0040ef8
 5249              	.set CYREG_TPIU_ITITMDATA, 0xe0040efc
 5250              	.set CYREG_TPIU_ITCTRL, 0xe0040f00
 5251              	.set CYREG_TPIU_DEVID, 0xe0040fc8
 5252              	.set CYREG_TPIU_DEVTYPE, 0xe0040fcc
 5253              	.set CYREG_TPIU_PID4, 0xe0040fd0
 5254              	.set CYREG_TPIU_PID5, 0xe0040fd4
 5255              	.set CYREG_TPIU_PID6, 0xe0040fd8
 5256              	.set CYREG_TPIU_PID7, 0xe0040fdc
 5257              	.set CYREG_TPIU_PID0, 0xe0040fe0
 5258              	.set CYREG_TPIU_PID1, 0xe0040fe4
 5259              	.set CYREG_TPIU_PID2, 0xe0040fe8
 5260              	.set CYREG_TPIU_PID3, 0xe0040fec
 5261              	.set CYREG_TPIU_CID0, 0xe0040ff0
 5262              	.set CYREG_TPIU_CID1, 0xe0040ff4
 5263              	.set CYREG_TPIU_CID2, 0xe0040ff8
 5264              	.set CYREG_TPIU_CID3, 0xe0040ffc
 5265              	.set CYDEV_ETM_BASE, 0xe0041000
 5266              	.set CYDEV_ETM_SIZE, 0x00001000
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 188


 5267              	.set CYREG_ETM_CTL, 0xe0041000
 5268              	.set CYREG_ETM_CFG_CODE, 0xe0041004
 5269              	.set CYREG_ETM_TRIG_EVENT, 0xe0041008
 5270              	.set CYREG_ETM_STATUS, 0xe0041010
 5271              	.set CYREG_ETM_SYS_CFG, 0xe0041014
 5272              	.set CYREG_ETM_TRACE_ENB_EVENT, 0xe0041020
 5273              	.set CYREG_ETM_TRACE_EN_CTRL1, 0xe0041024
 5274              	.set CYREG_ETM_FIFOFULL_LEVEL, 0xe004102c
 5275              	.set CYREG_ETM_SYNC_FREQ, 0xe00411e0
 5276              	.set CYREG_ETM_ETM_ID, 0xe00411e4
 5277              	.set CYREG_ETM_CFG_CODE_EXT, 0xe00411e8
 5278              	.set CYREG_ETM_TR_SS_EMBICE_CTRL, 0xe00411f0
 5279              	.set CYREG_ETM_CS_TRACE_ID, 0xe0041200
 5280              	.set CYREG_ETM_OS_LOCK_ACCESS, 0xe0041300
 5281              	.set CYREG_ETM_OS_LOCK_STATUS, 0xe0041304
 5282              	.set CYREG_ETM_PDSR, 0xe0041314
 5283              	.set CYREG_ETM_ITMISCIN, 0xe0041ee0
 5284              	.set CYREG_ETM_ITTRIGOUT, 0xe0041ee8
 5285              	.set CYREG_ETM_ITATBCTR2, 0xe0041ef0
 5286              	.set CYREG_ETM_ITATBCTR0, 0xe0041ef8
 5287              	.set CYREG_ETM_INT_MODE_CTRL, 0xe0041f00
 5288              	.set CYREG_ETM_CLM_TAG_SET, 0xe0041fa0
 5289              	.set CYREG_ETM_CLM_TAG_CLR, 0xe0041fa4
 5290              	.set CYREG_ETM_LOCK_ACCESS, 0xe0041fb0
 5291              	.set CYREG_ETM_LOCK_STATUS, 0xe0041fb4
 5292              	.set CYREG_ETM_AUTH_STATUS, 0xe0041fb8
 5293              	.set CYREG_ETM_DEV_TYPE, 0xe0041fcc
 5294              	.set CYREG_ETM_PID4, 0xe0041fd0
 5295              	.set CYREG_ETM_PID5, 0xe0041fd4
 5296              	.set CYREG_ETM_PID6, 0xe0041fd8
 5297              	.set CYREG_ETM_PID7, 0xe0041fdc
 5298              	.set CYREG_ETM_PID0, 0xe0041fe0
 5299              	.set CYREG_ETM_PID1, 0xe0041fe4
 5300              	.set CYREG_ETM_PID2, 0xe0041fe8
 5301              	.set CYREG_ETM_PID3, 0xe0041fec
 5302              	.set CYREG_ETM_CID0, 0xe0041ff0
 5303              	.set CYREG_ETM_CID1, 0xe0041ff4
 5304              	.set CYREG_ETM_CID2, 0xe0041ff8
 5305              	.set CYREG_ETM_CID3, 0xe0041ffc
 5306              	.set CYDEV_ROM_TABLE_BASE, 0xe00ff000
 5307              	.set CYDEV_ROM_TABLE_SIZE, 0x00001000
 5308              	.set CYREG_ROM_TABLE_NVIC, 0xe00ff000
 5309              	.set CYREG_ROM_TABLE_DWT, 0xe00ff004
 5310              	.set CYREG_ROM_TABLE_FPB, 0xe00ff008
 5311              	.set CYREG_ROM_TABLE_ITM, 0xe00ff00c
 5312              	.set CYREG_ROM_TABLE_TPIU, 0xe00ff010
 5313              	.set CYREG_ROM_TABLE_ETM, 0xe00ff014
 5314              	.set CYREG_ROM_TABLE_END, 0xe00ff018
 5315              	.set CYREG_ROM_TABLE_MEMTYPE, 0xe00fffcc
 5316              	.set CYREG_ROM_TABLE_PID4, 0xe00fffd0
 5317              	.set CYREG_ROM_TABLE_PID5, 0xe00fffd4
 5318              	.set CYREG_ROM_TABLE_PID6, 0xe00fffd8
 5319              	.set CYREG_ROM_TABLE_PID7, 0xe00fffdc
 5320              	.set CYREG_ROM_TABLE_PID0, 0xe00fffe0
 5321              	.set CYREG_ROM_TABLE_PID1, 0xe00fffe4
 5322              	.set CYREG_ROM_TABLE_PID2, 0xe00fffe8
 5323              	.set CYREG_ROM_TABLE_PID3, 0xe00fffec
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 189


 5324              	.set CYREG_ROM_TABLE_CID0, 0xe00ffff0
 5325              	.set CYREG_ROM_TABLE_CID1, 0xe00ffff4
 5326              	.set CYREG_ROM_TABLE_CID2, 0xe00ffff8
 5327              	.set CYREG_ROM_TABLE_CID3, 0xe00ffffc
 5328              	.set CYDEV_FLS_SIZE, CYDEV_FLASH_SIZE
 5329              	.set CYDEV_ECC_BASE, CYDEV_FLSECC_BASE
 5330              	.set CYDEV_FLS_SECTOR_SIZE, 0x00010000
 5331              	.set CYDEV_FLS_ROW_SIZE, 0x00000100
 5332              	.set CYDEV_ECC_SECTOR_SIZE, 0x00002000
 5333              	.set CYDEV_ECC_ROW_SIZE, 0x00000020
 5334              	.set CYDEV_EEPROM_SECTOR_SIZE, 0x00000400
 5335              	.set CYDEV_EEPROM_ROW_SIZE, 0x00000010
 5336              	.set CYDEV_PERIPH_BASE, CYDEV_CLKDIST_BASE
 5337              	.set CYCLK_LD_DISABLE, 0x00000004
 5338              	.set CYCLK_LD_SYNC_EN, 0x00000002
 5339              	.set CYCLK_LD_LOAD, 0x00000001
 5340              	.set CYCLK_PIPE, 0x00000080
 5341              	.set CYCLK_SSS, 0x00000040
 5342              	.set CYCLK_EARLY, 0x00000020
 5343              	.set CYCLK_DUTY, 0x00000010
 5344              	.set CYCLK_SYNC, 0x00000008
 5345              	.set CYCLK_SRC_SEL_CLK_SYNC_D, 0
 5346              	.set CYCLK_SRC_SEL_SYNC_DIG, 0
 5347              	.set CYCLK_SRC_SEL_IMO, 1
 5348              	.set CYCLK_SRC_SEL_XTAL_MHZ, 2
 5349              	.set CYCLK_SRC_SEL_XTALM, 2
 5350              	.set CYCLK_SRC_SEL_ILO, 3
 5351              	.set CYCLK_SRC_SEL_PLL, 4
 5352              	.set CYCLK_SRC_SEL_XTAL_KHZ, 5
 5353              	.set CYCLK_SRC_SEL_XTALK, 5
 5354              	.set CYCLK_SRC_SEL_DSI_G, 6
 5355              	.set CYCLK_SRC_SEL_DSI_D, 7
 5356              	.set CYCLK_SRC_SEL_CLK_SYNC_A, 0
 5357              	.set CYCLK_SRC_SEL_DSI_A, 7
  21              	
  22              	/* CDC */
  23              	.set CDC_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
  24              	.set CDC_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
  25              	.set CDC_arb_int__INTC_MASK, 0x400000
  26              	.set CDC_arb_int__INTC_NUMBER, 22
  27              	.set CDC_arb_int__INTC_PRIOR_NUM, 7
  28              	.set CDC_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22
  29              	.set CDC_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
  30              	.set CDC_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
  31              	.set CDC_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
  32              	.set CDC_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
  33              	.set CDC_bus_reset__INTC_MASK, 0x800000
  34              	.set CDC_bus_reset__INTC_NUMBER, 23
  35              	.set CDC_bus_reset__INTC_PRIOR_NUM, 7
  36              	.set CDC_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23
  37              	.set CDC_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
  38              	.set CDC_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
  39              	.set CDC_Dm__0__INTTYPE, CYREG_PICU15_INTTYPE7
  40              	.set CDC_Dm__0__MASK, 0x80
  41              	.set CDC_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1
  42              	.set CDC_Dm__0__PORT, 15
  43              	.set CDC_Dm__0__SHIFT, 7
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 190


  44              	.set CDC_Dm__AG, CYREG_PRT15_AG
  45              	.set CDC_Dm__AMUX, CYREG_PRT15_AMUX
  46              	.set CDC_Dm__BIE, CYREG_PRT15_BIE
  47              	.set CDC_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK
  48              	.set CDC_Dm__BYP, CYREG_PRT15_BYP
  49              	.set CDC_Dm__CTL, CYREG_PRT15_CTL
  50              	.set CDC_Dm__DM0, CYREG_PRT15_DM0
  51              	.set CDC_Dm__DM1, CYREG_PRT15_DM1
  52              	.set CDC_Dm__DM2, CYREG_PRT15_DM2
  53              	.set CDC_Dm__DR, CYREG_PRT15_DR
  54              	.set CDC_Dm__INP_DIS, CYREG_PRT15_INP_DIS
  55              	.set CDC_Dm__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE
  56              	.set CDC_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
  57              	.set CDC_Dm__LCD_EN, CYREG_PRT15_LCD_EN
  58              	.set CDC_Dm__MASK, 0x80
  59              	.set CDC_Dm__PORT, 15
  60              	.set CDC_Dm__PRT, CYREG_PRT15_PRT
  61              	.set CDC_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
  62              	.set CDC_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
  63              	.set CDC_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
  64              	.set CDC_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
  65              	.set CDC_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
  66              	.set CDC_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
  67              	.set CDC_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
  68              	.set CDC_Dm__PS, CYREG_PRT15_PS
  69              	.set CDC_Dm__SHIFT, 7
  70              	.set CDC_Dm__SLW, CYREG_PRT15_SLW
  71              	.set CDC_Dp__0__INTTYPE, CYREG_PICU15_INTTYPE6
  72              	.set CDC_Dp__0__MASK, 0x40
  73              	.set CDC_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0
  74              	.set CDC_Dp__0__PORT, 15
  75              	.set CDC_Dp__0__SHIFT, 6
  76              	.set CDC_Dp__AG, CYREG_PRT15_AG
  77              	.set CDC_Dp__AMUX, CYREG_PRT15_AMUX
  78              	.set CDC_Dp__BIE, CYREG_PRT15_BIE
  79              	.set CDC_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK
  80              	.set CDC_Dp__BYP, CYREG_PRT15_BYP
  81              	.set CDC_Dp__CTL, CYREG_PRT15_CTL
  82              	.set CDC_Dp__DM0, CYREG_PRT15_DM0
  83              	.set CDC_Dp__DM1, CYREG_PRT15_DM1
  84              	.set CDC_Dp__DM2, CYREG_PRT15_DM2
  85              	.set CDC_Dp__DR, CYREG_PRT15_DR
  86              	.set CDC_Dp__INP_DIS, CYREG_PRT15_INP_DIS
  87              	.set CDC_Dp__INTSTAT, CYREG_PICU15_INTSTAT
  88              	.set CDC_Dp__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE
  89              	.set CDC_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
  90              	.set CDC_Dp__LCD_EN, CYREG_PRT15_LCD_EN
  91              	.set CDC_Dp__MASK, 0x40
  92              	.set CDC_Dp__PORT, 15
  93              	.set CDC_Dp__PRT, CYREG_PRT15_PRT
  94              	.set CDC_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
  95              	.set CDC_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
  96              	.set CDC_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
  97              	.set CDC_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
  98              	.set CDC_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
  99              	.set CDC_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
 100              	.set CDC_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 191


 101              	.set CDC_Dp__PS, CYREG_PRT15_PS
 102              	.set CDC_Dp__SHIFT, 6
 103              	.set CDC_Dp__SLW, CYREG_PRT15_SLW
 104              	.set CDC_Dp__SNAP, CYREG_PICU_15_SNAP_15
 105              	.set CDC_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
 106              	.set CDC_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
 107              	.set CDC_dp_int__INTC_MASK, 0x1000
 108              	.set CDC_dp_int__INTC_NUMBER, 12
 109              	.set CDC_dp_int__INTC_PRIOR_NUM, 7
 110              	.set CDC_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12
 111              	.set CDC_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
 112              	.set CDC_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 113              	.set CDC_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
 114              	.set CDC_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
 115              	.set CDC_ep_0__INTC_MASK, 0x1000000
 116              	.set CDC_ep_0__INTC_NUMBER, 24
 117              	.set CDC_ep_0__INTC_PRIOR_NUM, 7
 118              	.set CDC_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24
 119              	.set CDC_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
 120              	.set CDC_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 121              	.set CDC_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
 122              	.set CDC_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
 123              	.set CDC_ep_1__INTC_MASK, 0x01
 124              	.set CDC_ep_1__INTC_NUMBER, 0
 125              	.set CDC_ep_1__INTC_PRIOR_NUM, 7
 126              	.set CDC_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_0
 127              	.set CDC_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
 128              	.set CDC_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 129              	.set CDC_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
 130              	.set CDC_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
 131              	.set CDC_ep_2__INTC_MASK, 0x02
 132              	.set CDC_ep_2__INTC_NUMBER, 1
 133              	.set CDC_ep_2__INTC_PRIOR_NUM, 7
 134              	.set CDC_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_1
 135              	.set CDC_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
 136              	.set CDC_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 137              	.set CDC_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
 138              	.set CDC_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
 139              	.set CDC_ep_3__INTC_MASK, 0x04
 140              	.set CDC_ep_3__INTC_NUMBER, 2
 141              	.set CDC_ep_3__INTC_PRIOR_NUM, 7
 142              	.set CDC_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_2
 143              	.set CDC_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
 144              	.set CDC_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 145              	.set CDC_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
 146              	.set CDC_sof_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
 147              	.set CDC_sof_int__INTC_MASK, 0x200000
 148              	.set CDC_sof_int__INTC_NUMBER, 21
 149              	.set CDC_sof_int__INTC_PRIOR_NUM, 7
 150              	.set CDC_sof_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_21
 151              	.set CDC_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
 152              	.set CDC_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 153              	.set CDC_USB__ARB_CFG, CYREG_USB_ARB_CFG
 154              	.set CDC_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG
 155              	.set CDC_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN
 156              	.set CDC_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR
 157              	.set CDC_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 192


 158              	.set CDC_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN
 159              	.set CDC_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR
 160              	.set CDC_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG
 161              	.set CDC_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN
 162              	.set CDC_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR
 163              	.set CDC_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG
 164              	.set CDC_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN
 165              	.set CDC_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR
 166              	.set CDC_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG
 167              	.set CDC_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN
 168              	.set CDC_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR
 169              	.set CDC_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG
 170              	.set CDC_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN
 171              	.set CDC_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR
 172              	.set CDC_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG
 173              	.set CDC_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN
 174              	.set CDC_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR
 175              	.set CDC_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG
 176              	.set CDC_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN
 177              	.set CDC_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR
 178              	.set CDC_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN
 179              	.set CDC_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR
 180              	.set CDC_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR
 181              	.set CDC_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA
 182              	.set CDC_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB
 183              	.set CDC_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA
 184              	.set CDC_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB
 185              	.set CDC_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR
 186              	.set CDC_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA
 187              	.set CDC_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB
 188              	.set CDC_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA
 189              	.set CDC_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB
 190              	.set CDC_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR
 191              	.set CDC_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA
 192              	.set CDC_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB
 193              	.set CDC_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA
 194              	.set CDC_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB
 195              	.set CDC_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR
 196              	.set CDC_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA
 197              	.set CDC_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB
 198              	.set CDC_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA
 199              	.set CDC_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB
 200              	.set CDC_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR
 201              	.set CDC_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA
 202              	.set CDC_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB
 203              	.set CDC_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA
 204              	.set CDC_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB
 205              	.set CDC_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR
 206              	.set CDC_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA
 207              	.set CDC_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB
 208              	.set CDC_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA
 209              	.set CDC_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB
 210              	.set CDC_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR
 211              	.set CDC_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA
 212              	.set CDC_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB
 213              	.set CDC_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA
 214              	.set CDC_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 193


 215              	.set CDC_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR
 216              	.set CDC_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA
 217              	.set CDC_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB
 218              	.set CDC_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA
 219              	.set CDC_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB
 220              	.set CDC_USB__BUF_SIZE, CYREG_USB_BUF_SIZE
 221              	.set CDC_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT
 222              	.set CDC_USB__CR0, CYREG_USB_CR0
 223              	.set CDC_USB__CR1, CYREG_USB_CR1
 224              	.set CDC_USB__CWA, CYREG_USB_CWA
 225              	.set CDC_USB__CWA_MSB, CYREG_USB_CWA_MSB
 226              	.set CDC_USB__DMA_THRES, CYREG_USB_DMA_THRES
 227              	.set CDC_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB
 228              	.set CDC_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG
 229              	.set CDC_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE
 230              	.set CDC_USB__EP_TYPE, CYREG_USB_EP_TYPE
 231              	.set CDC_USB__EP0_CNT, CYREG_USB_EP0_CNT
 232              	.set CDC_USB__EP0_CR, CYREG_USB_EP0_CR
 233              	.set CDC_USB__EP0_DR0, CYREG_USB_EP0_DR0
 234              	.set CDC_USB__EP0_DR1, CYREG_USB_EP0_DR1
 235              	.set CDC_USB__EP0_DR2, CYREG_USB_EP0_DR2
 236              	.set CDC_USB__EP0_DR3, CYREG_USB_EP0_DR3
 237              	.set CDC_USB__EP0_DR4, CYREG_USB_EP0_DR4
 238              	.set CDC_USB__EP0_DR5, CYREG_USB_EP0_DR5
 239              	.set CDC_USB__EP0_DR6, CYREG_USB_EP0_DR6
 240              	.set CDC_USB__EP0_DR7, CYREG_USB_EP0_DR7
 241              	.set CDC_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE
 242              	.set CDC_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5
 243              	.set CDC_USB__PM_ACT_MSK, 0x01
 244              	.set CDC_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5
 245              	.set CDC_USB__PM_STBY_MSK, 0x01
 246              	.set CDC_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN
 247              	.set CDC_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR
 248              	.set CDC_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0
 249              	.set CDC_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1
 250              	.set CDC_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0
 251              	.set CDC_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0
 252              	.set CDC_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1
 253              	.set CDC_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0
 254              	.set CDC_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0
 255              	.set CDC_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1
 256              	.set CDC_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0
 257              	.set CDC_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0
 258              	.set CDC_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1
 259              	.set CDC_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0
 260              	.set CDC_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0
 261              	.set CDC_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1
 262              	.set CDC_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0
 263              	.set CDC_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0
 264              	.set CDC_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1
 265              	.set CDC_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0
 266              	.set CDC_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0
 267              	.set CDC_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1
 268              	.set CDC_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0
 269              	.set CDC_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0
 270              	.set CDC_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1
 271              	.set CDC_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 194


 272              	.set CDC_USB__SOF0, CYREG_USB_SOF0
 273              	.set CDC_USB__SOF1, CYREG_USB_SOF1
 274              	.set CDC_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN
 275              	.set CDC_USB__USBIO_CR0, CYREG_USB_USBIO_CR0
 276              	.set CDC_USB__USBIO_CR1, CYREG_USB_USBIO_CR1
 277              	
 278              	/* I2C_1 */
 279              	.set I2C_1_I2C_FF__ADR, CYREG_I2C_ADR
 280              	.set I2C_1_I2C_FF__CFG, CYREG_I2C_CFG
 281              	.set I2C_1_I2C_FF__CLK_DIV1, CYREG_I2C_CLK_DIV1
 282              	.set I2C_1_I2C_FF__CLK_DIV2, CYREG_I2C_CLK_DIV2
 283              	.set I2C_1_I2C_FF__CSR, CYREG_I2C_CSR
 284              	.set I2C_1_I2C_FF__D, CYREG_I2C_D
 285              	.set I2C_1_I2C_FF__MCSR, CYREG_I2C_MCSR
 286              	.set I2C_1_I2C_FF__PM_ACT_CFG, CYREG_PM_ACT_CFG5
 287              	.set I2C_1_I2C_FF__PM_ACT_MSK, 0x04
 288              	.set I2C_1_I2C_FF__PM_STBY_CFG, CYREG_PM_STBY_CFG5
 289              	.set I2C_1_I2C_FF__PM_STBY_MSK, 0x04
 290              	.set I2C_1_I2C_FF__TMOUT_CFG0, CYREG_I2C_TMOUT_CFG0
 291              	.set I2C_1_I2C_FF__TMOUT_CFG1, CYREG_I2C_TMOUT_CFG1
 292              	.set I2C_1_I2C_FF__TMOUT_CSR, CYREG_I2C_TMOUT_CSR
 293              	.set I2C_1_I2C_FF__TMOUT_SR, CYREG_I2C_TMOUT_SR
 294              	.set I2C_1_I2C_FF__XCFG, CYREG_I2C_XCFG
 295              	.set I2C_1_I2C_IRQ__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
 296              	.set I2C_1_I2C_IRQ__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
 297              	.set I2C_1_I2C_IRQ__INTC_MASK, 0x8000
 298              	.set I2C_1_I2C_IRQ__INTC_NUMBER, 15
 299              	.set I2C_1_I2C_IRQ__INTC_PRIOR_NUM, 7
 300              	.set I2C_1_I2C_IRQ__INTC_PRIOR_REG, CYREG_NVIC_PRI_15
 301              	.set I2C_1_I2C_IRQ__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
 302              	.set I2C_1_I2C_IRQ__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 303              	
 304              	/* SCL_1 */
 305              	.set SCL_1__0__INTTYPE, CYREG_PICU12_INTTYPE0
 306              	.set SCL_1__0__MASK, 0x01
 307              	.set SCL_1__0__PC, CYREG_PRT12_PC0
 308              	.set SCL_1__0__PORT, 12
 309              	.set SCL_1__0__SHIFT, 0
 310              	.set SCL_1__AG, CYREG_PRT12_AG
 311              	.set SCL_1__BIE, CYREG_PRT12_BIE
 312              	.set SCL_1__BIT_MASK, CYREG_PRT12_BIT_MASK
 313              	.set SCL_1__BYP, CYREG_PRT12_BYP
 314              	.set SCL_1__DM0, CYREG_PRT12_DM0
 315              	.set SCL_1__DM1, CYREG_PRT12_DM1
 316              	.set SCL_1__DM2, CYREG_PRT12_DM2
 317              	.set SCL_1__DR, CYREG_PRT12_DR
 318              	.set SCL_1__INP_DIS, CYREG_PRT12_INP_DIS
 319              	.set SCL_1__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU12_BASE
 320              	.set SCL_1__MASK, 0x01
 321              	.set SCL_1__PORT, 12
 322              	.set SCL_1__PRT, CYREG_PRT12_PRT
 323              	.set SCL_1__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
 324              	.set SCL_1__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
 325              	.set SCL_1__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
 326              	.set SCL_1__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
 327              	.set SCL_1__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
 328              	.set SCL_1__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 195


 329              	.set SCL_1__PS, CYREG_PRT12_PS
 330              	.set SCL_1__SHIFT, 0
 331              	.set SCL_1__SIO_CFG, CYREG_PRT12_SIO_CFG
 332              	.set SCL_1__SIO_DIFF, CYREG_PRT12_SIO_DIFF
 333              	.set SCL_1__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
 334              	.set SCL_1__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
 335              	.set SCL_1__SLW, CYREG_PRT12_SLW
 336              	
 337              	/* SDA_1 */
 338              	.set SDA_1__0__INTTYPE, CYREG_PICU12_INTTYPE1
 339              	.set SDA_1__0__MASK, 0x02
 340              	.set SDA_1__0__PC, CYREG_PRT12_PC1
 341              	.set SDA_1__0__PORT, 12
 342              	.set SDA_1__0__SHIFT, 1
 343              	.set SDA_1__AG, CYREG_PRT12_AG
 344              	.set SDA_1__BIE, CYREG_PRT12_BIE
 345              	.set SDA_1__BIT_MASK, CYREG_PRT12_BIT_MASK
 346              	.set SDA_1__BYP, CYREG_PRT12_BYP
 347              	.set SDA_1__DM0, CYREG_PRT12_DM0
 348              	.set SDA_1__DM1, CYREG_PRT12_DM1
 349              	.set SDA_1__DM2, CYREG_PRT12_DM2
 350              	.set SDA_1__DR, CYREG_PRT12_DR
 351              	.set SDA_1__INP_DIS, CYREG_PRT12_INP_DIS
 352              	.set SDA_1__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU12_BASE
 353              	.set SDA_1__MASK, 0x02
 354              	.set SDA_1__PORT, 12
 355              	.set SDA_1__PRT, CYREG_PRT12_PRT
 356              	.set SDA_1__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
 357              	.set SDA_1__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
 358              	.set SDA_1__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
 359              	.set SDA_1__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
 360              	.set SDA_1__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
 361              	.set SDA_1__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
 362              	.set SDA_1__PS, CYREG_PRT12_PS
 363              	.set SDA_1__SHIFT, 1
 364              	.set SDA_1__SIO_CFG, CYREG_PRT12_SIO_CFG
 365              	.set SDA_1__SIO_DIFF, CYREG_PRT12_SIO_DIFF
 366              	.set SDA_1__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
 367              	.set SDA_1__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
 368              	.set SDA_1__SLW, CYREG_PRT12_SLW
 369              	
 370              	/* Miscellaneous */
 371              	.set BCLK__BUS_CLK__HZ, 24000000
 372              	.set BCLK__BUS_CLK__KHZ, 24000
 373              	.set BCLK__BUS_CLK__MHZ, 24
 374              	.set CYDEV_CHIP_DIE_LEOPARD, 1
 375              	.set CYDEV_CHIP_DIE_PSOC4A, 24
 376              	.set CYDEV_CHIP_DIE_PSOC5LP, 2
 377              	.set CYDEV_CHIP_DIE_PSOC5TM, 3
 378              	.set CYDEV_CHIP_DIE_TMA4, 4
 379              	.set CYDEV_CHIP_DIE_UNKNOWN, 0
 380              	.set CYDEV_CHIP_FAMILY_FM0P, 5
 381              	.set CYDEV_CHIP_FAMILY_FM3, 6
 382              	.set CYDEV_CHIP_FAMILY_FM4, 7
 383              	.set CYDEV_CHIP_FAMILY_PSOC3, 1
 384              	.set CYDEV_CHIP_FAMILY_PSOC4, 2
 385              	.set CYDEV_CHIP_FAMILY_PSOC5, 3
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 196


 386              	.set CYDEV_CHIP_FAMILY_PSOC6, 4
 387              	.set CYDEV_CHIP_FAMILY_UNKNOWN, 0
 388              	.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5
 389              	.set CYDEV_CHIP_JTAG_ID, 0x2E161069
 390              	.set CYDEV_CHIP_MEMBER_3A, 1
 391              	.set CYDEV_CHIP_MEMBER_4A, 24
 392              	.set CYDEV_CHIP_MEMBER_4AA, 23
 393              	.set CYDEV_CHIP_MEMBER_4AB, 28
 394              	.set CYDEV_CHIP_MEMBER_4AC, 14
 395              	.set CYDEV_CHIP_MEMBER_4D, 18
 396              	.set CYDEV_CHIP_MEMBER_4E, 6
 397              	.set CYDEV_CHIP_MEMBER_4F, 25
 398              	.set CYDEV_CHIP_MEMBER_4G, 4
 399              	.set CYDEV_CHIP_MEMBER_4H, 22
 400              	.set CYDEV_CHIP_MEMBER_4I, 30
 401              	.set CYDEV_CHIP_MEMBER_4J, 19
 402              	.set CYDEV_CHIP_MEMBER_4K, 20
 403              	.set CYDEV_CHIP_MEMBER_4L, 29
 404              	.set CYDEV_CHIP_MEMBER_4M, 27
 405              	.set CYDEV_CHIP_MEMBER_4N, 11
 406              	.set CYDEV_CHIP_MEMBER_4O, 8
 407              	.set CYDEV_CHIP_MEMBER_4P, 26
 408              	.set CYDEV_CHIP_MEMBER_4Q, 15
 409              	.set CYDEV_CHIP_MEMBER_4R, 9
 410              	.set CYDEV_CHIP_MEMBER_4S, 12
 411              	.set CYDEV_CHIP_MEMBER_4T, 10
 412              	.set CYDEV_CHIP_MEMBER_4U, 5
 413              	.set CYDEV_CHIP_MEMBER_4V, 21
 414              	.set CYDEV_CHIP_MEMBER_4W, 13
 415              	.set CYDEV_CHIP_MEMBER_4X, 7
 416              	.set CYDEV_CHIP_MEMBER_4Y, 16
 417              	.set CYDEV_CHIP_MEMBER_4Z, 17
 418              	.set CYDEV_CHIP_MEMBER_5A, 3
 419              	.set CYDEV_CHIP_MEMBER_5B, 2
 420              	.set CYDEV_CHIP_MEMBER_6A, 31
 421              	.set CYDEV_CHIP_MEMBER_FM3, 35
 422              	.set CYDEV_CHIP_MEMBER_FM4, 36
 423              	.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 32
 424              	.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 33
 425              	.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 34
 426              	.set CYDEV_CHIP_MEMBER_UNKNOWN, 0
 427              	.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B
 428              	.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED
 429              	.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT
 430              	.set CYDEV_CHIP_REV_LEOPARD_ES1, 0
 431              	.set CYDEV_CHIP_REV_LEOPARD_ES2, 1
 432              	.set CYDEV_CHIP_REV_LEOPARD_ES3, 3
 433              	.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3
 434              	.set CYDEV_CHIP_REV_PSOC4A_ES0, 17
 435              	.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17
 436              	.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0
 437              	.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0
 438              	.set CYDEV_CHIP_REV_PSOC5TM_ES0, 0
 439              	.set CYDEV_CHIP_REV_PSOC5TM_ES1, 1
 440              	.set CYDEV_CHIP_REV_PSOC5TM_PRODUCTION, 1
 441              	.set CYDEV_CHIP_REV_TMA4_ES, 17
 442              	.set CYDEV_CHIP_REV_TMA4_ES2, 33
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 197


 443              	.set CYDEV_CHIP_REV_TMA4_PRODUCTION, 17
 444              	.set CYDEV_CHIP_REVISION_3A_ES1, 0
 445              	.set CYDEV_CHIP_REVISION_3A_ES2, 1
 446              	.set CYDEV_CHIP_REVISION_3A_ES3, 3
 447              	.set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3
 448              	.set CYDEV_CHIP_REVISION_4A_ES0, 17
 449              	.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17
 450              	.set CYDEV_CHIP_REVISION_4AA_PRODUCTION, 0
 451              	.set CYDEV_CHIP_REVISION_4AB_PRODUCTION, 0
 452              	.set CYDEV_CHIP_REVISION_4AC_PRODUCTION, 0
 453              	.set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0
 454              	.set CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD, 0
 455              	.set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0
 456              	.set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0
 457              	.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA, 0
 458              	.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256K, 0
 459              	.set CYDEV_CHIP_REVISION_4G_ES, 17
 460              	.set CYDEV_CHIP_REVISION_4G_ES2, 33
 461              	.set CYDEV_CHIP_REVISION_4G_PRODUCTION, 17
 462              	.set CYDEV_CHIP_REVISION_4H_PRODUCTION, 0
 463              	.set CYDEV_CHIP_REVISION_4I_PRODUCTION, 0
 464              	.set CYDEV_CHIP_REVISION_4J_PRODUCTION, 0
 465              	.set CYDEV_CHIP_REVISION_4K_PRODUCTION, 0
 466              	.set CYDEV_CHIP_REVISION_4L_PRODUCTION, 0
 467              	.set CYDEV_CHIP_REVISION_4M_PRODUCTION, 0
 468              	.set CYDEV_CHIP_REVISION_4N_PRODUCTION, 0
 469              	.set CYDEV_CHIP_REVISION_4O_PRODUCTION, 0
 470              	.set CYDEV_CHIP_REVISION_4P_PRODUCTION, 0
 471              	.set CYDEV_CHIP_REVISION_4Q_PRODUCTION, 0
 472              	.set CYDEV_CHIP_REVISION_4R_PRODUCTION, 0
 473              	.set CYDEV_CHIP_REVISION_4S_PRODUCTION, 0
 474              	.set CYDEV_CHIP_REVISION_4T_PRODUCTION, 0
 475              	.set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0
 476              	.set CYDEV_CHIP_REVISION_4V_PRODUCTION, 0
 477              	.set CYDEV_CHIP_REVISION_4W_PRODUCTION, 0
 478              	.set CYDEV_CHIP_REVISION_4X_PRODUCTION, 0
 479              	.set CYDEV_CHIP_REVISION_4Y_PRODUCTION, 0
 480              	.set CYDEV_CHIP_REVISION_4Z_PRODUCTION, 0
 481              	.set CYDEV_CHIP_REVISION_5A_ES0, 0
 482              	.set CYDEV_CHIP_REVISION_5A_ES1, 1
 483              	.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1
 484              	.set CYDEV_CHIP_REVISION_5B_ES0, 0
 485              	.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0
 486              	.set CYDEV_CHIP_REVISION_6A_ES, 17
 487              	.set CYDEV_CHIP_REVISION_6A_NO_UDB, 33
 488              	.set CYDEV_CHIP_REVISION_6A_PRODUCTION, 33
 489              	.set CYDEV_CHIP_REVISION_FM3_PRODUCTION, 0
 490              	.set CYDEV_CHIP_REVISION_FM4_PRODUCTION, 0
 491              	.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION, 0
 492              	.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION, 0
 493              	.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION, 0
 494              	.set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_5B_PRODUCTION
 495              	.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REVISION_USED
 496              	.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1
 497              	.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0
 498              	.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn
 499              	.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 198


 500              	.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2
 501              	.set CYDEV_CONFIGURATION_COMPRESSED, 1
 502              	.set CYDEV_CONFIGURATION_DMA, 0
 503              	.set CYDEV_CONFIGURATION_ECC, 1
 504              	.set CYDEV_CONFIGURATION_IMOENABLED, CYDEV_CONFIG_FASTBOOT_ENABLED
 505              	.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0
 506              	.set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED
 507              	.set CYDEV_CONFIGURATION_MODE_DMA, 2
 508              	.set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1
 509              	.set CYDEV_DEBUG_ENABLE_MASK, 0x20
 510              	.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG
 511              	.set CYDEV_DEBUGGING_DPS_Disable, 3
 512              	.set CYDEV_DEBUGGING_DPS_JTAG_4, 1
 513              	.set CYDEV_DEBUGGING_DPS_JTAG_5, 0
 514              	.set CYDEV_DEBUGGING_DPS_SWD, 2
 515              	.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6
 516              	.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV
 517              	.set CYDEV_DEBUGGING_ENABLE, 1
 518              	.set CYDEV_DEBUGGING_XRES, 0
 519              	.set CYDEV_DMA_CHANNELS_AVAILABLE, 24
 520              	.set CYDEV_ECC_ENABLE, 0
 521              	.set CYDEV_HEAP_SIZE, 0x80
 522              	.set CYDEV_INSTRUCT_CACHE_ENABLED, 1
 523              	.set CYDEV_INTR_RISING, 0x00008000
 524              	.set CYDEV_IS_EXPORTING_CODE, 0
 525              	.set CYDEV_IS_IMPORTING_CODE, 0
 526              	.set CYDEV_PROJ_TYPE, 0
 527              	.set CYDEV_PROJ_TYPE_BOOTLOADER, 1
 528              	.set CYDEV_PROJ_TYPE_LAUNCHER, 5
 529              	.set CYDEV_PROJ_TYPE_LOADABLE, 2
 530              	.set CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER, 4
 531              	.set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3
 532              	.set CYDEV_PROJ_TYPE_STANDARD, 0
 533              	.set CYDEV_PROTECTION_ENABLE, 0
 534              	.set CYDEV_STACK_SIZE, 0x0800
 535              	.set CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP, 1
 536              	.set CYDEV_USE_BUNDLED_CMSIS, 1
 537              	.set CYDEV_VARIABLE_VDDA, 0
 538              	.set CYDEV_VDDA_MV, 5000
 539              	.set CYDEV_VDDD_MV, 5000
 540              	.set CYDEV_VDDIO0_MV, 5000
 541              	.set CYDEV_VDDIO1_MV, 5000
 542              	.set CYDEV_VDDIO2_MV, 5000
 543              	.set CYDEV_VDDIO3_MV, 5000
 544              	.set CYDEV_VIO0_MV, 5000
 545              	.set CYDEV_VIO1_MV, 5000
 546              	.set CYDEV_VIO2_MV, 5000
 547              	.set CYDEV_VIO3_MV, 5000
 548              	.set CYIPBLOCK_ARM_CM3_VERSION, 0
 549              	.set CYIPBLOCK_P3_ANAIF_VERSION, 0
 550              	.set CYIPBLOCK_P3_CAN_VERSION, 0
 551              	.set CYIPBLOCK_P3_CAPSENSE_VERSION, 0
 552              	.set CYIPBLOCK_P3_COMP_VERSION, 0
 553              	.set CYIPBLOCK_P3_DECIMATOR_VERSION, 0
 554              	.set CYIPBLOCK_P3_DFB_VERSION, 0
 555              	.set CYIPBLOCK_P3_DMA_VERSION, 0
 556              	.set CYIPBLOCK_P3_DRQ_VERSION, 0
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 199


 557              	.set CYIPBLOCK_P3_DSM_VERSION, 0
 558              	.set CYIPBLOCK_P3_EMIF_VERSION, 0
 559              	.set CYIPBLOCK_P3_I2C_VERSION, 0
 560              	.set CYIPBLOCK_P3_LCD_VERSION, 0
 561              	.set CYIPBLOCK_P3_LPF_VERSION, 0
 562              	.set CYIPBLOCK_P3_OPAMP_VERSION, 0
 563              	.set CYIPBLOCK_P3_PM_VERSION, 0
 564              	.set CYIPBLOCK_P3_SCCT_VERSION, 0
 565              	.set CYIPBLOCK_P3_TIMER_VERSION, 0
 566              	.set CYIPBLOCK_P3_USB_VERSION, 0
 567              	.set CYIPBLOCK_P3_VIDAC_VERSION, 0
 568              	.set CYIPBLOCK_P3_VREF_VERSION, 0
 569              	.set CYIPBLOCK_S8_GPIO_VERSION, 0
 570              	.set CYIPBLOCK_S8_IRQ_VERSION, 0
 571              	.set CYIPBLOCK_S8_SAR_VERSION, 0
 572              	.set CYIPBLOCK_S8_SIO_VERSION, 0
 573              	.set CYIPBLOCK_S8_UDB_VERSION, 0
 574              	.set DMA_CHANNELS_USED__MASK0, 0x00000000
 575              	.set CYDEV_BOOTLOADER_ENABLE, 0
 576              	.endif
  17              	
  18              	.syntax unified
  19              	.text
  20              	.thumb
  21              	
  22              	
  23              	/*******************************************************************************
  24              	* Function Name: CyDelayCycles
  25              	****************************************************************************//**
  26              	*
  27              	*  Delays for the specified number of cycles.
  28              	*
  29              	*  \param uint32 cycles: number of cycles to delay.
  30              	*
  31              	*******************************************************************************/
  32              	/* void CyDelayCycles(uint32 cycles) */
  33              	.align 3                    /* Align to 8 byte boundary (2^n) */
  34              	.global CyDelayCycles
  35              	.func CyDelayCycles, CyDelayCycles
  36              	.type CyDelayCycles, %function
  37              	.thumb_func
  38              	CyDelayCycles:              /* cycles bytes */
  39              	/* If ICache is enabled */
  40              	.ifeq CYDEV_INSTRUCT_CACHE_ENABLED - 1
  41              	
  42 0000 0230     	    ADDS r0, r0, #2           /*  1    2   Round to nearest multiple of 4 */
  43 0002 8008     	    LSRS r0, r0, #2           /*  1    2   Divide by 4 and set flags */
  44 0004 03D0     	    BEQ CyDelayCycles_done    /*  2    2   Skip if 0 */
  45 0006 00BF     	    NOP                       /*  1    2   Loop alignment padding */
  46              	
  47              	CyDelayCycles_loop:
  48 0008 0138     	    SUBS r0, r0, #1           /*  1    2 */
  49 000a 0046     	    MOV r0, r0                /*  1    2   Pad loop to power of two cycles */
  50 000c FCD1     	    BNE CyDelayCycles_loop    /*  2    2 */
  51              	
  52              	CyDelayCycles_done:
  53 000e 7047     	    BX lr                     /*  3    2 */
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 200


  54              	
  55              	.else
  56              	
  57              	    CMP r0, #20               /*  1    2   If delay is short - jump to cycle */
  58              	    BLS CyDelayCycles_short   /*  1    2  */
  59              	    PUSH {r1}                 /*  2    2   PUSH r1 to stack */
  60              	    MOVS r1, #1               /*  1    2  */
  61              	
  62              	    SUBS r0, r0, #20          /*  1    2   Subtract overhead */
  63              	    LDR r1,=CYREG_CACHE_CC_CTL/*  2    2   Load flash wait cycles value */
  64              	    LDRB r1, [r1, #0]         /*  2    2  */
  65              	    ANDS r1, #0xC0            /*  1    2  */
  66              	
  67              	    LSRS r1, r1, #6           /*  1    2  */
  68              	    PUSH {r2}                 /*  1    2   PUSH r2 to stack */
  69              	    LDR r2, =cy_flash_cycles  /*  2    2  */
  70              	    LDRB r1, [r2, r1]         /*  2    2  */
  71              	
  72              	    POP {r2}                  /*  2    2   POP r2 from stack */
  73              	    NOP                       /*  1    2   Alignment padding */
  74              	    NOP                       /*  1    2   Alignment padding */
  75              	    NOP                       /*  1    2   Alignment padding */
  76              	
  77              	CyDelayCycles_loop:
  78              	    SBCS r0, r0, r1           /*  1    2  */
  79              	    BPL CyDelayCycles_loop    /*  3    2  */
  80              	    NOP                       /*  1    2   Loop alignment padding */
  81              	    NOP                       /*  1    2   Loop alignment padding */
  82              	
  83              	    POP {r1}                  /*  2    2   POP r1 from stack */
  84              	CyDelayCycles_done:
  85              	    BX lr                     /*  3    2  */
  86              	    NOP                       /*  1    2   Alignment padding */
  87              	    NOP                       /*  1    2   Alignment padding */
  88              	
  89              	CyDelayCycles_short:
  90              	    SBCS r0, r0, #4           /*  1    2  */
  91              	    BPL CyDelayCycles_short   /*  3    2  */
  92              	    BX lr                     /*  3    2  */
  93              	
  94              	cy_flash_cycles:
  95              	.byte 0x0B
  96              	.byte 0x05
  97              	.byte 0x07
  98              	.byte 0x09
  99              	.endif
 100              	
 101              	.endfunc
 102              	
 103              	
 104              	/*******************************************************************************
 105              	* Function Name: CyEnterCriticalSection
 106              	****************************************************************************//**
 107              	*
 108              	*  CyEnterCriticalSection disables interrupts and returns a value indicating
 109              	*  whether interrupts were previously enabled (the actual value depends on
 110              	*  whether the device is PSoC 3 or PSoC 5).
ARM GAS  Generated_Source\PSoC5\CyBootAsmGnu.s 			page 201


 111              	*
 112              	*  Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
 113              	*  with interrupts still enabled. The test and set of the interrupt bits is not
 114              	*  atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid
 115              	*  corrupting processor state, it must be the policy that all interrupt routines
 116              	*  restore the interrupt enable bits as they were found on entry.
 117              	*
 118              	* \return
 119              	*  uint8
 120              	*   Returns 0 if interrupts were previously enabled or 1 if interrupts
 121              	*   were previously disabled.
 122              	*
 123              	*******************************************************************************/
 124              	/* uint8 CyEnterCriticalSection(void) */
 125              	.global CyEnterCriticalSection
 126              	.func CyEnterCriticalSection, CyEnterCriticalSection
 127              	.type CyEnterCriticalSection, %function
 128              	.thumb_func
 129              	CyEnterCriticalSection:
 130 0010 EFF31080 	    MRS r0, PRIMASK         /* Save and return interrupt state */
 131 0014 72B6     	    CPSID I                 /* Disable interrupts */
 132 0016 7047     	    BX lr
 133              	.endfunc
 134              	
 135              	
 136              	/*******************************************************************************
 137              	* Function Name: CyExitCriticalSection
 138              	****************************************************************************//**
 139              	*
 140              	*  CyExitCriticalSection re-enables interrupts if they were enabled before
 141              	*  CyEnterCriticalSection was called. The argument should be the value returned
 142              	*  from CyEnterCriticalSection.
 143              	*
 144              	*  \param uint8 savedIntrStatus:
 145              	*   Saved interrupt status returned by the CyEnterCriticalSection function.
 146              	*
 147              	*******************************************************************************/
 148              	/* void CyExitCriticalSection(uint8 savedIntrStatus) */
 149              	.global CyExitCriticalSection
 150              	.func CyExitCriticalSection, CyExitCriticalSection
 151              	.type CyExitCriticalSection, %function
 152              	.thumb_func
 153              	CyExitCriticalSection:
 154 0018 80F31088 	    MSR PRIMASK, r0         /* Restore interrupt state */
 155 001c 7047     	    BX lr
 156              	.endfunc
 157              	
 158 001e 00BF     	.end
