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* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*May 22, 2017
*ECN S17-0803, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT Si8481DB D G S 
M1 3 GX S S PMOS W= 3210000u L= 0.30u 
M2 S GX S D NMOS W= 3210000u L= 0.28u 
R1 D 3 1.001e-02 2.260e-03 5.035e-07 
CGS GX S 1.478e-09 
CGD GX D 8.836e-11 
RG G GY 1m 
RTCV 100 S 1e6 -0.117e-04 -1.039e-06 
ETCV GY GX 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD D S DBD 3210000u 
*********************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 2e-8 
+ RS = 0 KP = 5.406e-06 NSUB = 1.000e+13 
+ KAPPA = 3.632e-06 NFS = 1.044e+09 
+ LD = 0 IS = 0 TPG = -1 CAPOP = 12 ) 
***********************************************  
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 2e-8 
+NSUB = 4.562e+16 IS = 0 TPG = -1 CAPOP = 12 ) 
*********************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 5e-8 TREF = 25 BV = 21 
+RS = 8.567e-02 N = 1.227e+00 IS = 1.008e-08 
+EG = 1.050e+00 XTI = -7.381e+00 TRS = 1.000e-05 
+CJO = 6.620e-11 VJ = 3.000e-01 M = 3.718e-01 ) 
.ENDS 
