********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Apr 24, 2017
*ECN S17-0596, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiRC16DP D G S 
X1 D G S SiRC16DP_nm 
X2 S D   SiRC16DP_schottky 
.ENDS SiRC16DP 
.SUBCKT SiRC16DP_nm D G S 
M1 3 GX S S NMOS W= 13567500u L= 0.30u 
M2 S GX S D PMOS W= 13567500u L= 0.13u 
R1 D 3 6.492e-04 3.340e-03 9.990e-06 
CGS GX S 2.546e-09 
CGD GX D 1.000e-12 
RG G GY 1m 
RTCV 100 S 1e6 -1.015e-03 -6.853e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 1.552e-05 NSUB = 8.307e+16 
+ KAPPA = 1.777e-01 NFS = 1.000e+10 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 4.994e+16 IS = 0 TPG = -1 CAPOP = 12 ) 
**************************************************************** 
.ENDS SiRC16DP_nm
.subckt SiRC16DP_schottky 7 5 
d1 7 5 sdsm 
d2 7 5 sdlg 
d3 7 4 sdrev 
d4 5 4 sdblk 
.MODEL sdsm d (IS = 3.058e-12 N = 8.643e-01 EG = 9.066e-01 
+XTI = 3.405e+00 RS = 2.235e-03 TRS = 0. ) 
.MODEL sdlg d (IS = 9.414e-06 N = 1.019e+00 EG = 5.844e-01 
+XTI = 9.779e-03 RS = 2.000e-02 TRS = 0. 
+VJ = 2.190e+00 CJO = 5.113e-09 M = 6.540e-01 
+TT = 1.201e-08 ) 
.MODEL sdrev d (IS = 6.686e-06 N = 1.434e+00 EG = 5.000e-01 
+XTI = 1.173e+01 ) 
.MODEL sdblk d (IS = 1e-11 N=1) 
.ends SiRC16DP_schottky 
