********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*05-Nov-2018
*ECN S18-1113, Rev. A
*File Name: SiRA14BDP_PS.txt and SiRA14BDP_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiRA14BDP D G S 
M1 3 GX S S NMOS W= 2960000u L= 0.30u 
M2 S GX S D PMOS W= 2960000u L= 0.14u 
R1 D 3 2.850e-03 TC=3.646e-03,3.627e-06
CGS GX S 4.241e-10 
CGD GX D 1.008e-13 
RG G GY 2.8 
RTCV 100 S 1e6 TC=3.571e-04,-0.604e-05
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 2960000u 
*************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 1.699e-05 NSUB = 9.8888e+16 
+ KAPPA = 2.145e-01 NFS = 2.000e+011 
+ LD = 0 IS = 0 TPG = 1    )
*************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 1.928e+16 IS = 0 TPG = -1    )
*************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 1.949e-08 T_measured = 25 BV = 31
+RS = 6.064e-03 N = 9.969e-01 IS = 3.364e-13 
+EG = 1.166e+00 XTI = 1.290e+00 TRS1 = 1.876e-03
+CJO = 4.274e-10 VJ = 6.092e+00 M = 1.000e+00 ) 
.ENDS 
