********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Feb 22, 2016
*ECN S16-0299, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiUD402ED D G S 
x1 D G S SiUD402ED_mos
x2 G S   SiUD402ED_esd
.ENDS SiUD402ED
.SUBCKT SiUD402ED_mos D G S 
M1 3 GX S S NMOS W= 15066u L= 0.30u 
M2 S GX S D PMOS W= 15066u L= 0.27u 
R1 D 3 3.2489e-01 4.824e-03 6.961e-06
CGS GX S 10.252e-12 
CGD GX D 2.465e-12 
RG G GY 1m 
RTCV 100 S 1e6 9.726e-04 -7.703e-06
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 15066u 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 1.7e-8 
+ RS = 0 KP = 4.1422e-05 NSUB = 1.0e+17 
+ KAPPA = 8.016e-02 NFS = 1.000e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12   )
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 1.7e-8 
+NSUB = 5.816e+16 IS = 0 TPG = -1 CAPOP = 12   )
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 2.000e-08 TREF = 25 BV = 21
+RS = 5.689e-03 N = 1.383e+00 IS = 1.000e-06 
+EG = 1.054e+00 XTI = -7.897e+00 TRS = 6.354e-04
+CJO = 6.913e-10 VJ = 5.493e-01 M = 3.208e-01 )
.ENDS SiUD402ED_mos
.subckt SiUD402ED_esd 1 2 
r1 1 9 1.0237e+00 -3.000e-03
d1 9 2 dleak
.MODEL dleak d (IS = 4.054e-9 XTI = 3.582e+02 EG = 1.17 
+ TREF = 25 TCV = 0 N = 4.62983e+01 BV = 50) 
r2 1 10 1.60662e+01 -2.232e-03
d3 11 10 dout 
d4 11 2 dout 
.MODEL dout D (IS = 1.5160e-9 XTI= 100.4291e-01 EG = 1.17
+ TREF = 25 TCV = -4.5386e-04 N = 5.5e+00 BV = 9.65e+00 TLEV = 1)
.ends SiUD402ED_esd