********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*Sep 18, 2017
*ECN S17-1459, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiDR220DP D G S 
M1 3 GX S S NMOS W= 23850000u L= 0.30u 
M2 S GX S D PMOS W= 23850000u L= 0.11u 
R1 D 3 3.490e-04 1.710e-03 3.973e-06 
CGS GX S 4.965e-09 
CGD GX D 1.000e-13 
RG G GY 0.38 
RTCV 100 S 1e6 2.478e-04 1.096e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 23850000u 
***********************************************  
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 4e-8 
+ RS = 0 KP = 1.603e-05 NSUB = 1.152e+17 
+ KAPPA = 1.000e-4 NFS = 6.0340e+10 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
*********************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 4e-8 
+NSUB = 8.136e+16 IS = 0 TPG = -1 CAPOP = 12 ) 
*********************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 2.000e-08 TREF = 25 BV = 26 
+RS = 7.572e-03 N = 1.067e+00 IS = 1.393e-12 
+EG = 8.652e-01 XTI = 9.978e+00 TRS = 1.000e-05 
+CJO = 2.964e-10 VJ = 3.231e+00 M = 6.979e-01 ) 
.ENDS 
