********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*08-Oct-2018
*ECN S18-1030, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT  SiS932EDN D G S 
x1 D G S SiS932EDN_mos
x2 G S   SiS932EDN_esd
.ENDS SiS932EDN
.SUBCKT SiS932EDN_mos D G S 
M1 3 GX S S NMOS W= 1478896u L= 0.30u 
M2 S GX S D PMOS W= 1478896u L= 0.27u 
R1 D 3 1.480e-02 4.841e-03 5.982e-06 
CGS GX S 6.599e-10 
CGD GX D 4.375e-11 
RG G GY 3.1 
RTCV 100 S 1e6 1.051e-05 1.643e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 1478896u 
*************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 3e-8 
+ RS = 0 KP = 2.250e-05 NSUB = 1.085e+17 
+ KAPPA = 5.752e-04 NFS = 3.064e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 3e-8 
+NSUB = 5.411e+15 IS = 0 TPG = -1 CAPOP = 12 ) 
***************************************************************
.MODEL DBD D ( 
+FC = 0.1 TT = 1.601e-08 TREF = 25 BV = 31 
+RS = 2.090e-02 N = 1.098e+00 IS = 1.175e-10 
+EG = 1.015e+00 XTI = 4.054e-01 TRS = 8.824e-04 
+CJO = 2.077e-10 VJ = 3.212e-01 M = 4.177e-01 ) 
.ENDS SiS932EDN_mos
.subckt SiS932EDN_esd 1 2
r1 1 9 2.518e+05 TC= -5.594e-03 
d1 9 2 dleak 
.MODEL dleak d (IS = 3.000e-10 XTI = 4.769e+02 EG = 1.17 
+ TREF = 25 TCV = 0 N = 3.724e+01 BV = 50) 
r2 1 10 4.743e+00 TC= 5.166e-03 
d3 11 10 dout 
d4 11 2 dout 
.MODEL dout D (IS = 4.518e-12 XTI = 4.924e+01 EG = 1.17 
+ TREF = 25 TCV = -5.012e-03 N = 3.437e+00 BV = 1.124e+01 ) 
.ends SiS932EDN_esd