********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*Mar 19, 2018
*ECN S18-0319, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiS110DN D G S 
M1 3 GX S S NMOS W= 1337500u L= 0.30u 
M2 S GX S D PMOS W= 1337500u L= 0.20u 
R1 D 3 3.745e-02 7.650e-03 1.050e-05 
CGS GX S 4.125e-10 
CGD GX D 2.232e-12 
RG G GY 1.3 
RTCV 100 S 1e6 1.508e-03 -.073e-04 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 1337500u 
*********************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 7e-8 
+ RS = 0 KP = 5.997e-06 NSUB = 1.073e+17 
+ KAPPA = 2.380e-03 NFS = 1.318e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
***********************************************  
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 7e-8 
+NSUB = 2.227e+15 IS = 0 TPG = -1 CAPOP = 12 ) 
*********************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 2.000e-07 TREF = 25 BV = 101 
+RS = 5.448e-03 N = 1.455e+00 IS = 1.337e-09 
+EG = 1.146e+00 XTI = 1.517e+00 TRS = 2.803e-03 
+CJO = 5.004e-10 VJ = 1.837e+00 M = 8.097e-01 ) 
.ENDS 
