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* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*Dec 18, 2017
*ECN S17-1848, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiSS42DN D G S 
M1 3 GX S S NMOS W= 4265000u L= 0.30u 
M2 S GX S D PMOS W= 4265000u L= 0.18u 
R1 D 3 9.930e-03 7.937e-03 3.247e-05 
CGS GX S 1.296e-09 
CGD GX D 1.000e-13 
RG G GY 0.85m 
RTCV 100 S 1e6 1.224e-03 1.14e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 4265000u 
************************************************  
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 7e-8 
+ RS = 0 KP = 5.503e-06 NSUB = 1.199e+17 
+ KAPPA = 1.259e-01 NFS = 1.921e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
************************************************ 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 7e-8 
+NSUB = 3.196e+15 IS = 0 TPG = -1 CAPOP = 12 ) 
************************************************ 
.MODEL DBD D ( 
+FC = 0.1 TT = 4.704e-08 TREF = 25 BV = 101 
+RS = 4.119e-03 N = 1.251e+00 IS = 5.263e-11 
+EG = 1.210e+00 XTI = 1.554e-02 TRS = 3.030e-03 
+CJO = 5.072e-10 VJ = 9.666e-01 M = 6.801e-01 ) 
.ENDS 
