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* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*Oct 30, 2017
*ECN S17-1646, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiDR622DP D G S 
M1 3 GX S S NMOS W= 4597268u L= 0.30u 
M2 S GX S D PMOS W= 4597268u L= 0.28u 
R1 D 3 1.092e-02 8.089e-03 2.697e-05 
CGS GX S 1.079e-09 
CGD GX D 1.000e-13 
RG G GY 1.8 
RTCV 100 S 1e6 1.0869e-03 3.870e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 4597268u 
************************************************* 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 10e-8 
+ RS = 0 KP = 3.170e-06 NSUB = 1.11e+17 
+ KAPPA = 1.0524e-01 NFS = 4.550e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
************************************************* 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 10e-8 
+NSUB = 2.4713e+16 IS = 0 TPG = -1 CAPOP = 12 ) 
************************************************* 
.MODEL DBD D ( 
+FC = 0.1 TT = 1.000e-07 TREF = 25 BV = 151 
+RS = 7.557e-03 N = 1.130e+00 IS = 3.279e-12 
+EG = 1.224e+00 XTI = 4.867e-01 TRS = 2.827e-03 
+CJO = 8.511e-10 VJ = 4.966e+00 M = 1.000e+00 ) 
.ENDS 
