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* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*Apr 24, 2017
*ECN S17-0588, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT Si5448DU D G S 
M1 3 GX S S NMOS W= 3346000u L= 0.30u 
M2 S GX S D PMOS W= 3346000u L= 0.21u 
R1 D 3 5.483e-03 3.930e-03 1.059e-05 
CGS GX S 1.209e-09 
CGD GX D 1.000e-13 
RG G GY 1m 
RTCV 100 S 1e6 7.807e-04 -1.716e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 3346000u 
*************************************************  
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 1.114e-05 NSUB = 7.69e+16 
+ KAPPA = 1.399e-01 NFS = 1.003e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
*************************************************  
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 1.608e+16 IS = 0 TPG = -1 CAPOP = 12 ) 
*************************************************  
.MODEL DBD D ( 
+FC = 0.1 TT = 3.194e-08 TREF = 25 BV = 41 
+RS = 1.352e-02 N = 1.169e+00 IS = 2.414e-11 
+EG = 8.122e-01 XTI = 9.991e+00 TRS = 1.000e-05 
+CJO = 2.721e-10 VJ = 7.640e+00 M = 9.990e-01 ) 
.ENDS 
