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* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*24-Sep-2018
*ECN S18-0975, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiRA12BDP D G S 
M1 3 GX S S NMOS W= 4057500u L= 0.30u 
M2 S GX S D PMOS W= 4057500u L= 0.18u 
R1 D 3 2.108e-03 3.920e-03 5.031e-06 
CGS GX S 6.071e-10 
CGD GX D 1.000e-13 
RG G GY 1.4 
RTCV 100 S 1e6 7.136e-04 -1.056e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 4057500u 
*********************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 1.214e-05 NSUB = 1.326e+17 
+ KAPPA = 9.996e-02 NFS = 4.058e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
*********************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 9.920e+15 IS = 0 TPG = -1 CAPOP = 12 ) 
*********************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 4.259e-08 TREF = 25 BV = 31 
+RS = 4.213e-03 N = 1.096e+00 IS = 1.210e-12 
+EG = 1.141e+00 XTI = 1.705e+00 TRS = 5.567e-03 
+CJO = 4.327e-10 VJ = 5.964e+00 M = 9.990e-01 ) 
.ENDS 
