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* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*17-Sep-2018
*ECN S18-0958, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiJA72ADP D G S 
M1 3 GX S S NMOS W= 5820000u L= 0.30u 
M2 S GX S D PMOS W= 5820000u L= 0.040u 
R1 D 3 2.317e-03 3.462e-03 1.734e-05 
CGS GX S 1.595e-09 
CGD GX D 1.000e-13 
RG G GY 1.3 
RTCV 100 S 1e6 3.068e-04 5.938e-07 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 5820000u 
************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 1.111e-05 NSUB = 8.717e+16 
+ KAPPA = 2.092e-01 NFS = 1.003e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 2.009e+17 IS = 0 TPG = -1 CAPOP = 12 ) 
************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 2.291e-08 TREF = 25 BV = 41 
+RS = 8.956e-03 N = 1.170e+00 IS = 3.336e-11 
+EG = 8.548e-01 XTI = 9.993e+00 TRS = 1.000e-05 
+CJO = 2.812e-10 VJ = 7.266e+00 M = 9.276e-01 ) 
.ENDS 
