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* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*13-Aug-2018
*ECN S18-0817, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiRA58ADP D G S 
M1 3 GX S S NMOS W= 6920000u L= 0.30u 
M2 S GX S D PMOS W= 6920000u L= 0.072u 
R1 D 3 1.700e-03 3.725e-03 1.827e-05 
CGS GX S 1.999e-09 
CGD GX D 1.000e-13 
RG G GY 1.4 
RTCV 100 S 1e6 1.266e-03 1.174e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 6920000u 
**************************************************  
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 9.394e-06 NSUB = 7.990e+16 
+ KAPPA = 5.073e-02 NFS = 1.009e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 3.967e+16 IS = 0 TPG = -1 CAPOP = 12 ) 
**************************************************  
.MODEL DBD D ( 
+FC = 0.1 TT = 3.088e-08 TREF = 25 BV = 41 
+RS = 1.115e-02 N = 9.388e-01 IS = 1.078e-13 
+EG = 1.495e+00 XTI = -9.765e+00 TRS = 3.626e-03 
+CJO = 2.702e-10 VJ = 8.119e+00 M = 1.000e+00 ) 
.ENDS 
