********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*10-Dec-2018
*ECN S18-1214, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT Si7322ADN D G S 
M1 3 GX S S NMOS W= 670054u L= 0.30u 
M2 S GX S D PMOS W= 670054u L= 0.39u 
R1 D 3 3.450e-02 6.767e-03 2.382e-05 
CGS GX S 2.800e-10 
CGD GX D 5.879e-12 
RG G GY 1m 
RTCV 100 S 1e6 1.758e-03 5.529e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 670054u 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 6.899e-06 NSUB = 1.943e+17 
+ KAPPA = 3.067e-02 NFS = 1.525e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 2.172e+16 IS = 0 TPG = -1 CAPOP = 12 ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 5.830e-08 TREF = 25 BV = 101 
+RS = 5.146e-03 N = 1.068e+00 IS = 1.333e-12 
+EG = 1.228e+00 XTI = 6.069e-01 TRS = 3.010e-03 
+CJO = 5.442e-10 VJ = 7.308e+00 M = 6.529e-01 ) 
.ENDS 
