********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*10-Dec-2018
*ECN S18-1217, Rev. A
*File Name: SiR167DP_PS.txt and SiR167DP_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR167DP D G S 
M1 3 GX S S PMOS W= 10200000u L= 0.30u 
M2 S GX S D NMOS W= 10200000u L= 0.22u 
R1 D 3 3.190e-03 TC=4.355e-03,1.014e-05
CGS GX S 3.238e-09 
CGD GX D 2.748e-10 
RG G GY 1.6 
RTCV 100 S 1e6 TC=1.018e-05,-1.153e-07
ETCV GY GX 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD D S DBD 10200000u 
************************************************* 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 6.5e-8 
+ RS = 0 KP = 2.556e-06 NSUB = 1.506e+16 
+ KAPPA = 3.081e-03 NFS = 1.001e+11 
+ LD = 0 IS = 0 TPG = -1    )
************************************************* 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 6.5e-8 
+NSUB = 1.487e+16 IS = 0 TPG = -1    )
************************************************* 
.MODEL DBD D ( 
+FC = 0.1 TT = 5e-8 T_measured = 25 BV = 31
+RS = 1.508e-02 N = 1.055e+00 IS = 2.192e-12 
+EG = 1.253e+00 XTI = -4.669e+00 TRS1 = 9.237e-04
+CJO = 3.295e-11 VJ = 1.232e+00 M = 6.008e-01 ) 
.ENDS 
