********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*25-Jun-2018
*ECN S18-0628, Rev. A
*File Name: SiRA10BDP_PS.txt and SiRA10BDP_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiRA10BDP D G S 
M1 3 GX S S NMOS W= 5060000u L= 0.30u 
M2 S GX S D PMOS W= 5060000u L= 0.18u 
R1 D 3 1.6033e-03 TC=3.606e-03,1.038e-05
CGS GX S 6.518e-10 
CGD GX D 1.000e-13 
RG G GY 1.3 
RTCV 100 S 1e6 TC=4.02e-04,-1.510e-07
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 5060000u 
*************************************************  
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 1.127e-05 NSUB = 7.153e+16 
+ KAPPA = 1.175e-02 NFS = 1.020e+11 
+ LD = 0 IS = 0 TPG = 1    )
************************************************* 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 2.076e+16 IS = 0 TPG = -1    )
************************************************* 
.MODEL DBD D ( 
+FC = 0.1 TT = 9.104e-08 T_measured = 25 BV = 31
+RS = 6.413e-03 N = 1.132e+00 IS = 5.116e-12 
+EG = 1.180e+00 XTI = 4.237e-03 TRS1 = 1.020e-03
+CJO = 2.770e-10 VJ = 7.261e+00 M = 1.000e+00 ) 
.ENDS 
