********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*14-May-2018
*ECN S18-0509, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiUD412ED D G S 
x1 D G S SiUD412ED_mos
x2 G S   SiUD412ED_esd
.ENDS SiUD412ED
.SUBCKT SiUD412ED_mos D G S 
M1 3 GX S S NMOS W= 15066u L= 0.30u 
M2 S GX S D PMOS W= 15066u L= 0.60u 
R1 D 3 2.099e-01 3.635e-03 9.966e-06 
CGS GX S 1.770e-11 
CGD GX D 1.000e-13 
RG G GY 15 
RTCV 100 S 1e6 2.200e-04 -3.913e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 15066u 
********************************************************* 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 1.3e-8 
+ RS = 0 KP = 8.825e-05 NSUB = 1.121e+17 
+ KAPPA = 1.020e-03 NFS = 1.060e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
********************************************************* 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 1.3e-8 
+NSUB = 6.006e+17 IS = 0 TPG = -1 CAPOP = 12 ) 
********************************************************* 
.MODEL DBD D ( 
+FC = 0.1 TT = 2.000e-07 TREF = 25 BV = 12.2 
+RS = 2.219e-03 N = 1.328e+00 IS = 5.570e-09 
+EG = 9.592e-01 XTI = 1.002e+00 TRS = 1.000e-05 
+CJO = 8.896e-10 VJ = 1.188e+00 M = 4.468e-01 ) 
.ENDS SiUD412ED_mos
.subckt SiUD412ED_esd 1 2 
r1 1 9 3.411e+04 -4.290e-03 
d1 9 2 dleak 
.MODEL dleak d (IS = 1.813e-9 XTI = 4.0531e+02 EG = 1.17 
+ TREF = 25 TCV = 0 N = 3.900e+01 BV = 50) 
r2 1 10 3.998e+01 -0.2889e-03 
d3 11 10 dout 
d4 11 2 dout 
.MODEL dout D (IS = 9.158e-10 XTI = -1.959e+02 EG = 1.17 
+ TREF = 25 TCV = 1.609e-03 N = 1.343e+00 BV = 1.1768e+01 
+ TLEV = 1)
.ends SiUD412ED_esd