********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*Apr 09, 2018
*ECN S18-0413, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR104DP D G S 
M1 3 GX S S NMOS W= 10787500u L= 0.30u 
M2 S GX S D PMOS W= 10787500u L= 0.12u 
R1 D 3 4.522e-03 7.989e-03 3.076e-05 
CGS GX S 2.947e-09 
CGD GX D 1.008e-13 
RG G GY 0.90 
RTCV 100 S 1e6 9.843e-04 -4.128e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 10787500u 
************************************************* 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 7e-8 
+ RS = 0 KP = 5.332e-06 NSUB = 1.223e+17 
+ KAPPA = 2.020e-02 NFS = 2.703e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
************************************************* 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 7e-8 
+NSUB = 6.258e+15 IS = 0 TPG = -1 CAPOP = 12 ) 
************************************************* 
.MODEL DBD D ( 
+FC = 0.1 TT = 1.190e-08 TREF = 25 BV = 101 
+RS = 1.400e-02 N = 1.002e+00 IS = 2.971e-13 
+EG = 1.223e+00 XTI = 4.280e-02 TRS = 4.035e-03 
+CJO = 3.163e-10 VJ = 1.771e+00 M = 7.058e-01 ) 
.ENDS 
