********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Mar 19, 2018
*ECN S18-0333, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT Si7434ADP D G S 
M1 3 GX S S NMOS W= 3426592u L= 0.30u 
M2 S GX S D PMOS W= 3426592u L= 0.19u 
R1 D 3 1.174e-01 9.100e-03 2.087e-05 
CGS GX S 3.503e-10 
CGD GX D 1.413e-12 
RG G GY 2.3 
RTCV 100 S 1e6 1.170e-03 -4.307e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 3426592u 
************************************************ 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 10e-8 
+ RS = 0 KP = 1.789e-06 NSUB = 5.361e+16 
+ KAPPA = 2.179e-02 NFS = 1.007e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
************************************************ 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 10e-8 
+NSUB = 1.000e+15 IS = 0 TPG = -1 CAPOP = 12 )  
************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 2.000e-07 TREF = 25 BV = 251 
+RS = 1.683e-02 N = 1.206e+00 IS = 1.208e-11 
+EG = 7.130e-01 XTI = 1.000e+01 TRS = 4.616e-05 
+CJO = 2.290e-10 VJ = 4.668e+00 M = 7.583e-01 ) 
.ENDS 
