********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*Apr 09, 2018
*ECN S18-0414, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR112DP D G S 
M1 3 GX S S NMOS W= 8140000u L= 0.30u 
M2 S GX S D PMOS W= 8140000u L= 0.20u 
R1 D 3 1.393e-03 4.606e-03 1.438e-05 
CGS GX S 2.741e-09 
CGD GX D 1.008e-13 
RG G GY 1  
RTCV 100 S 1e6 1.02e-03 -1.510e-07 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 8140000u 
************************************************ 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 1.8278e-05 NSUB = 9.453e+16 
+ KAPPA = 2.675e-02 NFS = 1.020e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
************************************************ 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 2.184e+16 IS = 0 TPG = -1 CAPOP = 12 ) 
************************************************ 
.MODEL DBD D ( 
+FC = 0.1 TT = 9.104e-08 TREF = 25 BV = 41 
+RS = 1.613e-02 N = 1.102e+00 IS = 5.116e-12 
+EG = 1.180e+00 XTI = 4.237e-03 TRS = 1.020e-03 
+CJO = 2.770e-10 VJ = 7.261e+00 M = 1.000e+00 ) 
.ENDS 
