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* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*Dec 25, 2017
*ECN S17-1903, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR184DP D G S 
M1 3 GX S S NMOS W= 3551250u L= 0.30u 
M2 S GX S D PMOS W= 3551250u L= 0.24u 
R1 D 3 3.450e-03 6.142e-03 3.267e-05 
CGS GX S 1.005e-09 
CGD GX D 1.000e-13 
RG G GY 0.75 
RTCV 100 S 1e6 1.457e-05 -3.373e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 3551250u 
************************************************* 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 7e-8 
+ RS = 0 KP = 9.525e-06 NSUB = 1.139e+17 
+ KAPPA = 8.006e-02 NFS = 1.042e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
************************************************* 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 7e-8 
+NSUB = 3.831e+15 IS = 0 TPG = -1 CAPOP = 12 ) 
************************************************* 
.MODEL DBD D ( 
+FC = 0.1 TT = 3.942e-08 TREF = 25 BV = 61 
+RS = 5.145e-03 N = 1.092e+00 IS = 2.751e-12 
+EG = 1.234e+00 XTI = -4.147e-01 TRS = 4.029e-03 
+CJO = 4.557e-10 VJ = 9.783e+00 M = 1.000e+00 ) 
.ENDS 
