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* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*Dec 25, 2017
*ECN S17-1901, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR140DP D G S 
M1 3 GX S S NMOS W= 23850000u L= 0.30u 
M2 S GX S D PMOS W= 23850000u L= 0.13u 
R1 D 3 4.435e-04 5.129e-03 5.286e-06 
CGS GX S 3.529e-09 
CGD GX D 1.008e-13 
RG G GY 0.38 
RTCV 100 S 1e6 1.008e-05 -.0439e-05 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 23850000u 
**************************************************  
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 1.861e-05 NSUB = 9.526e+16 
+ KAPPA = 9.059e-03 NFS = 2.037e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 3.924e+16 IS = 0 TPG = -1 CAPOP = 12 ) 
************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 8.240e-08 TREF = 25 BV = 26 
+RS = 9.092e-03 N = 9.360e-01 IS = 1.000e-13 
+EG = 8.567e-01 XTI = 9.945e+00 TRS = 1.000e-05 
+CJO = 4.017e-10 VJ = 5.002e+00 M = 8.344e-01 ) 
.ENDS 
