********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*Mar 19, 2018
*ECN S18-0334, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT Si2308CDS  D G S 
M1 3 GX S S NMOS W= 129200u L= 0.30u 
M2 S GX S D PMOS W= 129200u L= 0.17u 
R1 D 3 1.000e-01 4.496e-03 1.105e-05 
CGS GX S 8.990e-11 
CGD GX D 3.183e-12 
RG G GY 1m 
RTCV 100 S 1e6 2.466e-03 .1157e-04 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 129200u 
*************************************************  
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 2.040e-05 NSUB = 1.293e+17 
+ KAPPA = 1.001e-02 NFS = 9.056e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
*************************************************  
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 1.139e+17 IS = 0 TPG = -1 CAPOP = 12 ) 
************************************************* 
.MODEL DBD D ( 
+FC = 0.1 TT = 1.402e-07 TREF = 25 BV = 61 
+RS = 2.654e-03 N = 1.321e+00 IS = 3.192e-10 
+EG = 1.120e+00 XTI = 3.964e+00 TRS = 2.211e-03 
+CJO = 8.525e-10 VJ = 9.024e+00 M = 5.910e-01 ) 
.ENDS 
