********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Jun 19, 2017
*ECN S17-0929, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT Si3440ADV D G S 
M1 3 GX S S NMOS W= 218615u L= 0.30u 
M2 S GX S D PMOS W= 218615u L= 0.36u 
R1 D 3 2.150e-01 8.990e-03 1.076e-05 
CGS GX S 6.896e-11 
CGD GX D 1.008e-13 
RG G GY 1m 
RTCV 100 S 1e6 4.430e-03 -2.080e-05 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 218615u 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 10e-8 
+ RS = 0 KP = 2.121e-06 NSUB = 5.826e+16 
+ KAPPA = 4.109e-03 NFS = 6.063e+11 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 10e-8 
+NSUB = 2.972e+16 IS = 0 TPG = -1 CAPOP = 12 ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 5.000e-08 TREF = 25 BV = 151 
+RS = 5.041e-03 N = 1.161e+00 IS = 1.287e-11 
+EG = 1.232e+00 XTI = 4.766e-01 TRS = 2.898e-03 
+CJO = 1.010e-09 VJ = 7.294e+00 M = 9.990e-01 ) 
.ENDS 
