********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Jan 23, 2017
*ECN S17-0115, Rev. A
*File Name: SiR626DP_PS.txt and SiR626DP_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR626DP D G S 
M1 3 GX S S NMOS W= 12987500u L= 0.30u
M2 S GX S D PMOS W= 12987500u L= 0.20u
R1 D 3 1.046e-03 TC=4.790e-03,1.900e-05
CGS GX S 3.232e-09
CGD GX D 1.000e-13
RG G GY 1m
RTCV 100 S 1e6 TC=1.068e-05,-0.845e-06
ETCV GX GY 100 200 1
ITCV S 100 1u
VTCV 200 S 1
DBD S D DBD 12987500u
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 7e-8 
+ RS = 0 KP = 1.048e-05 NSUB = 1.391e+17 
+ KAPPA = 1.530e-01 NFS = 5.042e+11 
+ LD = 0 IS = 0 TPG = 1    )
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 7e-8 
+NSUB = 7.066e+15 IS = 0 TPG = -1    )
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 1.590e-07 T_measured = 25 BV = 61
+RS = 7.690e-03 N = 1.087e+00 IS = 1.458e-12 
+EG = 1.199e+00 XTI = 2.881e-01 TRS1 = 1.961e-03
+CJO = 3.921e-10 VJ = 7.200e+00 M = 1.000e+00 ) 
.ENDS

