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* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*May 22, 2017
*ECN S17-0801, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT Si4403DDY D G S 
M1 3 GX S S PMOS W= 3402500u L= 0.30u 
M2 S GX S D NMOS W= 3402500u L= 0.44u 
R1 D 3 7.878e-03 2.812e-03 2.554e-06 
CGS GX S 1.767e-09 
CGD GX D 9.621e-11 
RG G GY 1m 
RTCV 100 S 1e6 3.014e-04 1.242e-06 
ETCV GY GX 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD D S DBD 3402500u 
********************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 2e-8 
+ RS = 0 KP = 9.555e-06 NSUB = 1.624e+15 
+ KAPPA = 1.606e-05 NFS = 4.073e+11 
+ LD = 0 IS = 0 TPG = -1 CAPOP = 12 ) 
**********************************************  
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 2e-8 
+NSUB = 2.748e+16 IS = 0 TPG = -1 CAPOP = 12 ) 
**********************************************  
.MODEL DBD D ( 
+FC = 0.1 TT = 5.579e-08 TREF = 25 BV = 21 
+RS = 3.324e-02 N = 1.737e+00 IS = 9.898e-07 
+EG = 9.487e-01 XTI = -2.610e+00 TRS = 1.000e-05 
+CJO = 2.000e-11 VJ = 3.003e-01 M = 4.035e-01 ) 
.ENDS 
