********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Nov 07, 2016
*ECN S16-2185, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR871DP D G S 
M1 3 GX S S PMOS W= 5667120u L= 0.30u 
M2 S GX S D NMOS W= 5667120u L= 0.35u 
R1 D 3 1.338e-02 5.304e-03 8.988e-06 
CGS GX S 2.322e-09 
CGD GX D 1.008e-13 
RG G GY 1m 
RTCV 100 S 1e6 9.957e-04 -9.566e-06 
ETCV GY GX 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD D S DBD 5667120u 
**************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 2.559e-06 NSUB = 4.022e+16 
+ KAPPA = 2.160e-03 NFS = 5.730e+11 
+ LD = 0 IS = 0 TPG = -1 CAPOP = 12 ) 
*************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 1.868e+16 IS = 0 TPG = -1 CAPOP = 12 ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 1.543e-07 TREF = 25 BV = 101 
+RS = 1.050e-02 N = 1.114e+00 IS = 3.986e-12 
+EG = 1.271e+00 XTI = -2.159e+00 TRS = 2.583e-03 
+CJO = 6.286e-10 VJ = 1.456e+01 M = 1.000e+00 ) 
.ENDS 
