*May 20, 2013
*ECN S13-1172, Rev. B
*File Name: SiR424DP_PS.txt and SiR424DP_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet.  Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR424DP D G S 
M1 3 GX S S NMOS W= 2803930u L= 0.25u 
M2 S GX S D PMOS W= 2803930u L= 2.441e-07 
R1 D 3 5.045e-04 TC=2.850e-02 4.064e-05 
CGS GX S 7.403e-10 
CGD GX D 6.407e-11 
RG G GY 1 
RTCV 100 S 1e6 TC=-4.470e-04 -3.364e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 3.417e-03 KP = 1.894e-05 NSUB = 9.565e+16 
+ KAPPA = 2.323e-03 ETA = 5.405e-07 NFS = 1.285e+12 
+ LD = 0 IS = 0 TPG = 1) 
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 3.383e+16 IS = 0 TPG = -1 ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 1.331e-08 T_MEASURED = 25 BV = 21 
+RS = 2.451e-03 N = 1.126e+00 IS = 3.151e-11 
+EG = 9.515e-01 XTI = 5.635e+00 TRS1 = 1.000e-05 
+CJO = 7.469e-10 VJ = 6.135e-01 M = 3.200e-01 ) 
.ENDS 
