********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*May 26, 2014
*ECN S14-1121, Rev. B
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT Si8416DB D G S 
M1 3 GX S S NMOS W= 973309u L= 0.25u 
M2 S GX S D PMOS W= 973309u L= 4.912e-07 
R1 D 3 1.638e-02 3.024e-03 1.086e-06 
CGS GX S 7.261e-10 
CGD GX D 4.503e-11 
RG G GY 2.5 
RTCV 100 S 1e6 -8.374e-05 4.630e-07 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 1.3e-8 
+ RS = 1.050e-03 KP = 5.393e-05 NSUB = 2.602e+17 
+ KAPPA = 4.897e-01 ETA = 1.000e-07 NFS = 1.472e+12 
+ LD = 0 IS = 0 TPG = 1) 
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 1.3e-8 
+NSUB = 3.764e+17 IS = 0 TPG = -1 ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 2.000e-08 TREF = 25 BV = 9 
+RS = 5.208e-02 N = 9.378e-01 IS = 5.869e-11 
+EG = 8.606e-01 XTI = 2.099e-01 TRS = 1.851e-04 
+CJO = 2.887e-10 VJ = 1.483e+00 M = 3.941e-01 ) 
.ENDS 
