Copyright Vishay Intertechnology 2025
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PTCES13-17_series_for_the_web
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author : alain Stas
date :01 Feb 2025
version :1

disclaimer:
===========
Any information, computations, or results generated by the models, or otherwise available from or through the programs,
is provided and utilized at your own discretion and risk. Vishay does not assume any responsibility or liability resulting
from your use of the programs or any such information, computations, or results, and shall have none.
The foregoing is in addition to, and not in limitations of, the exclusions and limitations of liability, and notices and disclaimers, set forth at Vishay Privacy & Legal.
The files contained in the  "PTCES_forweb_Feb2025" are the updated version of the LTspice PTCES spice modelling library.
It has been encrypted to protect Vishay modelling technology.
It is provided as is, without warranty on results obtained by simulation with these models.
Although great care has been provided to the model elaboration for appropriate reproduction of the electrical  and thermal behavior, it is
recommended to always verify the simulation results with real board manufacturing.
The models are suitable for transient, DC and AC simulations within the limits of the specification of the Vishay components.
The modelling of the parameters is made according to a Monte Carlo analysis.
The tolerances on R25 follow the component respective specifications.
For parameters PTCES : see https://www.vishay.com/product/29242
For the last version of LTspice : https://www.analog.com/en/design-center/design-tools-and-calculators/ltspice-simulator.html


usermode:
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- hereunder the complete list of symbols of 10 modelled components
PTCES17R102UTE.asy
PTCES17R121NTE.asy
PTCES17R251STE.asy
PTCES17R501TTE.asy
PTCES17R600MTE.asy
PTCES67R102UTE.asy
PTCES67R151NTE.asy
PTCES67R152UTE.asy
PTCES67R251STE.asy
PTCES67R501TTE.asy

- hereunder some simulations that can be run with these symbols, and associated plots
discharge_PTCES.asc
discharge_PTCES.plt
VIcurvePTCES17.asc
VIcurvePTCES17.log
VIcurvePTCES17.net
VIcurvePTCES17.plt
VIcurvePTCES67.asc
VIcurvePTCES67.log
VIcurvePTCES67.net
VIcurvePTCES67.plt

- the library hereunder is encrypted. Do not modify its name
PTCES_behavior_sept2024_nonencrypted5.txt
- to be used in LTspice IV , XVII 64 bits , or currently the LTSpice 24 (these models are not suitable as such for any other software than LTspice )
- leave all files into one directory without modifications of the .txt file (encrypted library)
- select the requested symbols for the PTCES among the .asy files
- do not forget that during the simulations, the parameters will vary randomly within the limits of their tolerances (+/-30% on the R25)
  So an average behaviour can only be obtained by doing a big number of simulations (in the spice directives add for example ".step param run 1 100 1")
- If you apply higher voltages to the electrical pins than allowed in the data sheet, the simulation results might be not representative of the reality.
- each .asy components has four 3 pins (elec1, elec2, Tptc) as sketched hereunder

               
 elec1    _____________     elec2
 --------[_____________]--------
                |
          +t  _|_|_ -------Tptc PTC internal temperature 
             |_____|


- elec1 and elec2 are the two electrical INPUT pins (without polarity) : to be connected to the electrical circuit
- the PTCES electrical value is depending upon the ambient temperature TEMP, implicitly or explicitely defined in the simulation (.TEMP = 60°C for example)
- As heat is generated inside the PTCES, the PTC internal temperature will increase accordingly, above TEMP.
- The PTC initial temperature is also fixed in any simulation at the value of the ambient temperature TEMP of LTspice (by default 27  C if not specified explicitly)..
- The pin PTC internal temperature is an output pin : if the user wishes to visualize the PTC surface temperature, a LABEL NET must be created and associated to this pin.
- in case of problem: return your simulation file at edesign.ntc@vishay.com
