Copyright Vishay Intertechnology 2023
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PTCEL67_series_for_the_web
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author : alain Stas
date :01 July 2022

disclaimer:
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Any information, computations, or results generated by the models, or otherwise available from or through the programs,
is provided and utilized at your own discretion and risk. Vishay does not assume any responsibility or liability resulting
from your use of the programs or any such information, computations, or results, and shall have none.
The foregoing is in addition to, and not in limitations of, the exclusions and limitations of liability, and notices and disclaimers, set forth at Vishay Privacy & Legal.
The files contained in the  "PTCEL67_series_for_the_web" are the beta version of the LTspice PTCEL67 spice modelling library.
It has been encrypted to protect Vishay modelling technology.
It is provided as is, without warranty on results obtained by simulation with these models.
Although great care has been provided to the model elaboration for appropriate reproduction of the electrical  and thermal behavior, it is
recommended to always verify the simulation results with real board manufacturation.
The models are suitable for transient, DC and AC simulations within the limits of the specification of the Vishay components.
The modelling of the parameters is made according to a Monte Carlo analysis.
The tolerances on R25 follow the component respective specifications.
For parameters PTCEL67 : see https://www.vishay.com/thermistors/list/product-29207/
For the last version of LTspice : https://www.analog.com/en/design-center/design-tools-and-calculators/ltspice-simulator.html


usermode:
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- hereunder the complete list of symbols of modelled components
PTCEL67R151NBE (also valid for NTE)
PTCEL67R251SBE (aso valid for STE)
PTCEL67R501TBE (also valid for TTE, and 305)
PTCEL67R102UBE (also valid for UTE)
PTCEL67R152UBE (also valid for UTE)
- to be used in LTspice IV , XVII 64 bits , currently the 17.1 version of LTSpice (these models are not suitable as such for any other software than LTspice )
- leave all files into one directory without modifications of the .cir file (encrypted library)
- select the requested symbols for the PTCEL67 among the .asy files
- do not forget that during the simulations, the parameters will vary randomly within the limits of their tolerances
  So an average behaviour can only be obtained by doing a big number of simulations (in the spice directives add for example ".step param run 1 100 1")
- If you apply higher voltages to the electrical pins than allowed in the data sheet, the simulation results might be not representative of the reality.
- The maximum number of PTCEL67 that can be simulated in one circuit, is around 9 parts max. Above this, the speed of simulation can become low, especially if some parts are switching.
  (try to execute the simulation "Capa_charge2.asc" with choice of "alternate solver" on your system : the simulation should run after a few seconds)
- each .asy components has four 4 pins (elec1, elec2, Tin and Tsurf) as sketched hereunder

               Tin
 elec1    ______|______     elec2
 --------[_____________]--------
                |
          +t _|_|_ -------PTC surface temperature Tsurf
             |_____|


- elec1 and elec2 are the two electrical INPUT pins (without polarity) : to be connected to the electrical circuit
- Tin is the ambient temperature and must be connected to any voltage source with ,as values, the ambient temperature in C (fixed or time changing)
  The PTC initial temperature is fixed in any simulation at the value of the ambient temperature TEMP of LTspice (by default 27 C if not specified explicitly).
  Thus if the user connects a DC voltage source with amplitude = {TEMP} to the input Tin,the PTC temperature will start at the value of TEMP.
- The pin Tsurf is an output pin : if the user wishes to visualize the PTC surface temperature, a LABEL NET must be created and associated to this pin.
- in case of problem: return your simulation file at edesign.ntc@vishay.com
